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21. 发明授权

US06940133B1 Integrated trim structure utilizing dynamic doping 有权
标题翻译：采用动态掺杂的集成微调结构
公开(公告)号：US06940133B1
公开(公告)日：2005-09-06
申请号：US10818039
申请日：2004-04-05
申请人： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko , Robert Drury
发明人： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko , Robert Drury
IPC分类号： H01C17/26 , H01L21/02 , H01L29/76 , H01L29/8605 , H01L29/94
CPC分类号： H01L28/20 , H01C17/267 , H01L29/8605
摘要： An integrated circuit trim structure includes a dopant source, a target trim element formed in proximity to the dopant source, and a conductive heating element. The heater element is formed in proximity to the dopant source and includes first and second terminals and a trapezoid shaped region formed between the first and second terminals. As predefined current pulse is applied to the first terminal to promote current flow between the first and second terminals, a local heat source is created at a predefined location within the trapezoid shaped region and in proximity to the dopant source such that dopant flows from the dopant source into the target trim element to change the conductive characteristics of the target trim element.
摘要翻译：集成电路微调结构包括掺杂剂源，在掺杂剂源附近形成的目标微调元件和导电加热元件。加热器元件形成在掺杂剂源附近，并且包括形成在第一和第二端子之间的第一和第二端子和梯形区域。当预定义的电流脉冲施加到第一端子以促进第一和第二端子之间的电流流动时，在梯形区域内的预定位置处并且在掺杂剂源附近产生局部热源，使得掺杂剂从掺杂剂源到目标装饰元件以改变目标装饰元件的导电特性。

22. 发明授权

US06933562B1 Power transistor structure with non-uniform metal widths 有权
标题翻译：功率晶体管结构具有不均匀的金属宽度
公开(公告)号：US06933562B1
公开(公告)日：2005-08-23
申请号：US10609191
申请日：2003-06-27
申请人： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko , Andy Strachan
发明人： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko , Andy Strachan
IPC分类号： H01L23/482 , H01L29/06 , H01L29/417 , H01L29/78 , H01L29/94 , H01L31/113 , H01L31/119 , H01L29/46 , H01L31/62
CPC分类号： H01L29/41758 , H01L23/4824 , H01L29/0692 , H01L29/41725 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A power transistor structure uses metal drain and source strips with non-uniform widths to reduce variations in current density across the power transistor structure. The reductions in current density, in turn, reduce the source-to-drain turn on resistance and maximize the overall current carrying capacity of power transistor structure.
摘要翻译：功率晶体管结构使用具有不均匀宽度的金属漏极和源极条来减小跨越功率晶体管结构的电流密度的变化。电流密度的降低又降低了源极到漏极导通电阻，并使功率晶体管结构的总载流能力最大化。

23. 发明授权

US06797555B1 Direct implantation of fluorine into the channel region of a PMOS device 有权
标题翻译：将氟直接注入PMOS器件的沟道区
公开(公告)号：US06797555B1
公开(公告)日：2004-09-28
申请号：US10659422
申请日：2003-09-10
申请人： Peter J. Hopper , Prasad Chaparala , Philipp Lindorfer , Vladislav Vashchenko
发明人： Peter J. Hopper , Prasad Chaparala , Philipp Lindorfer , Vladislav Vashchenko
IPC分类号： H01L218238
CPC分类号： H01L29/51 , H01L21/26506 , H01L29/1033
摘要： Fluorine is implanted directly into the channel region of a PMOS transistor structure, thereby improving the noise and VT drift margin of device performance by introducing Si—F complexes at the substrate-gate oxide interface.
摘要翻译：氟直接注入PMOS晶体管结构的沟道区，从而通过在衬底 - 栅极氧化物界面引入Si-F络合物来改善器件性能的噪声和VT漂移裕度。

24. 发明授权

US06707117B1 Method of providing semiconductor interconnects using silicide exclusion 有权
标题翻译：使用硅化物排除提供半导体互连的方法
公开(公告)号：US06707117B1
公开(公告)日：2004-03-16
申请号：US10285235
申请日：2002-10-31
申请人： Vladislav Vashchenko , Peter J. Hopper , Philipp Lindorfer , Andy Strachon , Peter Johnson
发明人： Vladislav Vashchenko , Peter J. Hopper , Philipp Lindorfer , Andy Strachon , Peter Johnson
IPC分类号： H01C2976
CPC分类号： H01L21/28518 , H01L21/76889 , H01L21/76895 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor structure, interconnects between regions of a single device or different devices are achieved by forming metal plugs that span across the regions to be interconnected, wherein the plugs are formed from the metal used in forming a silicide layer on the structure. The metal is masked off in desired areas prior to etching, to leave the metal plugs.
摘要翻译：在半导体结构中，单个器件或不同器件的区域之间的互连通过形成跨越要互连的区域的金属插塞来实现，其中插塞由在结构上形成硅化物层所用的金属形成。在蚀刻之前，将金属掩盖在所需区域中，以留下金属塞。

25. 发明授权

US08344394B1 High-speed avalanche light emitting diode (ALED) and related apparatus and method 有权
标题翻译：高速雪崩发光二极管（ALED）及相关设备及方法
公开(公告)号：US08344394B1
公开(公告)日：2013-01-01
申请号：US12584904
申请日：2009-09-15
申请人： Vladislav Vashchenko , Peter J. Hopper , Philipp Lindorfer
发明人： Vladislav Vashchenko , Peter J. Hopper , Philipp Lindorfer
IPC分类号： H01L33/00
CPC分类号： H01L33/0012 , H01L33/34 , H01L33/647
摘要： A circuit includes multiple doped regions in a substrate. A first of the doped regions has a tip proximate to a second of the doped regions and is separated from the second doped region by an intrinsic region to form a P-I-N structure. The circuit also includes first and second electrodes electrically coupled to the first and second doped regions, respectively. The electrodes are configured to supply voltages to the first and second doped regions to reverse bias the P-I-N structure and generate light. The first doped region could include multiple tips, the second doped region could include multiple tips, and each tip of the first doped region could be proximate to one of the tips of the second doped region to form multiple P-I-N structures. The P-I-N structure could also be configured to operate in double avalanche injection conductivity mode with internal positive feedback.
摘要翻译：电路包括衬底中的多个掺杂区域。掺杂区域中的第一个具有靠近第二掺杂区域的尖端，并且与第二掺杂区域分离出本征区域以形成P-I-N结构。电路还包括分别电耦合到第一和第二掺杂区域的第一和第二电极。电极被配置为向第一和第二掺杂区域提供电压以反向偏置P-I-N结构并产生光。第一掺杂区域可以包括多个尖端，第二掺杂区域可以包括多个尖端，并且第一掺杂区域的每个尖端可以接近第二掺杂区域的尖端之一以形成多个P-I-N结构。 P-I-N结构也可以被配置为在具有内部正反馈的双雪崩注入电导模式下工作。

26. 发明授权

US07754505B1 Method of forming a silicon-based light-emitting structure 有权
标题翻译：形成硅基发光结构的方法
公开(公告)号：US07754505B1
公开(公告)日：2010-07-13
申请号：US12284290
申请日：2008-09-19
申请人： Peter J. Hopper , Philipp Lindorfer , William French , Vladislav Vashchenko
发明人： Peter J. Hopper , Philipp Lindorfer , William French , Vladislav Vashchenko
IPC分类号： H01L21/00
CPC分类号： H01L33/387 , H01L33/04 , H01L33/08
摘要： A silicon-based light emitting structure is formed as a high density array of light-emitting p-n junctions that substantially increases the intensity of the light emitted in a planar region. The p-n junctions are formed using standard CMOS processing methods, and emit light in response to applied voltages that generate avalanche breakdown and an avalanche current.
摘要翻译：形成硅基发光结构作为发光p-n结的高密度阵列，其显着增加在平坦区域中发射的光的强度。使用标准CMOS处理方法形成p-n结，并响应于产生雪崩击穿和雪崩电流的施加电压而发光。

27. 发明授权

US07462874B1 Silicon-based light-emitting structure 有权
标题翻译：硅基发光结构
公开(公告)号：US07462874B1
公开(公告)日：2008-12-09
申请号：US11403516
申请日：2006-04-13
申请人： Peter J. Hopper , Philipp Lindorfer , William French , Vladislav Vashchenko
发明人： Peter J. Hopper , Philipp Lindorfer , William French , Vladislav Vashchenko
IPC分类号： H01L33/00
CPC分类号： H01L33/387 , H01L33/04 , H01L33/08
摘要： A silicon-based light emitting structure is formed as a high density array of light-emitting p-n junctions that substantially increases the intensity of the light emitted in a planar region. The p-n junctions are formed using standard CMOS processing methods, and emit light in response to applied voltages that generate avalanche breakdown and an avalanche current.
摘要翻译：形成硅基发光结构作为发光p-n结的高密度阵列，其显着增加在平坦区域中发射的光的强度。使用标准CMOS处理方法形成p-n结，并响应于产生雪崩击穿和雪崩电流的施加电压而发光。

28. 发明授权

US07375579B1 Programming of fuse-based memories using snapback devices 有权
标题翻译：使用快速恢复器件编程基于熔丝的存储器
公开(公告)号：US07375579B1
公开(公告)日：2008-05-20
申请号：US11198796
申请日：2005-08-04
申请人： Vladislav Vashchenko , Peter J. Hopper , Philipp Lindorfer
发明人： Vladislav Vashchenko , Peter J. Hopper , Philipp Lindorfer
IPC分类号： H01H37/76
CPC分类号： G11C17/16 , G11C17/18
摘要： In a fuse-based programmable circuit block, the poly-fuse is burned out by making use of a snapback device connected in series with the poly-fuse.
摘要翻译：在基于熔丝的可编程电路块中，通过使用与多熔丝串联连接的快速恢复装置将多晶硅熔断器烧掉。

29. 发明授权

US07298653B1 Reducing cross die variability in an EEPROM array 有权
标题翻译：减少EEPROM阵列中的交叉模具变化
公开(公告)号：US07298653B1
公开(公告)日：2007-11-20
申请号：US10873872
申请日：2004-06-21
申请人： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko , Yuri Mirgorodski
发明人： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko , Yuri Mirgorodski
IPC分类号： G11C11/34
CPC分类号： G11C29/02 , G11C16/04 , G11C16/12 , G11C29/021 , G11C29/028 , G11C29/50004
摘要： In an EEPROM array the cells are pre-charged or pre-erased so that they will respond uniformly to the same read voltage level. By clearly defining the threshold voltage for the cells in their erased states and in their programmed states, it is possible to define more than one read voltage and thus provide cells that an store multiple values and even analog values.
摘要翻译：在EEPROM阵列中，单元被预充电或预擦除，使得它们将均匀地响应于相同的读取电压电平。通过明确定义其擦除状态和编程状态下的单元的阈值电压，可以定义多个读取电压，从而提供存储多个值和甚至模拟值的单元。

30. 发明授权

US07221608B1 Single NMOS device memory cell and array 有权
标题翻译：单个NMOS器件存储单元和阵列
公开(公告)号：US07221608B1
公开(公告)日：2007-05-22
申请号：US10957986
申请日：2004-10-04
申请人： Vladislav Vashchenko , Peter J. Hopper , Philipp Lindorfer
发明人： Vladislav Vashchenko , Peter J. Hopper , Philipp Lindorfer
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/403 , G11C2211/4065
摘要： The snapback characteristics of the parasitic NPN structure inside an NMOS device are used to write and store information in the device by periodically triggering the device from the high impedance state to the low impedance state using the self turn-on characteristics of the device under elevated voltage. To minimize power consumption, and thus overheating, in the “on” state, a pulsed mode operation is combined with dV/dt triggering powering the device at a constant Vdd pulse amplitude.
摘要翻译： NMOS器件内的寄生NPN结构的快速恢复特性用于通过在高电压下使器件的自启动特性周期性地将器件从高阻抗状态触发到低阻抗状态来将信息写入和存储在器件中。为了最小化功率消耗并因此过热，在“导通”状态下，将脉冲模式操作与dV / dt触发相结合，以恒定的Vdd脉冲幅度向器件供电。

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