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21. 发明授权

US6158032A Data processing system, circuit arrangement and program product including multi-path scan interface and methods thereof 失效
标题翻译：数据处理系统，电路布置和程序产品，包括多路径扫描接口及其方法
公开(公告)号：US6158032A
公开(公告)日：2000-12-05
申请号：US49170
申请日：1998-03-27
申请人： Guy Richard Currier , Leland Leslie Day , Steven Michael Douskey , Paul Allen Ganfield , James Maurice Wallin
发明人： Guy Richard Currier , Leland Leslie Day , Steven Michael Douskey , Paul Allen Ganfield , James Maurice Wallin
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318536
摘要： A data processing system, circuit arrangement, program product, and method thereof utilize a multi-path scan interface that is capable of providing multiple scan paths into a plurality of scan ring segments in an integrated circuit device. The multi-path scan interface utilizes one or more multiplexers coupled between scan in and scan out ports and at least one scan ring segment to provide alternate scan paths depending upon select signals supplied to each multiplexer. With such a configuration, a standardized scan interface may developed for interfacing with a wide variety of scan ring segments, and optionally, for multiple purposes. As a result, the amount of custom circuitry necessary to provide access to scan ring segments is significantly reduced.
摘要翻译：数据处理系统，电路装置，程序产品及其方法利用能够向集成电路装置中的多个扫描环段提供多条扫描路径的多路径扫描接口。多路径扫描接口利用耦合在扫描入口和扫描端口中的一个或多个多路复用器和至少一个扫描环段，以根据提供给每个多路复用器的选择信号提供交替的扫描路径。利用这种配置，可以开发用于与各种各样的扫描环段对接的标准化扫描界面，并且可选地，出于多个目的。因此，提供访问扫描环段所需的定制电路的量显着减少。

22. 发明授权

US5835502A Method and apparatus for handling variable data word widths and array depths in a serial shared abist scheme 失效
标题翻译：用于处理串行共享静态方案中可变数据字宽和阵列深度的方法和装置
公开(公告)号：US5835502A
公开(公告)日：1998-11-10
申请号：US673258
申请日：1996-06-28
申请人： Anthony Gus Aipperspach , Todd Alan Christensen , Leland Leslie Day , Paul Allen Ganfield , Murali Vaddigiri , Paul Wong
发明人： Anthony Gus Aipperspach , Todd Alan Christensen , Leland Leslie Day , Paul Allen Ganfield , Murali Vaddigiri , Paul Wong
IPC分类号： G06F12/16 , G06F11/22 , G11C29/02 , G11C29/12 , G11C29/32 , G06F11/00
CPC分类号： G11C29/32
摘要： A method and apparatus for handling variable data word widths and array depths in an array built-in self-test system for testing a plurality of memory arrays using a single controller. Each array includes a predetermined row and column address depth and data word width. Each array further includes a scan register. A universal test data word is generated and sent to the scan register of each array. The universal length test data word has a length dependent upon the maximum row address depth, maximum column address depth and/or the maximum data word width. A portion of the test data word which exceeds the column address depth, row address depth and/or the data word width of a particular array is shifted off the end of the scan register of the particular array.
摘要翻译：一种用于处理阵列内置自检系统中的可变数据字宽度和阵列深度的方法和装置，用于使用单个控制器来测试多个存储器阵列。每个阵列包括预定的行和列地址深度和数据字宽度。每个阵列还包括扫描寄存器。生成通用测试数据字并将其发送到每个阵列的扫描寄存器。通用长度测试数据字的长度取决于最大行地址深度，最大列地址深度和/或最大数据字宽度。超过特定阵列的列地址深度，行地址深度和/或数据字宽度的测试数据字的一部分从特定阵列的扫描寄存器的结尾偏移。

23. 发明授权

US5815694A Apparatus and method to change a processor clock frequency 失效
标题翻译：改变处理器时钟频率的装置和方法
公开(公告)号：US5815694A
公开(公告)日：1998-09-29
申请号：US576172
申请日：1995-12-21
申请人： Paul Allen Ganfield , Charles Luther Johnson , James David Strom
发明人： Paul Allen Ganfield , Charles Luther Johnson , James David Strom
IPC分类号： G06F1/08
CPC分类号： G06F1/08
摘要： An apparatus and method for providing a variable frequency clock source is described wherein the frequency may be changed while maintaining the phase of the clock signal. A frequency conversation circuit, such as a phase locked loop (PLL), is employed to change the frequency of the clock and is controlled by a control unit which maintains the phase of the output clock signal while undergoing a frequency change operation.
摘要翻译：描述了一种用于提供可变频率时钟源的装置和方法，其中可以在保持时钟信号的相位的同时改变频率。使用诸如锁相环（PLL）的频率对话电路来改变时钟的频率，并且由控制单元控制，该控制单元在经历频率改变操作时保持输出时钟信号的相位。

24. 发明授权

US07761682B2 Memory controller operating in a system with a variable system clock 失效
标题翻译：内存控制器在具有可变系统时钟的系统中运行
公开(公告)号：US07761682B2
公开(公告)日：2010-07-20
申请号：US12191195
申请日：2008-08-13
申请人： Melissa Ann Barnum , Mark David Bellows , Paul Allen Ganfield , Lonny Lambrecht , Tolga Ozguner
发明人： Melissa Ann Barnum , Mark David Bellows , Paul Allen Ganfield , Lonny Lambrecht , Tolga Ozguner
IPC分类号： G06F13/14 , G06F13/36
CPC分类号： G11C8/18 , G06F13/1642 , G06F13/1689 , Y02D10/14
摘要： The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.
摘要翻译：本发明一般涉及在包含可变系统时钟的系统中操作的存储器控制器。存储器控制器可以与以可变处理器时钟频率工作的处理器交换数据。然而，存储器控制器可以以恒定的存储器时钟频率执行存储器访问。可以提供异步缓冲器以跨可变和恒定时钟域传输数据。为了防止在切换到较低处理器时钟频率时读取缓冲区溢出，存储器控制器可以使存储器定序器静止，并以较慢的速率从定序器调速读取数据。为了防止在运行中写入数据，存储器控制器的数据流逻辑可以执行握手以确保在执行写访问之前在缓冲器中完全接收到写数据。

25. 发明授权

US07716430B2 Separate handling of read and write of read-modify-write 失效
公开(公告)号：US07716430B2
公开(公告)日：2010-05-11
申请号：US12033910
申请日：2008-02-20
申请人： Melissa Ann Barnum , Paul Allen Ganfield , Lonny Lambrecht
发明人： Melissa Ann Barnum , Paul Allen Ganfield , Lonny Lambrecht
IPC分类号： G06F12/00
CPC分类号： G06F13/1673 , G06F9/3004 , G06F9/30087 , G06F9/383 , G06F9/3834
摘要： Separate handling of read and write operations of Read-Modify-Write Commands in an XDR™ memory system is provided. This invention allows the system to issue other commands between the reads and writes of a RMW. This insures that the dataflow time from read to write is not a penalty. A RMW buffer is used to store the read data and a write buffer is used to store the write data. A MUX is used to merge the read data and the write data, and transmit the merged data to the target DRAM via the XIO. The RMW buffer can also be used for scrubbing commands.

26. 发明申请

US20080307184A1 MEMORY CONTROLLER OPERATING IN A SYSTEM WITH A VARIABLE SYSTEM CLOCK 失效
标题翻译：在具有可变系统时钟的系统中操作的存储器控制器
公开(公告)号：US20080307184A1
公开(公告)日：2008-12-11
申请号：US12191195
申请日：2008-08-13
申请人： Melissa Ann Barnum , Mark David Bellows , Paul Allen Ganfield , Lonny Lambrecht , Tolga Ozguner
发明人： Melissa Ann Barnum , Mark David Bellows , Paul Allen Ganfield , Lonny Lambrecht , Tolga Ozguner
IPC分类号： G06F12/00
CPC分类号： G11C8/18 , G06F13/1642 , G06F13/1689 , Y02D10/14
摘要： The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.
摘要翻译：本发明一般涉及在包含可变系统时钟的系统中操作的存储器控制器。存储器控制器可以与以可变处理器时钟频率工作的处理器交换数据。然而，存储器控制器可以以恒定的存储器时钟频率执行存储器访问。可以提供异步缓冲器以跨可变和恒定时钟域传输数据。为了防止在切换到较低处理器时钟频率时读取缓冲区溢出，存储器控制器可以使存储器定序器静止，并以较慢的速率从定序器调速读取数据。为了防止在运行中写入数据，存储器控制器的数据流逻辑可以执行握手以确保在执行写访问之前在缓冲器中完全接收到写数据。

27. 发明授权

US07363442B2 Separate handling of read and write of read-modify-write 失效
标题翻译：读写修改写的单独处理
公开(公告)号：US07363442B2
公开(公告)日：2008-04-22
申请号：US10988314
申请日：2004-11-12
申请人： Melissa Ann Barnum , Paul Allen Ganfield , Lonny Lambrecht
发明人： Melissa Ann Barnum , Paul Allen Ganfield , Lonny Lambrecht
IPC分类号： G06F12/00
CPC分类号： G06F13/1673 , G06F9/3004 , G06F9/30087 , G06F9/383 , G06F9/3834
摘要： A method, an apparatus, and a computer program are provided for the separate handling of read and write operations of Read-Modify-Write Commands in an XDR™ memory system. This invention allows the system to issue other commands between the reads and writes of a RMW. This insures that the dataflow time from read to write is not a penalty. A RMW buffer is used to store the read data and a write buffer is used to store the write data. A MUX is used to merge the read data and the write data, and transmit the merged data to the target DRAM via the XIO. The RMW buffer can also be used for scrubbing commands.
摘要翻译：提供了一种方法，装置和计算机程序，用于在XDR（TM）存储器系统中单独处理读取 - 修改 - 写入命令的读取和写入操作。本发明允许系统在RMW的读取和写入之间发出其他命令。这确保从读取到写入的数据流时间不是一个惩罚。使用RMW缓冲器来存储读取的数据，并且使用写入缓冲器来存储写入数据。使用MUX来合并读取数据和写入数据，并通过XIO将合并的数据发送到目标DRAM。 RMW缓冲区也可用于擦除命令。

28. 发明授权

US07272699B2 Flexible sub-column to sub-row mapping for sub-page activation in XDR™ DRAMs 有权
标题翻译：灵活的子列到子行映射，用于XDR（TM）DRAM中的子页面激活
公开(公告)号：US07272699B2
公开(公告)日：2007-09-18
申请号：US10988312
申请日：2004-11-12
申请人： Paul Allen Ganfield , Ryan Abel Heckendorf
发明人： Paul Allen Ganfield , Ryan Abel Heckendorf
IPC分类号： G06F12/10
CPC分类号： G06F12/0646 , G06F12/02 , G06F2212/1028 , G11C11/408 , Y02D10/13
摘要： A method, a computer program, and an apparatus are provided for flexible SC to SR mapping to enable sub-page activation in an XDR™ memory system. An XDR™ memory system may allow system page size to reduced by a factor of two (half-page activation) or four (quarter-page activation). In an XDR™ memory system there are five different SCs and two different SRs. This scheme allows any one of the five SCs (or none) to be mapped to any one of the two SRs. Overall, this invention provides a flexible mapping scheme that can be utilized for any possible XDR memory system.
摘要翻译：提供了一种方法，计算机程序和装置，用于灵活的SC至SR映射以使得能够在XDR TM存储器系统中进行子页面激活。 XDR（TM）存储器系统可以允许系统页面大小减少二分之一（半页激活）或四（四分之一页激活）。在XDR（TM）存储器系统中，存在五个不同的SC和两个不同的SR。该方案允许将五个SC（或无）中的任何一个映射到两个SR中的任何一个。总体而言，本发明提供了可用于任何可能的XDR存储器系统的灵活的映射方案。

29. 发明授权

US07266650B2 Method, apparatus, and computer program product for implementing enhanced circular queue using loop counts 失效
标题翻译：用于使用循环计数实现增强型循环队列的方法，装置和计算机程序产品
公开(公告)号：US07266650B2
公开(公告)日：2007-09-04
申请号：US10988232
申请日：2004-11-12
申请人： Paul Allen Ganfield , Lonny Lambrecht
发明人： Paul Allen Ganfield , Lonny Lambrecht
IPC分类号： G06F12/00
CPC分类号： G06F17/30958
摘要： A method, apparatus, and computer program product are provided for implementing an enhanced circular queue using loop counts for command processing. A circular queue includes a plurality of entries for storing commands. As command entries are added to the queue at the head of the queue, a head loop count is stored with each command entry. A head pointer is updated to the head of the queue. When the head pointer wraps from a last queue entry to a first queue entry, the head loop count is incremented. A tail pointer points to an oldest command entry, and is updated when the oldest command entry is executed. When the tail pointer advances and wraps from a last queue entry to a first queue entry, the tail pointer loop count is incremented.
摘要翻译：提供了一种方法，装置和计算机程序产品，用于使用用于命令处理的循环计数来实现增强的循环队列。循环队列包括用于存储命令的多个条目。由于命令条目被添加到队列头部的队列中，所以每个命令条目都存储头循环计数。头指针被更新到队列的头部。当头指针从最后一个队列条目包装到第一个队列条目时，头循环计数递增。尾指针指向最旧的命令条目，并在执行最旧的命令条目时更新。当尾部指针从最后一个队列条目前进到第一个队列条目时，尾部指针循环计数递增。

30. 发明授权

US06260164B1 SRAM that can be clocked on either clock phase 失效
标题翻译：可以在任一时钟阶段对SRAM进行时钟控制
公开(公告)号：US06260164B1
公开(公告)日：2001-07-10
申请号：US09127355
申请日：1998-07-31
申请人： Anthony Gus Aipperspach , Leland Leslie Day , Paul Allen Ganfield , Charles Luther Johnson
发明人： Anthony Gus Aipperspach , Leland Leslie Day , Paul Allen Ganfield , Charles Luther Johnson
IPC分类号： G01R3128
CPC分类号： G11C11/417
摘要： A functional unit, such as an SRAM, in a single clock chip design that contains a scan path can be clocked on either rising edge and falling edge of the clock. The functional unit includes a clock signal having two phases and a plurality of latches for scanning. Two scan latches are added outside the array of the functional unit. In one clock phase, the two scan latches form a latch pair which is connected to the array at Scan-in side. In the other clock phase, one scan latch is connected to the array at the Scan-in side, and the other scan latch is connected to the array at the Scan-out side. In scan/hold operations, a first control signal for the array which is clocked at the falling edge of the clock leads a second control signal for the array which is clocked at the rising edge of the clock. In ABIST/functional operations, the first control signal for the array which is clocked at the falling edge of the clock trails the second control signal for the array which is clocked at the rising edge of the clock.
摘要翻译：包含扫描路径的单个时钟芯片设计中的诸如SRAM的功能单元可以在时钟的上升沿和下降沿被计时。功能单元包括具有两相的时钟信号和用于扫描的多个锁存器。两个扫描锁存器被添加到功能单元的阵列之外。在一个时钟相位中，两个扫描锁存器形成一个锁存器对，其在Scan-in侧连接到阵列。在另一个时钟阶段，一个扫描锁存器连接到Scan-in侧的阵列，另一个扫描锁存器连接到Scan-out侧的阵列。在扫描/保持操作中，在时钟的下降沿被计时的阵列的第一控制信号引出在时钟的上升沿被计时的阵列的第二控制信号。在ABIST /功能操作中，在时钟下降沿时钟脉冲的阵列的第一个控制信号跟踪在时钟上升沿时钟脉冲的阵列的第二个控制信号。

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