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21. 发明授权

US07480785B2 Parallel processing device and parallel processing method 失效
标题翻译：并行处理装置及并行处理方法
公开(公告)号：US07480785B2
公开(公告)日：2009-01-20
申请号：US10505718
申请日：2004-02-13
申请人： Toshishige Shimamura , Hiroki Morimura , Koji Fujii , Satoshi Shigematsu , Katsuyuki Machida
发明人： Toshishige Shimamura , Hiroki Morimura , Koji Fujii , Satoshi Shigematsu , Katsuyuki Machida
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06K9/00006 , G06F7/5095 , G06F7/607 , G06K9/00986 , G06K9/6202 , G06K9/78 , G06K9/80
摘要： A row decoding circuit (171) outputs a select signal to a row set in a row range setting unit (172) to select a select signal line (103), processing results from processing circuits (102) on this row are output to a data output line (104), and a row adder (106) adds processing results output to a data output line (104) of a column set in a column range selector (105).
摘要翻译：行解码电路（171）将选择信号输出到行范围设定单元（172）中设置的行，以选择选择信号线（103），将来自该行处理电路（102）的处理结果输出到数据输出线（104）和行加法器（106）将输出的处理结果相加在列范围选择器（105）中设置的列的数据输出线（104）。

22. 发明申请

US20080056543A1 Surface Shape Recognizing Sensor Device 失效
标题翻译：表面形状识别传感器装置
公开(公告)号：US20080056543A1
公开(公告)日：2008-03-06
申请号：US10582128
申请日：2005-07-15
申请人： Hiroki Morimura , Mamoru Nakanishi , Satoshi Shigematsu , Takahiro Hatano , Yukio Okazaki , Katsuyuki Machida
发明人： Hiroki Morimura , Mamoru Nakanishi , Satoshi Shigematsu , Takahiro Hatano , Yukio Okazaki , Katsuyuki Machida
IPC分类号： G06K9/00 , A61B5/117 , G01B7/28
CPC分类号： G06K9/0002 , A61B5/1172 , A61B2562/0209 , A61B2562/046
摘要： A sensor cell includes a sensor electrode (101) formed on a substrate (100), a signal output unit (16) which outputs a signal corresponding to a capacitance (Cf) formed between the sensor electrode and the surface of a finger (3), a high-sensitivity electrode (103) formed on the substrate so as to be insulated and isolated from the sensor electrode, and a potential controller (14) which controls the potential of the finger surface via a capacitance (Cc) formed between the high-sensitivity electrode and the finger surface by controlling the potential of the high-sensitivity electrode. In this arrangement, when the resistance of the finger is high, the potential of the finger surface can be controlled so as not to fluctuate with the potential change of the sensor electrode. This makes it possible to increase the sensitivity of detection of the capacitance formed between the sensor electrode and the finger surface, so ridges and valleys of the finger surface can be clearly discriminated by outputs from a plurality of sensor cells.
摘要翻译：传感器单元包括形成在基板（100）上的传感器电极（101），输出对应于形成在传感器电极和手指表面之间的电容（Cf）的信号的信号输出单元（16），形成在所述基板上以与所述传感器电极绝缘和隔离的高灵敏度电极（103），以及电位控制器（14），其经由形成在所述高电平之间的电容（Cc）来控制所述手指表面的电位通过控制高灵敏度电极的电位，感光电极和手指表面。在这种布置中，当手指的电阻高时，手指表面的电位可以被控制成不会随着传感器电极的电位变化而波动。这使得可以提高检测传感器电极和手指表面之间的电容的灵敏度，因此可以通过多个传感器单元的输出来清楚地识别手指表面的脊和谷。

23. 发明申请

US20080012619A1 Master-Slave Flip-Flop, Trigger Flip-Flop and Counter 失效
标题翻译：主从触发器，触发器触发器和计数器
公开(公告)号：US20080012619A1
公开(公告)日：2008-01-17
申请号：US10572446
申请日：2005-08-09
申请人： Hiroki Morimura , Satoshi Shigematsu , Yukio Okazaki , Katsuyuki Machida
发明人： Hiroki Morimura , Satoshi Shigematsu , Yukio Okazaki , Katsuyuki Machida
IPC分类号： H03K3/3562
CPC分类号： H03K3/356156 , H03K3/35625
摘要： A master latch (1) is formed from a static circuit, and a slave latch (2) is formed from a dynamic circuit. The number of circuit elements can be smaller as compared to a slave latch formed from a static circuit so that the size and area of a master-slave flip-flop can be reduced. Since the master latch is formed from a static circuit, data can be held stably during the standby time by setting the master latch in a data holding state.
摘要翻译：主锁存器（1）由静态电路形成，从锁存器（2）由动态电路形成。与由静态电路形成的从锁存器相比，电路元件的数量可以更小，从而可以减小主从触发器的尺寸和面积。由于主锁存器是由静态电路形成的，所以通过将主锁存器设置为数据保持状态，可以在待机时间内保持稳定的数据。

24. 发明授权

US07062075B2 Surface shape recognition sensor device 失效
公开(公告)号：US07062075B2
公开(公告)日：2006-06-13
申请号：US10140742
申请日：2002-05-07
申请人： Hiroki Morimura , Toshishige Shimamura , Satoshi Shigematsu , Katsuyuki Machida , Hakaru Kyuragi
发明人： Hiroki Morimura , Toshishige Shimamura , Satoshi Shigematsu , Katsuyuki Machida , Hakaru Kyuragi
IPC分类号： G06K9/00
CPC分类号： G06K9/0002
摘要： A calibration mode signal line to which sensor cells are commonly connected is arranged. In a calibration mode, a calibration mode signal is supplied to the sensor cells through the calibration mode signal line to designate calibration. In each sensor cell, when the calibration mode signal is being supplied from the calibration mode signal line, and the sensor cell is selected by the decoder, calibration operation of adjusting the detection sensitivity of a sensor circuit is executed using a calibration circuit.

25. 发明申请

US20050258877A1 Waveform shaping circuit 失效
标题翻译：波形整形电路
公开(公告)号：US20050258877A1
公开(公告)日：2005-11-24
申请号：US10505629
申请日：2004-01-21
申请人： Hiroki Morimura , Toshishige Shimamura , Koji Fujii , Satoshi Shigematsu , Yukio Okazaki , Katsuyuki Machida
发明人： Hiroki Morimura , Toshishige Shimamura , Koji Fujii , Satoshi Shigematsu , Yukio Okazaki , Katsuyuki Machida
IPC分类号： H03K5/08 , H03K5/1534 , H03K17/22 , H03K17/30 , H03B1/00
CPC分类号： H03K5/082 , H03K5/1534 , H03K17/223 , H03K17/302
摘要： A first control potential setting means (1) generates a first control potential (N2) which reverses the magnitude relationship with a second control potential (N3) when an input signal (IN) reaches the vicinity of a logical threshold value. A second control potential setting means (2) generates the second control potential (N3) which changes in the same direction as the input signal (IN), in accordance with a change in input signal (IN). An output means (3) includes transistors (Q5, Q6), and generates an output signal (OUT) having a predetermined potential on the basis of the first control potential (N2), the second control potential (N3), and a reset signal (RSET). A reset means (4) turns off the transistor (Q6) while a waveform shaping circuit is in operation.
摘要翻译：当输入信号（IN）达到逻辑门限值附近时，第一控制电位设定装置（1）产生使与第二控制电位（N 3）的大小关系相反的第一控制电位（N 2）。第二控制电位设定装置（2）根据输入信号（IN）的变化产生与输入信号（IN）沿相同方向变化的第二控制电位（N 3）。输出装置（3）包括晶体管（Q 5，Q 6），并且基于第一控制电位（N 2），第二控制电位（N 3）产生具有预定电位的输出信号（OUT）和复位信号（RSET）。当波形整形电路处于工作状态时，复位装置（4）关断晶体管（Q 6）。

26. 发明授权

US06248655B1 Method of fabricating a surface shape recognition sensor 有权
标题翻译：制作表面形状识别传感器的方法
公开(公告)号：US06248655B1
公开(公告)日：2001-06-19
申请号：US09515962
申请日：2000-02-29
申请人： Katsuyuki Machida , Satoshi Shigematsu , Hiroki Morimura , Akihiko Hirata
发明人： Katsuyuki Machida , Satoshi Shigematsu , Hiroki Morimura , Akihiko Hirata
IPC分类号： H01L2144
CPC分类号： G06K9/0002 , G01B7/004 , G01B7/34
摘要： A surface shape recognition sensor of this invention includes at least a plurality of capacitance detection elements having sensor electrodes arranged in the same plane on an interlevel dielectric film formed on a semiconductor substrate to be insulated/isolated from each other, capacitance detection means for detecting the capacitances of the capacitance detection elements, and a stationary electrode disposed on the interlevel dielectric film to be insulated/isolated from the sensor electrodes. When an object to be recognized touches the upper surface of the stationary electrode, the capacitances detected by the capacitance detection elements change in accordance with the recesses/projections on the upper surface.
摘要翻译：本发明的表面形状识别传感器至少包括多个电容检测元件，该电容检测元件具有布置在形成于半导体衬底上的层间电介质膜上的同一平面内的绝缘/隔离的电容检测元件，用于检测电容检测元件的电容和设置在层间电介质膜上的与传感器电极绝缘/隔离的固定电极。当待识别的物体接触固定电极的上表面时，由电容检测元件检测的电容根据上表面上的凹凸来改变。

27. 发明授权

US06917694B1 Surface shape recognition apparatus and method 失效
标题翻译：表面形状识别装置及方法
公开(公告)号：US06917694B1
公开(公告)日：2005-07-12
申请号：US09573615
申请日：2000-05-17
申请人： Katsuyuki Machida , Satoshi Shigematsu , Hiroki Morimura , Hakaru Kyuragi , Takuya Adachi
发明人： Katsuyuki Machida , Satoshi Shigematsu , Hiroki Morimura , Hakaru Kyuragi , Takuya Adachi
IPC分类号： A61B5/117 , G06K9/00 , G06F7/04
CPC分类号： G06K9/00006 , A61B5/1172
摘要： A surface shape recognition apparatus includes detection circuit, comparison circuit, storage circuit, and control circuit. The detection circuit electrically detects a surface shape pattern in a partial region of the target collation surface of an object using a plurality of sensor elements and outputs detection data representing the surface shape pattern. The comparison circuit compares the detection data from the detection circuit with predetermined collation data and outputs a comparison result. The storage circuit stores template data representing the surface shape pattern of the entire target collation surface, the template data being obtained from the object in advance. The control circuit partially reads out, as collation data, the template data stored in the storage circuit from an arbitrary position, outputs the collation data to the comparison circuit, and performs determination for authentication between the template data and the object on the basis of the comparison result from the comparison circuit. A surface shape recognition method is also disclosed.
摘要翻译：表面形状识别装置包括检测电路，比较电路，存储电路和控制电路。检测电路使用多个传感器元件电检测物体的目标核对表面的部分区域中的表面形状图案，并输出表示形状图案的检测数据。比较电路将来自检测电路的检测数据与预定核对数据进行比较，并输出比较结果。存储电路存储表示整个目标对照表面的表面形状图案的模板数据，模板数据是从对象预先获得的。控制电路作为核对数据部分地从任意位置读出存储在存储电路中的模板数据，将对照数据输出到比较电路，并基于该模板数据进行对模板数据与对象之间的认证的确定比较电路的比较结果。还公开了一种表面形状识别方法。

28. 发明授权

US07673145B2 Biometric image collation apparatus and collation method therefor 失效
标题翻译：生物图像对比装置及其对照方法
公开(公告)号：US07673145B2
公开(公告)日：2010-03-02
申请号：US10515566
申请日：2004-03-05
申请人： Takahiro Hatano , Satoshi Shigematsu , Hiroki Morimura , Namiko Ikeda , Yukio Okazaki , Katsuyuki Machida , Mamoru Nakanishi
发明人： Takahiro Hatano , Satoshi Shigematsu , Hiroki Morimura , Namiko Ikeda , Yukio Okazaki , Katsuyuki Machida , Mamoru Nakanishi
IPC分类号： H04L9/00
CPC分类号： G06K9/00067 , G06K9/00087 , G06K9/036
摘要： This invention includes an image quality priority level decision processing unit (40) which evaluates the magnitude of an image quality of each of a plurality of first image data formed from biometric images associated with the same target on the basis of a specific index having the relationship of a monotone function with authentication accuracy of biometric authentication, and outputs each of the first image data upon adding a priority level thereto on the basis of the evaluation result, a first image storage (6, 81) unit which stores each of the first image data having a priority level added thereto from the image quality priority level decision processing unit (40), a second image storage unit (8, 61) which stores second image data used for comparison/collation with the first image data, an image collation unit (7) which compares/collates the second image data stored in the second image storage unit (8, 61) with the first image data stored in the first image storage unit (6, 81) and outputs the comparison/collation result, and a control unit (9) which controls each of the units. The control unit (9) causes the image collation unit (7) to compare/collate the second image data stored in the second image storage unit (8, 61) with the first image data stored in the first image storage unit (6, 81) in accordance with the priority levels, and outputs the comparison/collation result from the image collation unit (7).
摘要翻译：本发明包括图像质量优先级决定处理单元（40），其根据具有关系的特定索引来评估由与相同目标相关联的生物特征图像形成的多个第一图像数据中的每一个的图像质量的大小具有生物体认证的认证精度的单调函数，并且基于评估结果向其添加优先级，并输出每个第一图像数据;第一图像存储器（6,81）单元，其存储每个第一图像从图像质量优先级判定处理单元（40）向其添加优先级的数据，存储用于与第一图像数据进行比较/对照的第二图像数据的第二图像存储单元（8,61），图像对照单元（7），其将存储在第二图像存储单元（8,61）中的第二图像数据与存储在第一图像存储单元（6,81）中的第一图像数据进行比较/比较 d输出比较/核对结果，以及控制单元（9）。控制单元（9）使图像核对单元（7）将存储在第二图像存储单元（8,61）中的第二图像数据与存储在第一图像存储单元（6,81中）的第一图像数据进行比较/ ），并且从图像对照单元（7）输出比较/核对结果。

29. 发明授权

US07440534B2 Master-slave flip-flop, trigger flip-flop and counter 失效
标题翻译：主从触发器，触发器触发器和计数器
公开(公告)号：US07440534B2
公开(公告)日：2008-10-21
申请号：US10572446
申请日：2005-08-09
申请人： Hiroki Morimura , Satoshi Shigematsu , Yukio Okazaki , Katsuyuki Machida
发明人： Hiroki Morimura , Satoshi Shigematsu , Yukio Okazaki , Katsuyuki Machida
IPC分类号： H03K23/50 , H03K3/356
CPC分类号： H03K3/356156 , H03K3/35625
摘要： A master latch (1) is formed from a static circuit, and a slave latch (2) is formed from a dynamic circuit. The number of circuit elements can be smaller as compared to a slave latch formed from a static circuit so that the size and area of a master-slave flip-flop can be reduced. Since the master latch is formed from a static circuit, data can be held stably during the standby time by setting the master latch in a data holding state.
摘要翻译：主锁存器（1）由静态电路形成，从锁存器（2）由动态电路形成。与由静态电路形成的从锁存器相比，电路元件的数量可以更小，从而可以减小主从触发器的尺寸和面积。由于主锁存器是由静态电路形成的，所以通过将主锁存器设置为数据保持状态，可以在待机时间内保持稳定的数据。

30. 发明授权

US07019563B2 Waveform shaping circuit 失效
标题翻译：波形整形电路
公开(公告)号：US07019563B2
公开(公告)日：2006-03-28
申请号：US10505629
申请日：2004-01-21
申请人： Hiroki Morimura , Toshishige Shimamura , Koji Fujii , Satoshi Shigematsu , Yukio Okazaki , Katsuyuki Machida
发明人： Hiroki Morimura , Toshishige Shimamura , Koji Fujii , Satoshi Shigematsu , Yukio Okazaki , Katsuyuki Machida
IPC分类号： H03B1/00
CPC分类号： H03K5/082 , H03K5/1534 , H03K17/223 , H03K17/302
摘要： A first control potential setting means (1) generates a first control potential (N2) which reverses the magnitude relationship with a second control potential (N3) when an input signal (IN) reaches the vicinity of a logical threshold value. A second control potential setting means (2) generates the second control potential (N3) which changes in the same direction as the input signal (IN), in accordance with a change in input signal (IN). An output means (3) includes transistors (Q5, Q6), and generates an output signal (OUT) having a predetermined potential on the basis of the first control potential (N2), the second control potential (N3), and a reset signal (RSET). A reset means (4) turns off the transistor (Q6) while a waveform shaping circuit is in operation.
摘要翻译：当输入信号（IN）达到逻辑门限值附近时，第一控制电位设定装置（1）产生使与第二控制电位（N 3）的大小关系相反的第一控制电位（N 2）。第二控制电位设定装置（2）根据输入信号（IN）的变化产生与输入信号（IN）沿相同方向变化的第二控制电位（N 3）。输出装置（3）包括晶体管（Q 5，Q 6），并且基于第一控制电位（N 2），第二控制电位（N 3）产生具有预定电位的输出信号（OUT）和复位信号（RSET）。当波形整形电路处于工作状态时，复位装置（4）关断晶体管（Q 6）。

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