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21. 发明申请

US20080188254A1 Mobile communication terminal, method for registering location thereof and computer program product 审中-公开
标题翻译：移动通信终端，其登记方法和计算机程序产品
公开(公告)号：US20080188254A1
公开(公告)日：2008-08-07
申请号：US12005382
申请日：2007-12-27
申请人： Keijirou Kubo , Satoshi Kuroki , Yasuhiro Mori , Kazuo Yano
发明人： Keijirou Kubo , Satoshi Kuroki , Yasuhiro Mori , Kazuo Yano
IPC分类号： H04B7/00
CPC分类号： H04W48/20 , H04W60/00
摘要： A mobile communication terminal includes a measuring portion measuring intensity of received radio waves that are radio waves received from base stations, a selecting portion selecting one of the base stations to which a request for location registration of the mobile communication terminal should be sent, and a requesting portion sending the request to the base station selected by the selecting portion. When the request is sent, the selecting portion initially selects a first base station of the base stations whose received radio wave has the highest intensity measured by the measuring portion, and, subsequently if the location registration in accordance with the request sent to one of the base stations has failed, the selecting portion selects a second base station of the base stations whose received radio wave has intensity lower than the intensity of the received radio wave from the one of the base stations.
摘要翻译：移动通信终端包括：测量作为从基站接收的无线电波的接收的无线电波的强度的测量部分，选择要发送移动通信终端的位置登记请求的基站之一的选择部分，以及请求部分将请求发送到由选择部分选择的基站。当请求被发送时，选择部分最初选择其接收的无线电波具有由测量部分测量的最高强度的基站的第一基站，并且随后如果根据请求的位置登记发送到基站发生故障，选择部分选择接收的无线电波的强度低于来自基站之一的所接收的无线电波的强度的基站的第二基站。

22. 发明授权

US07309892B2 Semiconductor element and semiconductor memory device using the same 失效
标题翻译：半导体元件和使用其的半导体存储器件
公开(公告)号：US07309892B2
公开(公告)日：2007-12-18
申请号：US11439152
申请日：2006-05-24
申请人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
发明人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
IPC分类号： H01L29/76 , H01L29/788 , H01L29/94
CPC分类号： B82Y10/00 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/0466 , G11C16/10 , G11C16/28 , G11C2216/06 , G11C2216/08 , H01L21/28273 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11551 , H01L27/1203 , H01L29/42328 , H01L29/513 , H01L29/66825 , H01L29/7613 , H01L29/785 , H01L29/7888
摘要： A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.
摘要翻译：一种场效应半导体元件，其具有较少数量的元件和减小的面积，并能够自身存储数据，而不需要在低温下进行冷却;以及采用该半导体元件的存储器件。栅极沟道电容被设置得如此小，以致捕获捕获一个电子或空穴是否可以根据半导体FET元件的电流的变化来明确且明显地被检测。通过检测通过在陷阱中捕获电子或空穴而导致的半导体元件的阈值电压的变化，可以在室温下实现数据存储。

23. 发明申请

US20060264241A1 Base station log collection device, method for collecting logs of base station and computer program product 审中-公开
标题翻译：基站日志收集装置，收集基站日志和计算机程序产品的方法
公开(公告)号：US20060264241A1
公开(公告)日：2006-11-23
申请号：US11492065
申请日：2006-07-25
申请人： Shinichi Koyamatsu , Kazuo Yano
发明人： Shinichi Koyamatsu , Kazuo Yano
IPC分类号： H04B1/38
CPC分类号： H04W88/08
摘要： A device and method is provided for reducing the cost involved in bases for colleting logs of base stations compared to conventional cases. A remote log collection device includes a bus interface for connecting to a wireless base station device, a wire communications network interface or a wireless communications network interface corresponding to a communications network different from a communications network used for the wireless base station device, a log data entry control portion for controlling the bus interface so that log data indicating contents of a process performed in the wireless base station device are entered, a RAM for storing the entered log data, and a log transmission control portion for controlling the wire communications network interface or the wireless communications network interface so that the log data stored in the RAM are transmitted to a maintenance device.
摘要翻译：提供了一种装置和方法，用于降低与常规情况相比基站收录日志所涉及的成本。远程日志收集装置包括用于连接到无线基站装置的总线接口，对应于与用于无线基站装置的通信网络不同的通信网络的有线通信网络接口或无线通信网络接口，日志数据输入控制部分，用于控制总线接口，从而输入指示在无线基站装置中执行的处理的内容的日志数据，用于存储输入的日志数据的RAM，以及用于控制有线通信网络接口的日志传输控制部分，无线通信网络接口，使得存储在RAM中的日志数据被发送到维护设备。

24. 发明授权

US07061053B2 Semiconductor element and semiconductor memory device using the same 失效
公开(公告)号：US07061053B2
公开(公告)日：2006-06-13
申请号：US10929424
申请日：2004-08-31
申请人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
发明人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
IPC分类号： H01L29/76
CPC分类号： B82Y10/00 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/0466 , G11C16/10 , G11C16/28 , G11C2216/06 , G11C2216/08 , H01L21/28273 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11551 , H01L27/1203 , H01L29/42328 , H01L29/513 , H01L29/66825 , H01L29/7613 , H01L29/785 , H01L29/7888
摘要： A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

25. 发明申请

US20060087117A1 Tube fitting 审中-公开
公开(公告)号：US20060087117A1
公开(公告)日：2006-04-27
申请号：US11301535
申请日：2005-12-13
申请人： Hidesaburo Ishii , Kazuo Yano
发明人： Hidesaburo Ishii , Kazuo Yano
IPC分类号： F16L13/00
CPC分类号： F16L37/00 , F16L55/041 , F16L2201/00
摘要： A tube fitting capable of absorbing vibration and shock resulting from a high pressure fluid passing through the tube fitting while it is used includes a connection head, a connection nipple, and an intermediate connection member. The connection head and the connection nipple are provided with an annular collar projecting from an end surface of the connection head and the connection nipple. The connection head, the connection nipple and the intermediate connection member are joined by inserting the annular collars into both ends of the intermediate connection member.

26. 发明授权

US07009243B2 Semiconductor memory device 失效
公开(公告)号：US07009243B2
公开(公告)日：2006-03-07
申请号：US10985946
申请日：2004-11-12
申请人： Tomoyuki Ishii , Kazuo Yano
发明人： Tomoyuki Ishii , Kazuo Yano
IPC分类号： H01L29/788
CPC分类号： G11C11/405 , G11C11/404 , H01L27/0688 , H01L27/115 , H01L27/11551 , H01L27/1156
摘要： A semiconductor memory device comprises a first transistor including a source region, a drain region, a first channel region of a semiconductor material formed on an insulating film and connecting the source region and the drain region, and a gate electrode for controlling potential of the first channel region; a second transistor including a source region, a drain region, a second channel region of a semiconductor material connecting the source region and the drain region, a second gate electrode for controlling potential of the second channel region, and a charge storage region coupled with the second channel region by electrostatic capacity; wherein the source region of the second transistor is connected to a source line, one end of the source or the drain region of the first transistor is connected to the charge storage region of the second transistor, the other end of the source or the drain region of the first transistor is connected to a data line.

27. 发明授权

US06970017B2 Logic circuit 失效
标题翻译：逻辑电路
公开(公告)号：US06970017B2
公开(公告)日：2005-11-29
申请号：US09946440
申请日：2001-09-06
申请人： Yohei Akita , Naoki Kato , Kazuo Yano
发明人： Yohei Akita , Naoki Kato , Kazuo Yano
IPC分类号： H03K3/356 , H03K3/3562 , H03K17/693 , H03K19/094
CPC分类号： H03K3/356156 , H03K3/35625 , H03K17/693
摘要： There is provided a logic circuit causing the same delay time as a conventional logic circuit and acting as a D flip-flop circuit with a data-selecting function.A logic circuit having the circuitry shown in FIG. 6 will be described briefly. Two transmission gates TG10a (TG10b) and TG11 and two inverters IV10 and IV11 are used to define a data propagation path from an input port I1 (I2) to an output port O1. Thus, four logic gates are located along the path in the same manner as they are in a conventional D flip-flop circuit. The transmission gate TG10a (TG10b) is controlled using a NOR circuit 12a that inputs a clock CLK and a select signal /sel that is the reverse of a select signal sel (NOR circuit 12b that inputs the clock CLK and the select signal sel). The transmission gate TG11 is controlled with the clock CLK. Either of two input data items is selected based on the select signals, and then output.When a D flip-flop circuit with a data-selecting function that causes the same delay time as a conventional D flip-flop circuit is adapted to a pipeline circuit, the action of the pipeline circuit can be speeded up.
摘要翻译：提供了与常规逻辑电路相同的延迟时间并用作具有数据选择功能的D触发器电路的逻辑电路。具有图1所示电路的逻辑电路。将简要描述图6。使用两个传输门TG10a（TG10b）和TG11以及两个反相器IV10和IV11来定义从输入端口I 1（I 2）到输出端口O 1的数据传播路径。因此，沿着路径以与常规D触发器电路中相同的方式定位四个逻辑门。传输门TG10a（TG10b）使用输入时钟CLK和与选择信号sel相反的选择信号/ sel（输入时钟CLK的NOR电路12b）的NOR电路12a和选择信号sel）。传输门TG11由时钟CLK控制。基于选择信号选择两个输入数据项之一，然后输出。当具有导致与常规D触发器电路相同的延迟时间的数据选择功能的D触发器电路适用于流水线电路时，可以加速流水线电路的动作。

28. 发明申请

US20050087797A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20050087797A1
公开(公告)日：2005-04-28
申请号：US10985946
申请日：2004-11-12
申请人： Tomoyuki Ishii , Kazuo Yano
发明人： Tomoyuki Ishii , Kazuo Yano
IPC分类号： H01L27/10 , B82B1/00 , G11C11/404 , G11C11/405 , H01L21/8242 , H01L27/06 , H01L27/108 , H01L27/115 , H01L29/788
CPC分类号： G11C11/405 , G11C11/404 , H01L27/0688 , H01L27/115 , H01L27/11551 , H01L27/1156
摘要： A semiconductor memory device comprises a first transistor including a source region, a drain region, a first channel region of a semiconductor material formed on an insulating film and connecting the source region and the drain region, and a gate electrode for controlling potential of the first channel region; a second transistor including a source region, a drain region, a second channel region of a semiconductor material connecting the source region and the drain region, a second gate electrode for controlling potential of the second channel region, and a charge storage region coupled with the second channel region by electrostatic capacity; wherein the source region of the second transistor is connected to a source line, one end of the source or the drain region of the first transistor is connected to the charge storage region of the second transistor, the other end of the source or the drain region of the first transistor is connected to a data line.
摘要翻译：半导体存储器件包括：第一晶体管，包括源极区，漏极区，形成在绝缘膜上并连接源极区和漏极区的半导体材料的第一沟道区;以及栅电极，用于控制第一渠道区域第二晶体管，包括源极区域，漏极区域，连接源极区域和漏极区域的半导体材料的第二沟道区域，用于控制第二沟道区域的电位的第二栅电极和与第二沟道区域耦合的电荷存储区域第二通道区域通过静电容量; 其中所述第二晶体管的源极区域连接到源极线，所述第一晶体管的源极或漏极区域的一端连接到所述第二晶体管的电荷存储区域，所述源极或漏极区域的另一端的第一晶体管连接到数据线。

29. 发明授权

US06845349B1 Method for designing semiconductor integrated circuit and automatic designing device 失效
标题翻译：半导体集成电路设计方法及自动设计装置
公开(公告)号：US06845349B1
公开(公告)日：2005-01-18
申请号：US09659735
申请日：2000-09-11
申请人： Yasuhiko Sasaki , Kazuo Yano , Shunzo Yamashita , Koichi Seki
发明人： Yasuhiko Sasaki , Kazuo Yano , Shunzo Yamashita , Koichi Seki
IPC分类号： G06F17/50 , H03K19/173 , G06G7/62
CPC分类号： H03K19/1737 , G06F17/505 , H03K19/1736
摘要： A program for automatically designing a logic circuit used for a method of designing a pass transistor circuit, by which the number of required transistors, delay time, power consumption and chip area of the pass transistor circuit is reduced. The program executes the following steps: a) receiving inputted logic functions which define the logical relationship between the inputs and the outputs, and an inputted target specification, b) generating a binary decision diagram from part of the logic functions received at (a), c) replacing the diagram nodes formed at (b) with pass transistor circuit, d) judging whether or not the simulation characteristics of the pass transistor circuit described in (c) meets the target specification described in (a), and executing the following steps when the judgment is “no”, e) replacing part of the diagram generated by the procedure described in (b) with another diagram, f) allocating a new binary decision diagram to the control inputs of the nodes of the replaced diagram prepared at (e), and g) repeating the steps (c) and (d) for the diagram prepared at (f).
摘要翻译：用于自动设计用于设计传输晶体管电路的方法的逻辑电路的程序，由此降低了所需晶体管的数量，延迟时间，功耗以及传输晶体管电路的芯片面积。该程序执行以下步骤：a）接收定义输入和输出之间的逻辑关系的输入逻辑功能以及输入的目标规范，b）从（a）中接收的部分逻辑函数生成二进制判定图， c）用传统晶体管电路代替（b）形成的图形节点，d）判断（c）中描述的传输晶体管电路的仿真特性是否满足（a）中描述的目标规范，并执行以下步骤当判断为“否”时，e）用另一个图替换由（b）中描述的过程产生的图的一部分，f）将新的二进制决策图分配给在 e），g）对（f）制备的图重复步骤（c）和（d）。

30. 发明授权

US06820242B2 Logic circuit including combined pass transistor and CMOS circuits and a method of synthesizing the logic circuit 失效
标题翻译：包括组合传输晶体管和CMOS电路的逻辑电路和合成逻辑电路的方法
公开(公告)号：US06820242B2
公开(公告)日：2004-11-16
申请号：US10178216
申请日：2002-06-25
申请人： Shunzo Yamashita , Kazuo Yano
发明人： Shunzo Yamashita , Kazuo Yano
IPC分类号： G06F1750
CPC分类号： H03K19/1736 , G06F17/505 , H03K19/1737
摘要： To produce a logic circuit with excellent characteristics including area, delay time and power consumption by combining pass transistor logic circuits and CMOS logic circuits, a binary decision diagram is created from a Boolean function. Respective nodes are mapped into 2-input, 1-output, 1-control input pass transistor selectors to synthesize a pass transistor logic circuit. A pass transistor selector operating as a NAND or NOR logic with any one of its two inputs, excluding the control input, being fixed to a logical constant “1” or “0” is replaced with a CMOS gate operating as a NAND or NOR logic logically equivalent to the pass transistor selector if the value of a predetermined circuit characteristic obtained by the replacement is closer to an optimal value.
摘要翻译：为了通过组合传输晶体管逻辑电路和CMOS逻辑电路来产生具有优异特性（包括面积，延迟时间和功耗）的逻辑电路，从布尔函数创建二进制决策图。各节点映射到2输入1输出1控制输入通道晶体管选择器，以合成传输晶体管逻辑电路。用作NAND或NOR逻辑的传输晶体管选择器被替换为操作为NAND或NOR逻辑的CMOS栅极，其两个输入中的任一个（不包括控制输入）被固定为逻辑常数“1”或“0” 如果通过替换获得的预定电路特性的值更接近于最佳值，则在逻辑上等效于通过晶体管选择器。

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