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21. 发明申请

US20070281390A1 Manufacturing method of a package substrate 审中-公开
标题翻译：封装衬底的制造方法
公开(公告)号：US20070281390A1
公开(公告)日：2007-12-06
申请号：US11727852
申请日：2007-03-28
申请人： Myung-Sam Kang , Je-Gwang Yoo , Jung-Hyun Park , Ji-Eun Kim , Hoe-Ku Jung , Jin-Yong An
发明人： Myung-Sam Kang , Je-Gwang Yoo , Jung-Hyun Park , Ji-Eun Kim , Hoe-Ku Jung , Jin-Yong An
IPC分类号： H01L21/00
CPC分类号： H01L21/4846 , H01L23/49827 , H01L2924/0002 , H05K3/064 , H05K3/108 , H05K3/242 , H05K3/243 , H05K3/427 , H05K2201/0376 , H05K2203/0361 , H05K2203/1394 , H01L2924/00
摘要： The present invention relates to a manufacturing method of a package substrate. A manufacturing method of a package substrate for mounting an electric component by connecting electrodes of the electric component to bonding pads, includes: manufacturing a buried pattern substrate having a circuit pattern and bonding pads buried in an insulating layer and having a seed layer laminated on the insulating layer, laminating a dry film onto the seed layer and removing the seed layer and the dry film of the upper side of the bonding pads, performing surface-treatment using the remaining seed layer as a plating lead; and removing the remaining seed layer and the dry film such that the circuit pattern is exposed.
摘要翻译：本发明涉及封装基板的制造方法。一种用于通过将电气部件的电极连接到接合焊盘来安装电气部件的封装基板的制造方法，包括：制造具有电路图案的掩埋图案基板和埋在绝缘层中并具有层叠在所述绝缘层上的种子层的接合焊盘绝缘层，将干膜层压到种子层上，去除接合焊盘的上侧的种子层和干膜，使用剩余的种子层作为电镀引线进行表面处理; 并且除去剩余的种子层和干膜，使得电路图案被暴露。

22. 发明申请

US20070210439A1 Board on chip package and manufacturing method thereof 有权
标题翻译：片上封装及其制造方法
公开(公告)号：US20070210439A1
公开(公告)日：2007-09-13
申请号：US11715906
申请日：2007-03-09
申请人： Myung-Sam Kang , Chang-Sup Ryu , Jung-Hyun Park , Hoe-Ku Jung , Ji-Eun Kim
发明人： Myung-Sam Kang , Chang-Sup Ryu , Jung-Hyun Park , Hoe-Ku Jung , Ji-Eun Kim
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/3128 , H01L21/568 , H01L21/6835 , H01L23/13 , H01L24/16 , H01L24/48 , H01L24/81 , H01L2221/68345 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2224/81801 , H01L2924/00014 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/12044 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/1532 , H01L2924/30105 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An aspect of the present invention features a manufacturing method of a board on chip package. The method can comprise: (a) laminating a dry film on a carrier film, one side of which is laminated by a thin metal film; (b) patterning the dry film in accordance with a circuit wire through light exposure and developing process, and forming a solder ball pad and a circuit wire; (c) removing the dry film; (d) laminating an upper photo solder resist excluding a portion where the solder ball pad is formed; (e) etching the thin metal film formed on a portion where the upper photo solder resist is not laminated; (f) mounting a semiconductor chip on the solder ball pad by a flip chip bonding; (g) molding the semiconductor chip with a passivation material; (h) removing the carrier film and the thin metal film; and (i) laminating a lower photo solder resist under the solder ball pad. The board on chip package and the manufacturing method thereof according to the present invention can design a high density circuit since a circuit pattern is formed using a seed layer.
摘要翻译：本发明的一个方面的特征在于片上封装的制造方法。该方法可以包括：（a）在载体膜上层压干膜，其一面由薄金属膜层压; （b）通过曝光和显影工艺根据电路线图案化干膜，并形成焊球焊盘和电路线; （c）去除干膜; （d）层压除了形成焊锡球焊盘的部分之外的上光阻焊剂; （e）蚀刻形成在上层光阻抗层未层叠的部分上的金属薄膜; （f）通过倒装芯片接合将半导体芯片安装在焊球垫上; （g）用钝化材料模制半导体芯片; （h）去除载体膜和金属薄膜; 和（i）在焊球垫下方层叠下光阻焊剂。根据本发明的片上封装及其制造方法可以设计高密度电路，因为使用种子层形成电路图案。

23. 发明授权

US08197702B2 Manufacturing method of printed circuit board 有权
标题翻译：印刷电路板的制造方法
公开(公告)号：US08197702B2
公开(公告)日：2012-06-12
申请号：US12508224
申请日：2009-07-23
申请人： Myung-Sam Kang , Jung-Hyun Park , Ji-Eun Kim
发明人： Myung-Sam Kang , Jung-Hyun Park , Ji-Eun Kim
IPC分类号： C25D5/02 , B32B37/00 , B32B38/00
CPC分类号： B32B37/02 , B32B2457/08 , C25D5/022 , H05K3/205 , H05K3/428 , H05K3/4658 , H05K2201/0376 , H05K2203/0384
摘要： Disclosed is a method of manufacturing a printed circuit board. The method of manufacturing a printed circuit board having a via for interlayer connection can include forming a circuit pattern on one side of a carrier, pressing one side of the carrier into one side of the insulator, removing the carrier, forming a hole penetrating through the insulator by processing one end of the circuit pattern, and forming a conductive material inside the hole to have the conductive material correspond to the via.
摘要翻译：公开了印刷电路板的制造方法。制造具有用于层间连接的通孔的印刷电路板的方法可以包括在载体的一侧上形成电路图案，将载体的一侧压在绝缘体的一侧，去除载体，形成贯穿该载体的孔通过处理电路图案的一端，并且在孔内形成导电材料以使导电材料对应于通孔。

24. 发明申请

US20100255634A1 Manufacturing method of bottom substrate of package 审中-公开
标题翻译：封装底部基板的制造方法
公开(公告)号：US20100255634A1
公开(公告)日：2010-10-07
申请号：US12801574
申请日：2010-06-15
申请人： Jung-Hyun Park , Byoung-Youl Min , Je-Gwang Yoo , Myung-Sam Kang , Hoe-Ku Jung , Ji-Eun Kim
发明人： Jung-Hyun Park , Byoung-Youl Min , Je-Gwang Yoo , Myung-Sam Kang , Hoe-Ku Jung , Ji-Eun Kim
IPC分类号： H01L21/60 , H01L21/50
CPC分类号： H01L23/3128 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06541 , H01L2225/06568 , H01L2225/06586 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01087 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A manufacturing method of bottom substrate of package. A bottom substrate of a package on package electrically connected to a top substrate by means of a solder ball, including a core board, a solder ball pad formed on a surface of the core board in correspondence with a location of the solder ball, an insulation layer laminated on the core board, a through hole formed by removing a part of the insulation layer such that the solder ball pad is exposed, and a metallic layer filled in the through hole and connected electrically with the solder ball, allows the number of ICs mounted on a bottom substrate to be increased without increasing the size of a solder ball, and allows the size and pitch of the solder balls to be made smaller by controlling the thickness of the insulation layer laminated on the bottom substrate, whereby more signal transmission is possible between a top substrate and a bottom substrate.
摘要翻译：封装底部基板的制造方法。封装的封装的底部衬底通过焊球电连接到顶部衬底，所述焊球包括芯板，与所述焊球的位置对应地形成在所述芯板的表面上的焊球焊盘，绝缘体层叠在芯板上的通孔，通过去除绝缘层的一部分使得焊球焊盘露出而形成的通孔以及填充在通孔中并与焊球电连接的金属层允许IC的数量安装在底部基板上以增加焊球的尺寸，并且通过控制层叠在底部基板上的绝缘层的厚度，可以使焊球的尺寸和间距变小，由此更多的信号传输是可能在顶部基板和底部基板之间。

25. 发明申请

US20080009128A1 Buried pattern substrate and manufacturing method thereof 审中-公开
标题翻译：埋地图案基板及其制造方法
公开(公告)号：US20080009128A1
公开(公告)日：2008-01-10
申请号：US11708339
申请日：2007-02-21
申请人： Shuhichi Okabe , Myung-Sam Kang , Jung-Hyun Park , Hoe-Ku Jung , Ji-Eun Kim
发明人： Shuhichi Okabe , Myung-Sam Kang , Jung-Hyun Park , Hoe-Ku Jung , Ji-Eun Kim
IPC分类号： H01L21/44
CPC分类号： H05K3/205 , H05K3/4038 , H05K3/4617 , H05K2203/0733 , H05K2203/1572
摘要： A buried pattern substrate and a manufacturing method thereof are disclosed. A method of manufacturing a buried pattern substrate having a circuit pattern formed on a surface, in which the circuit pattern is connected electrically by a stud bump, includes (a) forming the circuit pattern and the stud bump by depositing a plating layer selectively on a seed layer of a carrier film, where the seed layer is laminated on a surface of the carrier film, (b) laminating and pressing the carrier film on an insulation layer such that the circuit pattern and the stud bump face the insulation layer, and (c) removing the carrier film and the seed layer, allows the circuit interconnection to be realized using a copper (Cu) stud bump, so that a drilling process for interconnection is unnecessary, the degree of freedom for circuit design is improved, a via land is made unnecessary and the size of a via is small, to allow higher density in a circuit.
摘要翻译：公开了掩埋图案基板及其制造方法。一种制造埋设图形衬底的方法，其中电路图案形成在电路图形通过柱形凸块电连接的表面上，包括：（a）通过在晶种层层叠在载体膜的表面上的载体膜的种子层，（b）在绝缘层上层叠压制载体膜，使得电路图案和柱状凸块面向绝缘层，和 c）去除载体膜和种子层，允许使用铜（Cu）柱状凸块实现电路互连，使得不需要用于互连的钻孔工艺，提高了电路设计的自由度，通孔焊盘不必要，并且通孔的尺寸小，以允许电路中的较高密度。

26. 发明授权

US08003439B2 Board on chip package and manufacturing method thereof 有权
标题翻译：片上封装及其制造方法
公开(公告)号：US08003439B2
公开(公告)日：2011-08-23
申请号：US12385316
申请日：2009-04-03
申请人： Myung-Sam Kang , Chang-Sup Ryu , Jung-Hyun Park , Hoe-Ku Jung , Ji-Eun Kim
发明人： Myung-Sam Kang , Chang-Sup Ryu , Jung-Hyun Park , Hoe-Ku Jung , Ji-Eun Kim
IPC分类号： H01L21/00
CPC分类号： H01L23/3128 , H01L21/568 , H01L21/6835 , H01L23/13 , H01L24/16 , H01L24/48 , H01L24/81 , H01L2221/68345 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2224/81801 , H01L2924/00014 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/12044 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/1532 , H01L2924/30105 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of manufacturing a board on chip package including laminating a dry film on a carrier film, one side of which is laminated by a thin metal film; patterning the dry film in accordance with a circuit wire through light exposure and developing process, and forming a solder ball pad and a circuit wire; removing the dry film; laminating an upper photo solder resist excluding a portion where the solder ball pad is formed; etching the thin metal film formed on a portion where the upper photo solder resist is not laminated; mounting a semiconductor chip on the solder ball pad by a flip chip bonding; molding the semiconductor chip with a passivation material; removing the carrier film and the thin metal film; and laminating a lower photo solder resist under the solder ball pad. The board on chip package provides a high density circuit since a circuit pattern is formed using a seed layer.
摘要翻译：一种制造片上封装的方法，包括在载体膜上层叠干膜，其一面由薄金属膜层压; 通过曝光和显影工艺根据电路线图案化干膜，并形成焊球焊盘和电路线; 去除干膜; 层压除了形成焊球垫的部分之外的上光阻焊剂; 蚀刻形成在上层光阻焊层未层叠的部分上的金属薄膜; 通过倒装芯片焊接将半导体芯片安装在焊球垫上; 用钝化材料成型半导体芯片; 去除载体膜和金属薄膜; 并在焊球下方层叠下光阻焊剂。由于使用种子层形成电路图案，片上封装芯片提供了高密度电路。

27. 发明授权

US07858437B2 Method for manufacturing a substrate with cavity 有权
标题翻译：用于制造具有空腔的衬底的方法
公开(公告)号：US07858437B2
公开(公告)日：2010-12-28
申请号：US11706186
申请日：2007-02-15
申请人： Hoe-Ku Jung , Myung-Sam Kang , Ji-Eun Kim , Jung-Hyun Park
发明人： Hoe-Ku Jung , Myung-Sam Kang , Ji-Eun Kim , Jung-Hyun Park
IPC分类号： H01L21/44
CPC分类号： H01L21/481 , H01L23/13 , H01L24/73 , H01L25/105 , H01L25/50 , H01L2224/16 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06568 , H01L2225/1058 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/15331 , H05K1/183 , H05K3/205 , H05K3/4658 , H05K3/4697 , H05K2203/0568 , H05K2203/0571 , H05K2203/308 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： An aspect of the present invention features a method for manufacturing a substrate having a cavity. The method can comprises: (a) forming an upper layer circuit on an upper seed layer; (b) laminating a dry film on a portion of the upper seed layer where a cavity is to be formed; (c) fabricating an upper outer layer by forming an insulation layer on top of the upper seed layer and on top and sides of the upper layer circuit; (d) stacking the upper outer layer on one side of a core layer where an internal circuit is formed; (e) removing the upper seed layer; and (f) forming the cavity by removing the dry film. The method for manufacturing a substrate with a cavity according to the present invention can reduce the total thickness of the substrate while the thickness of an insulation layer remains the same, by forming the insulation layer on sides of an external circuit.
摘要翻译：本发明的一个方面的特征在于一种用于制造具有腔的衬底的方法。该方法可以包括：（a）在上部种子层上形成上层电路; （b）在要形成空腔的上种子层的一部分上层压干膜; （c）通过在上部种子层的顶部和上层电路的顶部和侧面上形成绝缘层来制造上部外层; （d）在形成有内部电路的芯层的一侧堆叠上外层; （e）去除上部种子层; 和（f）通过去除干膜形成空腔。根据本发明的用于制造具有腔的衬底的方法可以通过在外部电路的侧面上形成绝缘层来减小衬底的总厚度，同时绝缘层的厚度保持相同。

28. 发明申请

US20080105458A1 Substrate for mounting flip chip and the manufacturing method thereof 审中-公开
标题翻译：用于安装倒装芯片的基板及其制造方法
公开(公告)号：US20080105458A1
公开(公告)日：2008-05-08
申请号：US11976762
申请日：2007-10-26
申请人： Myung-Sam Kang , Jung-Hyun Park , Sang-Duck Kim , Ji-Eun Kim , Jong-Gyu Choi
发明人： Myung-Sam Kang , Jung-Hyun Park , Sang-Duck Kim , Ji-Eun Kim , Jong-Gyu Choi
IPC分类号： H05K1/09 , H05K3/00
CPC分类号： H01L23/13 , H01L21/4853 , H01L23/3114 , H01L23/49816 , H01L2924/00013 , H01L2924/0002 , H05K1/111 , H05K3/107 , H05K3/4007 , H05K2201/0367 , H05K2201/09745 , H05K2201/10674 , Y02P70/611 , Y10T29/49147 , H01L2224/29099 , H01L2924/00
摘要： A substrate for mounting a flip chip and a method of manufacturing the substrate method of manufacturing the substrate are disclosed. Using a method of manufacturing a substrate for flip chip mounting that includes providing an insulating layer, in which a circuit pattern is buried, and forming at least one bump pad shaped as an indentation by removing at least one portion of the circuit pattern, the bumps pads can be formed by removing portions of a circuit pattern in the shape of indentations, to prevent solder bumps from flowing to the insulating layer portions and reduce the pitch between bumps.
摘要翻译：公开了一种用于安装倒装芯片的基板和制造基板的制造方法的方法。使用制造用于倒装芯片安装的衬底的方法，其包括提供绝缘层，其中埋置电路图案，并且通过去除电路图案的至少一部分形成形成凹陷的至少一个凸块焊盘，所述凸块可以通过去除凹陷形状的电路图案的部分来形成焊盘，以防止焊料凸块流到绝缘层部分并降低凸块之间的间距。

29. 发明申请

US20070190764A1 Method for manufacturing a substrate with cavity 有权
标题翻译：用于制造具有空腔的衬底的方法
公开(公告)号：US20070190764A1
公开(公告)日：2007-08-16
申请号：US11706186
申请日：2007-02-15
申请人： Hoe-Ku Jung , Myung-Sam Kang , Ji-Eun Kim , Jung-Hyun Park
发明人： Hoe-Ku Jung , Myung-Sam Kang , Ji-Eun Kim , Jung-Hyun Park
IPC分类号： H01L21/20
CPC分类号： H01L21/481 , H01L23/13 , H01L24/73 , H01L25/105 , H01L25/50 , H01L2224/16 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06568 , H01L2225/1058 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/15331 , H05K1/183 , H05K3/205 , H05K3/4658 , H05K3/4697 , H05K2203/0568 , H05K2203/0571 , H05K2203/308 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： An aspect of the present invention features a method for manufacturing a substrate having a cavity. The method can comprises: (a) forming an upper layer circuit on an upper seed layer; (b) laminating a dry film on a portion of the-upper seed layer where a cavity is to be formed; (c) fabricating an upper outer layer by forming an insulation layer on top of the upper seed layer and on top and sides of the upper layer circuit; (d) stacking the upper outer layer on one side of a core layer where an internal circuit is formed; (e) removing the upper seed layer; and (f) forming the cavity by removing the dry film. The method for manufacturing a substrate with a cavity according to the present invention can reduce the total thickness of the substrate while the thickness of an insulation layer remains the same, by forming the insulation layer on sides of an external circuit.
摘要翻译：本发明的一个方面的特征在于一种用于制造具有腔的衬底的方法。该方法可以包括：（a）在上种子层上形成上层电路; （b）在要形成空腔的上部种子层的一部分上层叠干膜; （c）通过在上部种子层的顶部和上层电路的顶部和侧面上形成绝缘层来制造上部外层; （d）在形成有内部电路的芯层的一侧堆叠上外层; （e）去除上部种子层; 和（f）通过去除干膜形成空腔。根据本发明的用于制造具有腔的衬底的方法可以通过在外部电路的侧面上形成绝缘层来减小衬底的总厚度，同时绝缘层的厚度保持相同。

30. 发明申请

US20080098596A1 Method for forming transcriptional circuit and method for manufacturing circuit board 失效
标题翻译：转录电路形成方法及电路板制造方法
公开(公告)号：US20080098596A1
公开(公告)日：2008-05-01
申请号：US11976071
申请日：2007-10-19
申请人： Sang-Duck Kim , Jung-Hyun Park , Hoe-Ku Jung , Jong-Gyu Choi , Ji-Eun Kim , Jeong-Woo Park
发明人： Sang-Duck Kim , Jung-Hyun Park , Hoe-Ku Jung , Jong-Gyu Choi , Ji-Eun Kim , Jeong-Woo Park
IPC分类号： H05K3/20
CPC分类号： H05K3/20 , H05K3/205 , H05K3/207 , H05K3/386 , H05K2203/0113 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49158 , Y10T29/49163
摘要： A method for forming transcriptional circuits and a method for manufacturing a circuit board are disclosed. A method of forming a transcriptional circuit, which includes forming an intaglio pattern corresponding to a circuit pattern by selectively forming a resist on a mold board, filling conductive material in the intaglio pattern, and transferring the conductive material onto a carrier by pressing the carrier onto the mold board such that the carrier faces the surface of the mold board having the conductive material filled in, makes it possible to form transcriptional circuits that can be transcribed into an insulation board using existing equipment, whereby costs can be reduced.
摘要翻译：公开了一种形成转录电路的方法及其制造方法。一种形成转录电路的方法，其包括通过在模板上选择性地形成抗蚀剂来形成对应于电路图案的凹版图案，将导电材料填充到凹版图案中，以及通过将载体压载到载体上而将载体转移到使得载体面向具有填充有导电材料的模板的表面的模板，使得可以形成可以使用现有设备转录成绝缘板的转录电路，由此可以降低成本。

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