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21. 发明授权

US06947239B2 Magnetic storage device equipped with write driver circuit capable of performing impedance matching by a simple circuit 失效
标题翻译：具有能够通过简单电路执行阻抗匹配的写入驱动电路的磁存储装置
公开(公告)号：US06947239B2
公开(公告)日：2005-09-20
申请号：US10638785
申请日：2003-08-11
申请人： Yasuhiko Takahashi
发明人： Yasuhiko Takahashi
IPC分类号： G11B5/09 , G11B5/00 , G11B5/012 , G11B5/02
CPC分类号： G11B5/022 , G11B5/012 , G11B5/02 , G11B2005/001 , G11B2005/0013
摘要： A magnetic storage device equipped with a write driver circuit is provided. This magnetic storage device includes: four current sources each provided at a corresponding one of the four sides of an “H-bridge” circuit; a magnetic head provided at the bridging part of the “H-bridge” circuit; and a series circuit including capacitors and terminating resistors. A separate series circuit is provided between the ground and each corresponding one of the connection points of the bridging part and the four sides of the “H-bridge” circuit. With this magnetic storage device, impedance matching can be easily performed. Also, a smaller circuit size can be realized, and accordingly, the power consumption can be reduced. Furthermore, desired recording can be performed at a high transfer rate.
摘要翻译：提供一种配有写驱动电路的磁存储装置。这种磁存储装置包括：四个电流源，每个电流源设置在“H桥”电路的四个相应的一侧; 设置在“H桥”电路的桥接部分的磁头; 以及包括电容器和终端电阻器的串联电路。在桥接部分和“H桥”电路的四侧的连接点的每个相应的一个连接点之间提供单独的串联电路。利用该磁存储装置，可以容易地进行阻抗匹配。此外，可以实现更小的电路尺寸，因此能够降低功耗。此外，可以以高传送速率执行期望的记录。

22. 发明授权

US06346843B2 Clock signal generating circuit using variable delay circuit 失效
标题翻译：时钟信号发生电路采用可变延迟电路
公开(公告)号：US06346843B2
公开(公告)日：2002-02-12
申请号：US09843795
申请日：2001-04-30
申请人： Yasuhiko Takahashi
发明人： Yasuhiko Takahashi
IPC分类号： H03H1126
CPC分类号： H03L7/0805 , G06F1/10 , H03L7/0814 , H03L7/085
摘要： In an high-frequency LSI chip, a clock signal generating circuit establishes accurate synchronization between an input clock signal and an internal clock signal to prevent an input circuit from causing a synchronization shift. The clock signal generating circuit includes an input circuit for amplifying an input signal and outputting an amplified signal as a first internal signal; a variable delay circuit, on the basis of a control signal, for delaying the first internal signal and outputting a delayed signal as a second internal signal; a phase comparator for finding a phase difference between the input signal and second internal signal and outputting a phase difference signal indicative of the phase difference; and a control circuit for generating the control signal on the basis of the phase difference signal. Thus, the influences of a delay caused by the input circuit, which would not be avoided in the prior art, can be avoided and the accurate internal clock signal can be generated.
摘要翻译：在高频LSI芯片中，时钟信号发生电路在输入时钟信号和内部时钟信号之间建立精确的同步，以防止输入电路引起同步偏移。时钟信号发生电路包括用于放大输入信号并输出放大信号作为第一内部信号的输入电路; 基于控制信号的可变延迟电路，用于延迟所述第一内部信号并输出延迟的信号作为第二内部信号; 相位比较器，用于求出输入信号和第二内部信号之间的相位差，并输出指示相位差的相位差信号; 以及控制电路，用于根据相位差信号产生控制信号。因此，可以避免在现有技术中不能避免的由输入电路引起的延迟的影响，并且可以产生精确的内部时钟信号。

23. 发明授权

US5383033A Image processor for an improved tone level expression 失效
标题翻译：图像处理器，用于改善色阶表达
公开(公告)号：US5383033A
公开(公告)日：1995-01-17
申请号：US965791
申请日：1992-10-23
申请人： Yasuhiko Takahashi
发明人： Yasuhiko Takahashi
IPC分类号： G06T5/00 , H04N1/405 , H04N1/40
CPC分类号： H04N1/4051 , H04N1/4052
摘要： An image processor comprises means for determining generation of a dot by a dither method when an inputted data is a low gray level region not larger than a first threshold, means for generating a dot and distributing an error in a peripheral area when the inputted data is in a high gray level region larger than a second threshold, and means for generating a dot and distributing an error in a peripheral area when the inputted data is in a region higher than an intermediate gray level region larger than the first threshold and not larger than the second threshold, and for generating no dot and distributing an error the portion by which the inputted data exceeds the first threshold in a peripheral area as error, so that different tone level processing is performed in accordance with the gray level of the inputted data.
摘要翻译：图像处理器包括当输入的数据是不大于第一阈值的低灰度级区域时通过抖动方法确定点的生成的装置，当输入的数据为在大于第二阈值的高灰度级区域中，以及用于当所输入的数据位于比所述第一阈值大于所述第一阈值的中间灰度级区域高的区域时，生成点并在外围区域中分配错误的装置第二阈值，并且用于不产生点并且在周边区域中将输入的数据超过第一阈值的部分作为错误分配，使得根据输入的数据的灰度级执行不同的音调电平处理。

24. 发明授权

US5278671A Image processing apparatus with correction of diffusion errors of overlapping dots 失效
标题翻译：具有校正重叠点扩散误差的图像处理装置
公开(公告)号：US5278671A
公开(公告)日：1994-01-11
申请号：US770053
申请日：1991-10-04
申请人： Yasuhiko Takahashi , Akira Higashide , Hiroto Yamada
发明人： Yasuhiko Takahashi , Akira Higashide , Hiroto Yamada
IPC分类号： H04N1/405 , H04N1/21 , H04N1/40
CPC分类号： H04N1/4052
摘要： An image processing apparatus in which, when a multi-tone image is printed by using an error diffusion technique, error data to be diffused is modified so that the tone level of the image data as printed varies linearly with variation of an input image data. A printed dot of a pixel has a larger area than that of the theoretical pixel so that the dot juts out into adjacent pixels. The error data to be diffused is modified in consideration of jut-out dot areas of adjacent pixels, so as to obtain a linear variation of the tone-level with variation of the input image data.
摘要翻译：一种图像处理装置，其中，当通过使用误差扩散技术打印多色调图像时，修改要扩散的误差数据，使得打印的图像数据的色调电平随着输入图像数据的变化而线性变化。像素的打印点的面积大于理论像素的面积，使得点突出到相邻像素中。考虑到相邻像素的突出点区域来修改要扩散的误差数据，以便通过输入图像数据的变化来获得色调级的线性变化。

25. 发明授权

US4918977A Liquid leakage detector line 失效
标题翻译：液体检漏仪线
公开(公告)号：US4918977A
公开(公告)日：1990-04-24
申请号：US103478
申请日：1987-09-30
申请人： Yasuhiko Takahashi , Kunimitsu Tamura , Nagato Niimura , Keizo Asao , Teruyosi Honoki , Tadaaki Masui , Masuo Ishizaka
发明人： Yasuhiko Takahashi , Kunimitsu Tamura , Nagato Niimura , Keizo Asao , Teruyosi Honoki , Tadaaki Masui , Masuo Ishizaka
IPC分类号： G01M3/04
CPC分类号： G01M3/045
摘要： The present invention relates to a liquid leakage detector line for detecting the leakage, if occurs, of a liquid such as sulfuric acid or strong alkali from a transportion pipe line or a storage tank. The liquid leakage detector line comprises: a pair of wiry electrodes each including a conductor covered with an insulator layer made of macromolecular material including an ester bond, the wiry electrodes being disposed substantially in parallel with each other; and a liquid-absorbent material covering these wiry electrodes. The liquid-absorbent material may be a braided body layer made of liquid-absorbent yarn which is disposed outside of the pair of wiry electrodes, or may be a braided body layer similar to the first-mentioned braided body layer which is disposed at the outer periphery of each of the wiry electrodes. If a sulfuric acid or alkali liquid leaks, the liquid-absorbent material covering the wiry electrodes absorbs such leakage liquid. The liquid thus absorbed causes the insulator layers to dissolve to short-circuit the conductors. The insulation resistance between the conductors is measured from one end of the liquid leakage detector line. The decrease in insulation resistance is detected to detect liquid leakage.
摘要翻译：液体泄漏检测器线路技术领域本发明涉及一种液体泄漏检测器线路，用于检测来自运输管线或储罐的液体如硫酸或强碱的泄漏（如果发生）。液体泄漏检测器线包括：一对wiry电极，每个包括导体，覆盖有由包括酯键的高分子材料制成的绝缘体层，导线电极基本上彼此平行地设置; 以及覆盖这些wiry电极的吸液材料。吸液材料可以是设置在一对电极的外侧的吸液性纱线的编织体层，也可以是与设置在外侧的第一提到的编织体层相似的编织体层每个wiry电极的周边。如果硫酸或碱液体泄漏，覆盖电极的吸液材料会吸收这种泄漏液体。这样吸收的液体导致绝缘体层溶解以使导线短路。从液体泄漏检测器线的一端测量导体之间的绝缘电阻。检测到绝缘电阻的下降以检测液体泄漏。

26. 发明授权

US07981738B2 Semiconductor memory device and a method of manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07981738B2
公开(公告)日：2011-07-19
申请号：US12909878
申请日：2010-10-22
申请人： Masahiro Moniwa , Hiraku Chakihara , Kousuke Okuyama , Yasuhiko Takahashi
发明人： Masahiro Moniwa , Hiraku Chakihara , Kousuke Okuyama , Yasuhiko Takahashi
IPC分类号： H01L21/8238 , H01L21/8234
CPC分类号： H01L27/11 , G11C11/412 , H01L27/1104
摘要： A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.
摘要翻译： SRAM的存储单元具有两个驱动MISFET和两个垂直MISFET。 p沟道垂直MISFET形成在n沟道驱动MISFET的上方。垂直MISFET分别主要包括由下半导体层，中间半导体层和按此顺序层叠的上半导体层形成的层压体，形成在层叠体的侧壁表面上的氧化硅栅极绝缘膜和栅电极形成为覆盖层压体的侧壁。垂直MISFET是完全耗尽型MISFET。

27. 发明申请

US20110129848A1 Antibody Recognizing G Protein, and Agent and Kit Using the Same 审中-公开
标题翻译：抗体识别G蛋白，以及使用其的药剂和试剂盒
公开(公告)号：US20110129848A1
公开(公告)日：2011-06-02
申请号：US13018546
申请日：2011-02-01
申请人： Yasuhiko Takahashi , Yasuo Matsumoto , Kenji Oeda
发明人： Yasuhiko Takahashi , Yasuo Matsumoto , Kenji Oeda
IPC分类号： G01N33/68 , C07K16/18
CPC分类号： C07K14/4722
摘要： A novel protein (Gm1) includes an amino acid sequence part having a high homology with a domain having a high homology with a GTP binding site and a GTPase site conserved among G protein α subunits and a trimer forming domain conserved among G protein α subunits. The Gm1 protein is involved in signal transduction via a G protein-coupled receptor (GPCR) stimulation. The Gm1 protein is expressed intensively in human brain, thymus, testes, spleen, small intestine, uterus and heart. A method for screening for a substance capable of regulating a cellular signal transduction employs a polynucleotide encoding the Gm1 protein
摘要翻译：一种新型蛋白质（Gm1）包括与G蛋白α亚基保守的G蛋白α亚基和三聚体形成结构域在G蛋白α亚基中保守的与GTP结合位点和GTP酶位点高度同源的结构域具有高度同源性的氨基酸序列部分。 Gm1蛋白通过G蛋白偶联受体（GPCR）刺激参与信号转导。 Gm1蛋白在人脑，胸腺，睾丸，脾脏，小肠，子宫和心脏中都集中表达。筛选能够调节细胞信号转导的物质的方法采用编码Gm1蛋白的多核苷酸

28. 发明授权

US07852584B2 Head IC, read circuit, and media storage device 失效
标题翻译：头IC，读电路和媒体存储设备
公开(公告)号：US07852584B2
公开(公告)日：2010-12-14
申请号：US12004797
申请日：2007-12-21
申请人： Jyunko Matsui , Yasuhiko Takahashi
发明人： Jyunko Matsui , Yasuhiko Takahashi
IPC分类号： G11B5/09
CPC分类号： G11B5/09
摘要： A head IC adjusts an amplitude level of head read signals with regard to scattering in head output characteristics, so as to conform to the input dynamic range of the read channel AGC. An AGC amplifier is provided in a head IC connected to a read channel, and the feedback response speed of the AGC circuit of the head IC is set to be substantially slower than the feedback response speed of the AGC circuit of the read channel. Within the head IC, the amplitude of signals from the head is automatically adjusted, enabling adjustment of the input signal level to the input dynamic range of the AGC amplifier of the read channel. The AGC circuit of the head IC has no effect on the faster AGC operation of the AGC circuit of the read channel.
摘要翻译：头部IC调整头部读取信号的幅度水平，关于头部输出特性中的散射，以便符合读取通道AGC的输入动态范围。 AGC放大器设置在连接到读通道的头IC中，并且头IC的AGC电路的反馈响应速度被设置为比读通道的AGC电路的反馈响应速度慢。在头IC内，来自头部的信号的幅度被自动调节，使得能够将输入信号电平调节到读通道的AGC放大器的输入动态范围。头IC的AGC电路对读通道的AGC电路的较快的AGC操作没有影响。

29. 发明授权

US07606003B2 Electrical device for interconnecting magnetic head and driving circuit which uses adjusted length wires of opposite polarity to reduce crosstalk and storage apparatus including same 失效
标题翻译：用于互连磁头和驱动电路的电气装置，其使用相反极性的调节长度的线以减少串扰和包括其的存储装置
公开(公告)号：US07606003B2
公开(公告)日：2009-10-20
申请号：US11385474
申请日：2006-03-21
申请人： Yoshihiro Amemiya , Tetsuyuki Kubota , Yasuhiko Takahashi
发明人： Yoshihiro Amemiya , Tetsuyuki Kubota , Yasuhiko Takahashi
IPC分类号： G11B5/55
CPC分类号： G11B5/486
摘要： A storage apparatus and a magnetic head driving device includes a recording/reproducing head including a write element and a magnetoresistive element, a driving circuit for driving the write element and the magnetoresistive element, and write wires and read wires which connect the recording/reproducing head to the driving circuit. The write wires and the read wires are disposed in parallel in at least a portion between the recording/reproducing head and the driving circuit. At a location between the recording/reproducing head and the driving circuit, either of the write wires and the read wires are disposed so that a polarity of the either of the write wires and the read wires is reversed with respect to a polarity of the other of the write wires and the read wires.
摘要翻译：一种存储装置和磁头驱动装置，包括具有写入元件和磁阻元件的记录/再现头，用于驱动写入元件和磁阻元件的驱动电路，以及连接记录/再现头的写入线和读取线到驱动电路。写入线和读取线在记录/再现头与驱动电路之间的至少一部分上平行设置。在记录/再现头和驱动电路之间的位置处，写入线和读取线都被设置成使得写入线和读取线中的任一个的极性相对于另一个的极性反转的写入线和读取的线。

30. 发明申请

US20090042789A1 Method for Improving Symptom of Mood Disorder 审中-公开
标题翻译：改善情绪障碍症状的方法
公开(公告)号：US20090042789A1
公开(公告)日：2009-02-12
申请号：US11914834
申请日：2006-05-17
申请人： Yasuhiko Takahashi , Kenji Oeda
发明人： Yasuhiko Takahashi , Kenji Oeda
IPC分类号： A61K38/16 , C07K14/00 , A01K67/00 , A61K31/7052 , C12Q1/68 , A61P25/00 , G01N33/68 , G01N33/53 , C12N5/00 , C07H21/00
CPC分类号： G01N33/6872 , A01K67/0275 , A01K2217/05 , A01K2227/105 , A01K2267/0356 , A61K38/00 , A61K48/00 , C07K14/47 , C12N15/8509 , G01N33/6896 , G01N2333/4719 , G01N2500/00 , G01N2800/304
摘要： The present invention relates to a method for improving symptom of mood disorder or its related disorder comprising a step of allowing activated-type Gm1 protein and the like to be excessively present in a brain of a mammal, and a non-human mammal, to which the method has been applied, and the like.
摘要翻译：本发明涉及改善情绪障碍或其相关疾病症状的方法，其包括使活化型Gm1蛋白等过量存在于哺乳动物和非人哺乳动物的脑中的步骤，其中已经应用了该方法等。

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