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21. 发明授权

US07068713B2 Digital filter circuit 失效
公开(公告)号：US07068713B2
公开(公告)日：2006-06-27
申请号：US10206673
申请日：2002-07-29
申请人： Motoya Iwasaki
发明人： Motoya Iwasaki
IPC分类号： H03K5/159 , H04B1/10
CPC分类号： H03H17/0226 , H03H17/0607
摘要： A digital filter circuit includes a decoder, ROM tables, multipliers, and an adder. The decoder decomposes an input multilevel signal into a plurality of 1-bit signals. The ROM tables output filter waveforms stored in advance, on the basis of the 1-bit signals output from the decoder. The multipliers and adder execute a plurality of weighting operations for the respective bits of outputs from the ROM tables and then add the outputs.

22. 发明授权

US06999734B2 Nonlinear compensating circuit, base-station apparatus, and transmission power clipping method 有权
标题翻译：非线性补偿电路，基站装置和发射功率削波方法
公开(公告)号：US06999734B2
公开(公告)日：2006-02-14
申请号：US10304850
申请日：2002-11-27
申请人： Motoya Iwasaki
发明人： Motoya Iwasaki
IPC分类号： H04B1/04
CPC分类号： H04W52/367 , H03G11/04 , H04B2201/70706
摘要： A nonlinear compensating circuit, a base-station apparatus and a transmission power clipping method for executing a clipping operation in a high output amplifier at the transmitting end during multicarrier amplification. A plurality of power converting circuits calculate power values of respective input signals. An adder adds up the calculated power values to obtain a synthetic power value P. A divider divides a predetermined threshold value T by the synthetic power value P. When the divided value T/P is equal to or more than 1, a determining circuit outputs a clip control signal for turning off the clipping operation to a plurality of clipping circuits. When the divided value T/P is less than 1, the clip control signal turn on the clipping operation.
摘要翻译：一种用于在多载波放大期间在发送端的高输出放大器中执行限幅操作的非线性补偿电路，基站装置和发射功率削波方法。多个功率转换电路计算各个输入信号的功率值。加法器将计算的功率值相加以获得合成功率值P.分频器将预定阈值T除以合成功率值P.当分频值T / P等于或大于1时，确定电路输出用于将削波操作截止到多个限幅电路的剪辑控制信号。当分割值T / P小于1时，剪辑控制信号打开剪辑操作。

23. 发明授权

US5912930A Phase shift keying signal demodulation method and device 失效
标题翻译：相移键控信号解调方法及装置
公开(公告)号：US5912930A
公开(公告)日：1999-06-15
申请号：US825764
申请日：1997-04-01
申请人： Motoya Iwasaki
发明人： Motoya Iwasaki
IPC分类号： H04L27/22 , H04L27/227 , H03D3/00 , H03D3/22 , H04L27/152
CPC分类号： H04L25/03885 , H04L27/2276
摘要： The invention provides a PSK signal demodulation device of small circuit scale that is capable of both rapid synchronization pull-in and stable demodulation operation following demodulation synchronization pull-in. To achieve these capabilities, the phase shift keying signal demodulation device of this invention is provided with an adaptive line enhancer demodulation circuit, a PLL demodulation circuit, and a switching circuit that switches the demodulation circuits from the adaptive line enhancer demodulation circuit to the PLL demodulation circuit. The switching circuit switches between the demodulation circuits such that, upon start of input of an N-phase PSK signal, demodulation is effected by the adaptive line enhancer demodulation circuit until phase synchronization is established between the input N-phase PSK signal and the recovered carrier, and demodulation is effected by the PLL demodulation circuit after establishment of phase synchronization.
摘要翻译：本发明提供一种小型电路规模的PSK信号解调装置，其能够在解调同步拉入之后进行快速同步拉入和稳定的解调操作。为了实现这些能力，本发明的相移键控信号解调装置设置有自适应线路增强器解调电路，PLL解调电路和切换电路，其将解调电路从自适应线路增强器解调电路切换到PLL解调电路。开关电路在解调电路之间切换，使得在开始输入N相PSK信号时，解调由自适应线路增强器解调电路实现，直到在输入的N相PSK信号和恢复的载波之间建立相位同步并且在相位同步建立之后由PLL解调电路进行解调。

24. 发明授权

US5838797A Secure communication by encryption/decryption of vector at PSK modulation/detection stage 失效
标题翻译：通过PSK调制/检测阶段的向量的加密/解密来保证通信
公开(公告)号：US5838797A
公开(公告)日：1998-11-17
申请号：US576968
申请日：1995-12-26
申请人： Motoya Iwasaki
发明人： Motoya Iwasaki
IPC分类号： H04L27/18 , H04K1/00 , H04L9/00 , H04L9/20 , H04L27/00 , H04L27/20 , H04L27/22 , H04L27/233 , H04M1/68
CPC分类号： H04L27/2332 , H04K1/006 , H04L27/2067 , H04L2027/003 , H04L2027/0057
摘要： At the transmit end of a secure communication system, an input data symbol is mapped to a corresponding vector in a two-dimensional phase plane. The vector is pseudorandomly phase-rotated in a first direction according to a unique pseudorandom number and quadrature-modulated on a carrier for transmission. At the receive end, a quadrature detector quasi-synchronously quadrature-detects the transmitted carrier with a local carrier to recover a vector, which is pseudorandomly phase-rotated according to a pseudorandom number identical to the unique pseudorandom number in a second direction opposite to the first direction. A quadrature demodulator detects a phase error of the local carrier with respect to the received carrier and provides quadrature-demodulation on the oppositely phase-rotated vector using the detected phase error.
摘要翻译：在安全通信系统的发送端，将输入数据符号映射到二维相平面中的相应向量。该向量根据唯一的伪随机数在第一方向上伪随机相位旋转，并在载波上进行正交调制以进行传输。在接收端，正交检波器准同步正交检波用本地载波进行发送的载波，以恢复向量，该矢量根据与第二方向相反的第二方向的唯一伪随机数的伪随机数伪随机相位旋转第一个方向正交解调器检测相对于接收的载波的本地载波的相位误差，并使用检测到的相位误差在相反相位旋转矢量上提供正交解调。

25. 发明授权

US5384552A Clock recovery circuit for extracting clock information from a received baseband signal 失效
标题翻译：用于从接收的基带信号中提取时钟信息的时钟恢复电路
公开(公告)号：US5384552A
公开(公告)日：1995-01-24
申请号：US157698
申请日：1993-11-24
申请人： Motoya Iwasaki
发明人： Motoya Iwasaki
IPC分类号： H03H15/00 , H04B1/10 , H04B3/04 , H04B14/04 , H04J3/06 , H04L7/00 , H04L7/02 , H04L7/033 , H03L7/00
CPC分类号： H04L7/0029
摘要： In a clock recovery circuit, an asynchronous oscillator generates a first clock pulse at a frequency n times the frequency of a baseband signal. A sampler samples the baseband signal in response to the first clock pulses. A flip-flop holds and delivers the sampled signal in response to a second clock pulse supplied from a voltage-controlled oscillator. The time difference between the first clock pulse and the second clock pulse is detected and a set of tap-gain values is selected according to the time difference. The sample delivered from the flip-flop is successively delayed by a tapped delay line to produce tap signals which are respectively weighted with the selected tap-gain values. The weighted samples are summed to estimate an intermediate sample. A clock phase error of the estimated sample with respect to the clock timing of the transmitted signal is determined for controlling the VCO.
摘要翻译：在时钟恢复电路中，异步振荡器产生频率为基带信号频率n倍的第一时钟脉冲。采样器响应于第一个时钟脉冲采样基带信号。触发器保持并传送采样信号以响应从压控振荡器提供的第二时钟脉冲。检测第一时钟脉冲和第二时钟脉冲之间的时间差，并根据时间差选择一组抽头增益值。从触发器传送的样本被抽头延迟线连续延迟，以产生分别用选择的抽头增益值加权的抽头信号。将加权样本相加以估计中间样本。确定相对于发送信号的时钟定时的估计采样的时钟相位误差用于控制VCO。

26. 发明授权

US5276710A Carrier frequency error detector capable of accurately detecting a carrier frequency error 失效
标题翻译：载波频率误差检测器能够准确检测载波频率误差
公开(公告)号：US5276710A
公开(公告)日：1994-01-04
申请号：US921711
申请日：1992-07-30
申请人： Motoya Iwasaki
发明人： Motoya Iwasaki
IPC分类号： H04L7/04 , H04L27/00 , H04L27/233 , H04L27/06
CPC分类号： H04L27/2332 , H04L2027/003 , H04L2027/0065 , H04L2027/0095 , H04L7/042
摘要： On detecting a carrier frequency error in a received signal, a correlation unit (12) detects a correlated signal in signals which a transmission unique word signal in the received signal and a local unique word signal are differentially detected. A frequency fine detection unit (17) detects a fine frequency error by using the correlated signal and a frame timing signal. A frequency coarse detection unit (21) detects a coarse frequency error by using the buffered signal from a data buffer (20) and the frame timing signal. A first adder (25) adds the fine frequency error to the coarse frequency error to a first added signal. A second adder (31) adds the first added signal to a maximum power frequency detected by a maximum power frequency detection unit (27) to produce the carrier frequency error.
摘要翻译：在检测到接收信号中的载波频率误差时，相关单元（12）检测接收信号中的发送唯一字信号和本地唯一字信号被差分检测的信号中的相关信号。频率精细检测单元（17）通过使用相关信号和帧定时信号来检测精细频率误差。频率粗略检测单元（21）通过使用来自数据缓冲器（20）的缓冲信号和帧定时信号来检测粗频率误差。第一加法器（25）将粗频率误差的精细频率误差与第一相加信号相加。第二加法器（31）将第一相加信号与由最大功率频率检测单元（27）检测到的最大功率频率相加，以产生载波频率误差。

27. 发明授权

US5157694A Coherent PSK demodulator using bit error rate and S/N ratio to establish synchronization 失效
标题翻译：使用位错误率和S / N比来建立同步的相关PSK解调器
公开(公告)号：US5157694A
公开(公告)日：1992-10-20
申请号：US824716
申请日：1992-01-17
申请人： Motoya Iwasaki , Susumu Otani
发明人： Motoya Iwasaki , Susumu Otani
IPC分类号： H04L27/22 , H04L27/00 , H04L27/18 , H04L27/227
CPC分类号： H04L27/2273 , H04L27/186 , H04L2027/0067 , H04L2027/0073 , H04L2027/0093
摘要： In a coherent M-ary PSK demodulator, an M-ary PSK detector demodulates a received M-ary PSK modulated convolutional code with a carrier recovered by a voltage-controlled oscillator to produce first and second channels of demodulated convolutional codes. A convolutional decoder decodes the signals of the first and second channels while correcting bit errors. An error rate detector is provided for detecting when the number of such errors occurring during a specified period of time is smaller than a predetermined value and generates a signal indicating that the convolutional decoder is synchronized with the demodulated signals. The power levels of signal and noise components of the demodulated channels are detected by a power detector. In a frequency control circuit, a series of VCO control signals of a different value are generated as candidates for precise synchronization in response to the signal from the error rate detector in order to synchronize the PSK detector successively at the candidate frequencies, and signal-to-noise ratios are successively derived from the outputs of the power detector. A maximum value of the derived signal-to-noise ratios is then detected and one of the candidate VCO control signals which corresponds to the detected maximum signal-to-noise ratio is adopted as a valid VCO control signal.

28. 发明授权

US5128626A Coherently demodulating arrangement including quasi-coherent demodulator for PSK signals 失效
标题翻译：相干解调装置包括用于PSK信号的准相干解调器
公开(公告)号：US5128626A
公开(公告)日：1992-07-07
申请号：US705747
申请日：1991-05-28
申请人： Motoya Iwasaki
发明人： Motoya Iwasaki
IPC分类号： H04L27/00 , H03D1/22 , H03L7/087 , H03L7/093 , H04L27/38
CPC分类号： H03L7/087 , H03D1/2254 , H03L7/093
摘要： An arrangement for coherently demodulating PSK (phase-shift keying) signals, includes a quasi-coherent demodulator which implements coarse coherent demodulation on an incoming PSK-modulated IF signal using a variable frequency which is applied from a controllable local oscillator. The output of the quasi-coherent demodulator is applied to a coherent demodulator which also receives the output of a VCO (Voltage Controlled Oscillator). A phase detector receives the output of the coherent demodulator and applies the output thereof to the VCO via a loop filter. The output of the loop filter is applied to a local oscillator controller having an output which is used to control the controllable local oscillator.
摘要翻译：用于相干解调PSK（相移键控）信号的装置包括准相干解调器，其使用从可控本地振荡器施加的可变频率对输入的PSK调制的IF信号实现粗略的相干解调。准相干解调器的输出被应用于同时接收VCO（压控振荡器）的输出的相干解调器。相位检测器接收相干解调器的输出，并通过环路滤波器将其输出提供给VCO。环路滤波器的输出被施加到具有用于控制可控本地振荡器的输出的本地振荡器控制器。

29. 发明授权

US08422602B2 Pattern detection circuit, base station and mobile communication system using the same, and pattern detecting method 有权
标题翻译：模式检测电路，基站和使用相同的移动通信系统，以及模式检测方法
公开(公告)号：US08422602B2
公开(公告)日：2013-04-16
申请号：US12372470
申请日：2009-02-17
申请人： Kyoichiro Masuda , Motoya Iwasaki
发明人： Kyoichiro Masuda , Motoya Iwasaki
IPC分类号： H04L27/06 , H04L7/00
CPC分类号： H04L27/2647
摘要： A pattern detection circuit for performing pattern detection on input signals from a communication terminal, includes a frequency domain transformer that transforms input signals into frequency domain signals; a frequency extractor that extracts frequency components of the frequency domain signals; and a pattern detector that performs the pattern detection on the input signals based on cross-correlation values in frequency domain between the extracted frequency components and predetermined patterns.
摘要翻译：用于对来自通信终端的输入信号执行模式检测的模式检测电路包括将输入信号变换为频域信号的频域变换器; 频率提取器，其提取频域信号的频率分量; 以及模式检测器，其基于所提取的频率分量和预定模式之间的频域中的互相关值，对输入信号执行模式检测。

30. 发明授权

US08345563B2 Wireless communication system, data transmission method for uplink thereof, base station device, and mobile station device 有权
标题翻译：无线通信系统，其上行链路的数据传输方法，基站装置和移动台装置
公开(公告)号：US08345563B2
公开(公告)日：2013-01-01
申请号：US12068082
申请日：2008-02-01
申请人： Shigeomi Oshiba , Motoya Iwasaki
发明人： Shigeomi Oshiba , Motoya Iwasaki
IPC分类号： H04W4/00 , H04W72/00 , H04J3/00 , H04J1/16 , H04B7/208 , H04B7/00 , H04B1/38
CPC分类号： H04W72/0406 , H04L1/001 , H04L1/0011 , H04L1/0016 , H04L1/0025 , H04L5/0007 , H04L5/0046 , H04L5/0094
摘要： A wireless base station sends transmission parameters that specify a control signal coding rate and a data signal coding rate which satisfy a BLER (Block Error Rate) required for a control signal and a data signal in a TTI (Transmit Time Interval) scheduled in response to a transmission request from a mobile station. In the specified TTI, the mobile station applies the coding rates, included in the transmission parameters and specified for the control signal and the data signal, to the control signal and the data signal, time-division multiplexes the coded control signal and coded data signal to generate constant transmission-power transmission data, and sends the generated transmission data to a wireless base station via PUSCH.
摘要翻译：无线基站发送指定控制信号编码率和数据信号编码率的传输参数，所述控制信号编码率和数据信号编码率满足响应于...的调度的TTI（发送时间间隔）中的控制信号和数据信号所需的BLER（块错误率）来自移动台的发送请求。在指定的TTI中，移动台将包含在传输参数中并为控制信号和数据信号指定的编码率应用于控制信号和数据信号，对编码的控制信号和编码数据信号进行时分复用以产生恒定的传输功率传输数据，并且经由PUSCH将生成的传输数据发送到无线基站。

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