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21. 发明申请

US20110001559A1 SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME 有权
标题翻译：半导体器件及其驱动方法
公开(公告)号：US20110001559A1
公开(公告)日：2011-01-06
申请号：US12614672
申请日：2009-11-09
申请人： Sang-Hoon SHIN , Hyung-Dong Lee , Jeong-Woo Lee , Hyang-Hwa Choi
发明人： Sang-Hoon SHIN , Hyung-Dong Lee , Jeong-Woo Lee , Hyang-Hwa Choi
IPC分类号： H01L25/00
CPC分类号： H01L25/0657 , H01L22/22 , H01L23/481 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/3011
摘要： A semiconductor device and a method for driving the same rapidly detect failure of a through-semiconductor-chip via and effectively repairing the failure using a latching unit assigned to each through-semiconductor-chip via. The semiconductor device includes a plurality of semiconductor chips that are stacked, and a plurality of through-semiconductor-chip vias to commonly transfer a signal to the plurality of semiconductor chips, wherein each of the semiconductor chips includes a multiplicity of latching units assigned to the through-semiconductor-chip vias and the multiplicity of latching units of each of the semiconductor chips constructs a boundary scan path including the plurality of through-semiconductor-chip vias to sequentially transfer test data.
摘要翻译：半导体器件及其驱动方法可以快速检测半导体芯片通孔的故障，并使用分配给每个贯通半导体芯片通孔的锁存单元有效地修复故障。半导体器件包括堆叠的多个半导体芯片，以及多个贯穿半导体芯片通孔，以共同地将信号传递到多个半导体芯片，其中每个半导体芯片包括分配给多个半导体芯片的多个锁存单元通过半导体芯片通孔，并且每个半导体芯片的多个锁存单元构成包括多个通过半导体芯片通孔的边界扫描路径以顺序地传送测试数据。

22. 发明授权

US07826300B2 Semiconductor memory apparatus 有权
标题翻译：半导体存储装置
公开(公告)号：US07826300B2
公开(公告)日：2010-11-02
申请号：US12347055
申请日：2008-12-31
申请人： Hyung-Wook Moon , Jeong-Woo Lee , Won-Jun Choi
发明人： Hyung-Wook Moon , Jeong-Woo Lee , Won-Jun Choi
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C7/1045 , G11C11/408
摘要： A semiconductor memory apparatus includes first and second bank blocks, a mode generator configured to generate a chip select mode signal used to control an operational mode of the first and second bank blocks, and a controller configured to drive the first and second bank blocks in response to the chip select mode signal, first and second select signals, and a predetermined address signal that are used to control driving of the first and second bank blocks, wherein the controller receives the chip select mode signal having a level used to determine a single chip mode to control operation of the first and second bank blocks in one rank unit, and the first and second bank blocks are selectively activated by using the predetermined address signal.
摘要翻译：半导体存储装置包括第一和第二存储块，模式发生器，被配置为产生用于控制第一和第二存储块的操作模式的芯片选择模式信号;以及控制器，被配置为响应于驱动第一和第二存储块与芯片选择模式信号，第一和第二选择信号以及用于控制第一和第二存储块的驱动的预定地址信号，其中控制器接收具有用于确定单个芯片的电平的芯片选择模式信号模式，以一个等级单位来控制第一和第二存储区块的操作，并且通过使用预定的地址信号来选择性地激活第一和第二存储体块。

23. 发明申请

US20100197072A1 Method of manufacturing a thin film solar cell 有权
标题翻译：制造薄膜太阳能电池的方法
公开(公告)号：US20100197072A1
公开(公告)日：2010-08-05
申请号：US12591943
申请日：2009-12-04
申请人： Tae-Youn Kim , Won-Seo Park , Jeong-Woo Lee , Seong-Kee Park , Kyung-Jin Shim
发明人： Tae-Youn Kim , Won-Seo Park , Jeong-Woo Lee , Seong-Kee Park , Kyung-Jin Shim
IPC分类号： H01L31/18
CPC分类号： H01L31/056 , H01L31/046 , H01L31/0463 , Y02E10/52
摘要： A method of manufacturing a thin film solar cell includes steps of preparing a substrate on which unit cells are defined, forming transparent conducive layers on the substrate and corresponding to the unit cells, respectively, the transparent conductive layers spaced apart from each other with a first separation line therebetween, forming light-absorbing layers on the transparent conductive layers and corresponding to the unit cells, respectively, the light-absorbing layers spaced apart from each other with a second separation line therebetween, forming a third separation line in each of the light-absorbing layers, the third separation line spaced apart from the second separation line, forming a reflection material layer by disposing a silk screen over the third separation line and applying a conductive paste, and forming reflection electrodes corresponding to the unit cells, respectively, by sintering the reflection material layer.
摘要翻译：制造薄膜太阳能电池的方法包括以下步骤：准备在其上限定单元电池的基板，分别在基板上形成透明导电层并对应于单元电池，所述透明导电层分别与第一在其间分别在透明导电层上形成光吸收层并分别对应于单元电池，其间的光吸收层彼此间隔开第二分隔线，在每个光线中形成第三分隔线吸收层，第三分离线与第二分离线间隔开，通过在第三分离线上设置丝网并施加导电浆料形成反射材料层，并分别形成与单元电池对应的反射电极，通过烧结反射材料层。

24. 发明申请

US20100193021A1 THIN FILM SOLAR CELL AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：薄膜太阳能电池及其制造方法
公开(公告)号：US20100193021A1
公开(公告)日：2010-08-05
申请号：US12633255
申请日：2009-12-08
申请人： Won-Seo Park , Jeong-Woo Lee , Seong-Kee Park , Kyung-Jin Shim , Tae-Youn Kim , Yi-Yin Yu
发明人： Won-Seo Park , Jeong-Woo Lee , Seong-Kee Park , Kyung-Jin Shim , Tae-Youn Kim , Yi-Yin Yu
IPC分类号： H01L31/0216 , H01L31/18
CPC分类号： H01L31/022466 , H01L31/056 , H01L31/1884 , Y02E10/50 , Y02E10/52
摘要： A thin film solar cell includes a first substrate, a transparent conductive layer on an inner surface of the first substrate, the transparent conductive layer having an uneven top surface and including through-holes, a light-absorbing layer on the transparent conductive layer, a reflection electrode on the light-absorbing layer, a second substrate facing and attached with the first substrate, and a polymeric material layer on an inner surface of the second substrate.
摘要翻译：薄膜太阳能电池包括第一基板，在第一基板的内表面上的透明导电层，透明导电层具有不平坦的顶表面并且包括通孔，透明导电层上的光吸收层，光吸收层上的反射电极，面对并附着有第一衬底的第二衬底，以及在第二衬底的内表面上的聚合材料层。

25. 发明授权

US07584304B2 Non-volatile memory storage device including an interface select switch and associated method 失效
标题翻译：包括接口选择开关和相关方法的非易失性存储器存储设备
公开(公告)号：US07584304B2
公开(公告)日：2009-09-01
申请号：US11181212
申请日：2005-07-13
申请人： Jeong-Woo Lee , Dong-Ryul Ryu
发明人： Jeong-Woo Lee , Dong-Ryul Ryu
IPC分类号： G06F3/00
CPC分类号： G06F3/0664 , G06F3/0605 , G06F3/0661 , G06F3/0679 , G06F13/385 , G06F13/4027 , G11C7/1006
摘要： We describe and claim an improved non-volatile memory storage device including an interface select switch and associated method. The device comprises a non-volatile memory, and an interface unit including a plurality of storage interfaces, the interface unit to select a storage interface from the plurality of storage interfaces responsive to a selection signal, where the non-volatile memory to exchange data with a host external to the device via the selected storage interface. In an embodiment, the selected storage interface is an ATA storage interface to convert the exchanged data in accordance with an ATA protocol when selected responsive to the selection signal. In another embodiment, the selected storage interface is a SATA storage interface to convert the exchanged data in accordance with a SATA protocol when selected responsive to the selection signal.
摘要翻译：我们描述并要求一种包括接口选择开关和相关方法的改进的非易失性存储器存储设备。所述设备包括非易失性存储器和包括多个存储接口的接口单元，所述接口单元响应于选择信号从所述多个存储接口中选择存储接口，其中所述非易失性存储器与通过所选存储接口在设备外部的主机。在一个实施例中，所选择的存储接口是ATA存储接口，用于在响应于选择信号选择时根据ATA协议转换所交换的数据。在另一个实施例中，所选择的存储接口是SATA存储接口，用于在响应于选择信号选择时根据SATA协议转换所交换的数据。

26. 发明授权

US07567093B2 Semiconductor memory device with on-die termination circuit 有权
标题翻译：具有片上终端电路的半导体存储器件
公开(公告)号：US07567093B2
公开(公告)日：2009-07-28
申请号：US11819800
申请日：2007-06-29
申请人： Kwan-Weon Kim , Jeong-Woo Lee
发明人： Kwan-Weon Kim , Jeong-Woo Lee
IPC分类号： H03K17/16
CPC分类号： H04L25/0278 , H03K19/017545 , H03K19/017581 , H04L25/028
摘要： A semiconductor memory device is able to inactivate an on-die termination circuit without an additional pin. The semiconductor memory device includes a control signal generator, a resistance control unit, and a resistance supply unit. The control signal generator generates an initializing signal and driving clocks in response to a plurality of control signals. The resistance control unit, initialized by the initializing signal, generates a termination-off signal in response to the driving clocks. The resistance supply unit supplies termination resistance in response to the termination-off signal and a mode register setting value. The plurality of control signals are inputted through input pins not connected to the resistance supply unit.
摘要翻译：半导体存储器件能够在没有附加引脚的情况下使管芯端接电路失活。半导体存储器件包括控制信号发生器，电阻控制单元和电阻供应单元。控制信号发生器响应于多个控制信号产生初始化信号和驱动时钟。由初始化信号初始化的电阻控制单元响应于驱动时钟产生终止关闭信号。电阻供应单元响应于终止信号和模式寄存器设置值提供终止电阻。多个控制信号通过未连接到电阻供应单元的输入引脚输入。

27. 发明申请

US20080197891A1 Frequency synthesizer using two phase locked loops 有权
标题翻译：频率合成器使用两个锁相环
公开(公告)号：US20080197891A1
公开(公告)日：2008-08-21
申请号：US11902358
申请日：2007-09-20
申请人： Joonbae Park , Kyeongho Lee , Yido Koo , Jeong-Woo Lee
发明人： Joonbae Park , Kyeongho Lee , Yido Koo , Jeong-Woo Lee
IPC分类号： H03L7/22 , H03B21/01
CPC分类号： H03L7/23 , H03L7/183 , H03L7/1976
摘要： The application discloses system and method embodiments related to a frequency synthesizer. Embodiments of a frequency synthesizer can have a low phase noise and a narrow channel spacing. Embodiments of a frequency synthesizer can use two phase locked loops. One embodiment of a frequency synthesizer can include a reference frequency oscillator for outputting a signal having a reference frequency, an integer-N phase locked loop to generate a first output frequency signal based on the reference frequency signal, a fractional-N phase locked loop to generate a second output frequency based on the reference frequency signal and a circuit to generate an output frequency signal by combining the first output frequency and the second output frequency.
摘要翻译：本申请公开了与频率合成器相关的系统和方法实施例。频率合成器的实施例可以具有低相位噪声和窄通道间隔。频率合成器的实施例可以使用两个锁相环。频率合成器的一个实施例可以包括：参考频率振荡器，用于输出具有参考频率的信号，整数N个锁相环，以基于参考频率信号产生第一输出频率信号;分数N相锁相环基于参考频率信号产生第二输出频率，以及通过组合第一输出频率和第二输出频率来产生输出频率信号的电路。

28. 发明申请

US20070094571A1 ECC circuit of semiconductor memory circuit 审中-公开
标题翻译：半导体存储器电路的ECC电路
公开(公告)号：US20070094571A1
公开(公告)日：2007-04-26
申请号：US11545867
申请日：2006-10-11
申请人： Jeong-Woo Lee
发明人： Jeong-Woo Lee
IPC分类号： G11C29/00
CPC分类号： G06F11/1008 , H03M13/091
摘要： An error detection and correction (EEC) circuit of a semiconductor memory device includes first through m'th ECC engines (m is a natural number) connected in series, and a flipflop that receives output data from the m'th ECC engine, outputs an error detection/correction signal in response to a clock signal, and provides the error detection/correction signal to the first ECC engine. Each ECC engine receives output data from the former ECC engine and n-bit data (n is a natural number) from an ECC data input circuit. The ECC circuit is able to process m*n-bit data by means of the serially connected n-bit ECC engines arranged in number of m.
摘要翻译：半导体存储器件的误差检测和校正（EEC）电路包括串联连接的第一至第M ECC引擎（m为自然数），以及从第m个ECC引擎接收输出数据的触发器输出误差检测/校正信号，并向第一ECC引擎提供错误检测/校正信号。每个ECC引擎从ECC数据输入电路接收来自前一ECC引擎的输出数据和n位数据（n为自然数）。 ECC电路能够通过以m个数量排列的串行连接的n位ECC引擎来处理m * n位数据。

29. 发明申请

US20060185643A1 Premixed charge compression ignition engine and reciprocating generator having the same 失效
标题翻译：预混充气压缩点火发动机和具有相同功能的往复式发电机
公开(公告)号：US20060185643A1
公开(公告)日：2006-08-24
申请号：US10550809
申请日：2004-03-23
申请人： Chan-Jae Lee , Jeong-Woo Lee , Sang-Hyeon Lee
发明人： Chan-Jae Lee , Jeong-Woo Lee , Sang-Hyeon Lee
IPC分类号： F02B17/00 , F02B7/00 , F02B25/08 , F02B75/32
CPC分类号： F02B75/32 , F02B75/282 , F02D15/02 , F02M25/03 , F16C7/04 , Y02T10/12 , Y02T10/121
摘要： The object of the present invention is to provide a premixed charge compression ignition (PCCI) engine. The PCCI engine has a fuel injector (22) in a suction manifold (8) to prepare a premixed charge of fuel and air and induces a natural ignition of the premixed charge in a combustion chamber (20) of a high temperature and high pressure. The PCCI engine further includes a structurally improved connecting rod which has a spring operated in organic conjunction with the other elements of the PCCI engine. The present invention further provides a PCCI reciprocating generator that is fabricated by a combination of a reciprocating generator unit with the PCCI engine, so that the PCCI reciprocating generator operates with improved operational efficiency. In the present invention, two PCCI engines may be arranged to symmetrically face each other, thus providing a multiple PCCI engine.
摘要翻译：本发明的目的是提供一种预混合的充气压缩点火（PCCI）发动机。 PCCI发动机在吸入歧管（8）中具有燃料喷射器（22），以制备燃料和空气的预混合装料，并引起预混合装料在高温高压燃烧室（20）中的自然点燃。 PCCI发动机还包括结构改进的连杆，其具有与PCCI发动机的其它元件有机连接的弹簧。本发明还提供了一种通过往复式发电机单元与PCCI发动机的组合制造的PCCI往复式发电机，使得PCCI往复式发电机以更好的运行效率运行。在本发明中，两个PCCI引擎可以被布置成对称地彼此面对，从而提供多个PCCI引擎。

30. 发明授权

US07071535B2 Integrated circuit package having inductance loop formed from a bridge interconnect 有权
标题翻译：集成电路封装，其具有由桥互连形成的电感环路
公开(公告)号：US07071535B2
公开(公告)日：2006-07-04
申请号：US10927152
申请日：2004-08-27
申请人： Yido Koo , Hyungki Huh , Kang Yoon Lee , Jeong-Woo Lee , Joonban Park , Kyeongho Lee
发明人： Yido Koo , Hyungki Huh , Kang Yoon Lee , Jeong-Woo Lee , Joonban Park , Kyeongho Lee
IPC分类号： H01L29/00 , H03B7/14
CPC分类号： H01L23/642 , H01L23/645 , H01L24/48 , H01L24/49 , H01L2223/6611 , H01L2224/48091 , H01L2224/48247 , H01L2224/49113 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15192 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H03B5/1215 , H03B5/1228 , H03B5/1265 , H01L2224/45099 , H01L2224/05599
摘要： An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a second wire which connects a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a conductive bridge between the pins. The bridge may be formed by making the I/O pins have a unitary construction. In another embodiment, the bridge is formed by a metallization layer located either on the surface of the package substrate or within this substrate. The I/O pins are preferably ones which are adjacent one another; however, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization. Also, the integrated circuit may be implemented in any one of a variety of systems, at least one parameter of which is controlled by the length of the inductor loop of the package.
摘要翻译：集成电路封装包括由引线和一个或多个输入/输出（I / O）封装引脚的连接形成的电感回路。在一个实施例中，电感回路由将集成电路芯片上的第一接合焊盘连接到封装的第一I / O引脚的第一引线和将芯片上的第二接合焊盘连接到第二引线的第二引线形成封装的I / O引脚。为了完成电感环路，第一和第二I / O引脚通过引脚之间的导电桥连接。可以通过使I / O引脚具有单一结构来形成桥。在另一个实施例中，桥由位于封装衬底的表面上或在该衬底内的金属化层形成。 I / O引脚优选为彼此相邻的引脚; 然而，环路可以基于例如环路长度要求，空间考虑和/或其他设计或功能因素的I / O引脚的不相邻连接形成。通过在集成电路封装的极限内形成电感器回路，实现了空间要求的显着降低，这反过来促进了小型化。此外，集成电路可以在各种系统中的任何一个中实现，其中的至少一个参数由封装的电感器环的长度来控制。

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