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21. 发明申请

US20080028137A1 Method and Apparatus For Refresh Management of Memory Modules 审中-公开
标题翻译：用于内存模块刷新管理的方法和装置
公开(公告)号：US20080028137A1
公开(公告)日：2008-01-31
申请号：US11828182
申请日：2007-07-25
申请人： Keith R. Schakel , Suresh Natarajan Rajan , Michael John Sebastian Smith , David T. Wang
发明人： Keith R. Schakel , Suresh Natarajan Rajan , Michael John Sebastian Smith , David T. Wang
IPC分类号： G06F13/28
CPC分类号： G11C11/406 , G11C7/04 , G11C11/40611 , G11C11/40618
摘要： One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller, and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices
摘要翻译：一个实施例提出了一种接口电路，其被配置为管理刷新命令序列，其包括适于从存储器控制器接收刷新命令的系统接口，时钟频率检测电路被配置为确定向两个或多个存储器件耦合的交错刷新命令的发送定时基于从存储器控制器接收的刷新命令到接口电路，以及被配置为生成用于两个或更多个存储器设备的交错刷新命令的至少两个刷新命令序列输出

22. 发明申请

US20080027702A1 SYSTEM AND METHOD FOR SIMULATING A DIFFERENT NUMBER OF MEMORY CIRCUITS 有权
标题翻译：用于模拟不同数量的存储器电路的系统和方法
公开(公告)号：US20080027702A1
公开(公告)日：2008-01-31
申请号：US11461420
申请日：2006-07-31
申请人： Suresh Natarajan Rajan , Keith R. Schakel , Michael John Sebastian Smith , David T. Wang , Frederick Daniel Weber
发明人： Suresh Natarajan Rajan , Keith R. Schakel , Michael John Sebastian Smith , David T. Wang , Frederick Daniel Weber
IPC分类号： G06F13/10
CPC分类号： G11C11/406 , G11C7/10 , G11C11/40618
摘要： A system and method are provided for simulating a different number of memory circuits. Included is an interface circuit in communication with a first number of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit of a second number. Further, the interface circuit interfaces a majority of address or control signals of the memory circuits.
摘要翻译：提供了一种用于模拟不同数量的存储器电路的系统和方法。包括与第一数量的存储器电路和系统通信的接口电路。这种接口电路可操作以将存储器电路和系统接口以模拟第二数量的至少一个存储器电路。此外，接口电路接口存储器电路的大多数地址或控制信号。

23. 发明申请

US20080027697A1 MEMORY CIRCUIT SIMULATION SYSTEM AND METHOD WITH POWER SAVING CAPABILITIES 有权
标题翻译：存储电路仿真系统及省电功能的方法
公开(公告)号：US20080027697A1
公开(公告)日：2008-01-31
申请号：US11553372
申请日：2006-10-26
申请人： Suresh Natarajan Rajan , Keith R. Schakel , Michael John Sebastian Smith , David T. Wang , Frederick Daniel Weber
发明人： Suresh Natarajan Rajan , Keith R. Schakel , Michael John Sebastian Smith , David T. Wang , Frederick Daniel Weber
IPC分类号： G06F17/50
CPC分类号： G11C11/406 , G11C7/10 , G11C11/40618
摘要： A system and method are provided including a component in communication with a plurality of memory circuits and a system. The component is operable to interface the memory circuits an the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. The component is further operable to perform a power saving operation.
摘要翻译：提供了一种包括与多个存储器电路和系统通信的部件的系统和方法。该组件可操作以使存储器电路和系统接口，用于模拟至少一个与至少一个存储器电路的至少一个方面不同的方面的存储器电路。该部件进一步可操作以执行省电操作。

24. 发明申请

US20080025122A1 MEMORY REFRESH SYSTEM AND METHOD 失效
标题翻译：存储器刷新系统和方法
公开(公告)号：US20080025122A1
公开(公告)日：2008-01-31
申请号：US11461437
申请日：2006-07-31
申请人： Keith R. Schakel , Suresh Natarajan Rajan , Michael John Sebastian Smith , David T. Wang , Frederick Daniel Weber
发明人： Keith R. Schakel , Suresh Natarajan Rajan , Michael John Sebastian Smith , David T. Wang , Frederick Daniel Weber
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40618 , G11C11/4093
摘要： A system and method are provided. In response to the receipt of a refresh control signal, a plurality of refresh control signals is sent to the memory circuits at different times.
摘要翻译：提供了一种系统和方法。响应于接收到刷新控制信号，在不同的时间将多个刷新控制信号发送到存储器电路。

25. 发明申请

US20080025108A1 SYSTEM AND METHOD FOR DELAYING A SIGNAL COMMUNICATED FROM A SYSTEM TO AT LEAST ONE OF A PLURALITY OF MEMORY CIRCUITS 有权
标题翻译：用于将从系统传播到信号的信号延迟至多个存储器电路的系统和方法
公开(公告)号：US20080025108A1
公开(公告)日：2008-01-31
申请号：US11461430
申请日：2006-07-31
申请人： Suresh Natarajan Rajan , Keith R. Schakel , Michael John Sebastian Smith , David T. Wang , Frederick Daniel Weber
发明人： Suresh Natarajan Rajan , Keith R. Schakel , Michael John Sebastian Smith , David T. Wang , Frederick Daniel Weber
IPC分类号： G11C7/10 , G11C7/00 , G11C8/00
CPC分类号： G11C8/18 , G11C5/04 , G11C7/1066 , G11C8/12 , G11C11/406 , G11C11/40618 , G11C29/50012
摘要： A system and method are provided for delaying a signal communicated from a system to a plurality of memory circuits. Included is a component in communication with a plurality of memory circuits and a system. Such component is operable to receive a signal from the system and communicate the signal to at least one of the memory circuits after a delay. In other embodiments, the component is operable to receive a signal from at least one of the memory circuits and communicate the signal to the system after a delay.
摘要翻译：提供了一种用于将从系统传送的信号延迟到多个存储器电路的系统和方法。包括与多个存储器电路和系统通信的部件。这样的组件可操作以从系统接收信号并且在延迟之后将该信号传送到至少一个存储器电路。在其他实施例中，组件可操作以从至少一个存储器电路接收信号，并在延迟之后将该信号传送到系统。

26. 发明授权

US09047976B2 Combined signal delay and power saving for use with a plurality of memory circuits 有权
标题翻译：用于多个存储器电路的组合的信号延迟和功率节省
公开(公告)号：US09047976B2
公开(公告)日：2015-06-02
申请号：US11553390
申请日：2006-10-26
申请人： Suresh Natarajan Rajan , Keith R. Schakel , Michael John Sebastian Smith , David T. Wang , Frederick Daniel Weber
发明人： Suresh Natarajan Rajan , Keith R. Schakel , Michael John Sebastian Smith , David T. Wang , Frederick Daniel Weber
IPC分类号： G06F1/32 , G11C11/406 , G11C7/10
CPC分类号： G11C11/406 , G11C7/10 , G11C11/40618
摘要： A system and method are provided. In use, at least one of a plurality of memory circuits is identified. In association with the at least one memory circuit, a power saving operation is performed and the communication of a signal thereto is delayed.
摘要翻译：提供了一种系统和方法。在使用中，识别出多个存储电路中的至少一个。与至少一个存储器电路相关联，执行省电操作并且延迟其信号的通信。

27. 发明授权

US08762675B2 Memory system for synchronous data transmission 有权
标题翻译：用于同步数据传输的内存系统
公开(公告)号：US08762675B2
公开(公告)日：2014-06-24
申请号：US13620199
申请日：2012-09-14
申请人： David T. Wang , Suresh Natarajan Rajan
发明人： David T. Wang , Suresh Natarajan Rajan
IPC分类号： G06F13/28 , G06F13/16 , G11C7/22
CPC分类号： G06F13/1689 , G06F1/12 , G11C7/22
摘要： One embodiment of the present invention sets forth an interface circuit configured to combine time staggered data bursts returned by multiple memory devices into a larger contiguous data burst. As a result, an accurate timing reference for data transmission that retains the use of data (DQ) and data strobe (DQS) signals in an infrastructure-compatible system while eliminating the cost of the idle cycles required for data bus turnarounds to switch from reading from one memory device to reading from another memory device, or from writing to one memory device to writing to another memory device may be obtained, thereby increasing memory system bandwidth relative to the prior art approaches.
摘要翻译：本发明的一个实施例提出了一种接口电路，其被配置为将由多个存储器件返回的时间交错数据突发组合成更大的连续数据脉冲串。因此，数据传输的准确定时参考保留了在基础架构兼容系统中使用数据（DQ）和数据选通（DQS）信号，同时消除了数据总线周转从读取中切换所需的空闲周期的成本从一个存储器件到另一个存储器件的读取，或从写入到一个存储器件到另一个存储器件的写入可以获得，从而相对于现有技术的方法增加了存储器系统带宽。

28. 发明授权

US08745321B2 Simulating a memory standard 有权
标题翻译：模拟内存标准
公开(公告)号：US08745321B2
公开(公告)日：2014-06-03
申请号：US13620291
申请日：2012-09-14
申请人： Suresh Natarajan Rajan , Keith R. Schakel , Michael John Sebastian Smith , David T. Wang , Frederick Daniel Weber
发明人： Suresh Natarajan Rajan , Keith R. Schakel , Michael John Sebastian Smith , David T. Wang , Frederick Daniel Weber
IPC分类号： G06F12/00
CPC分类号： G11C7/1072 , G06F13/4243 , G11C7/10 , G11C11/406 , G11C11/40618 , Y02D10/14 , Y02D10/151
摘要： An apparatus includes multiple first memory circuits, each first memory circuit being associated with a first memory standard, where the first memory standard defines a first set of control signals that each first memory circuit circuits is operable to accept. The apparatus also includes an interface circuit coupled to the first memory circuits, in which the interface circuit is operable to emulate at least one second memory circuit, each second memory circuit being associated with a second different memory standard.
摘要翻译：一种装置包括多个第一存储器电路，每个第一存储器电路与第一存储器标准相关联，其中第一存储器标准定义了每个第一存储器电路电路可操作地接受的第一组控制信号。该装置还包括耦合到第一存储器电路的接口电路，其中接口电路可操作以模拟至少一个第二存储器电路，每个第二存储器电路与第二不同存储器标准相关联。

29. 发明申请

US20130188424A1 SYSTEM AND METHOD FOR STORING AT LEAST A PORTION OF INFORMATION RECEIVED IN ASSOCIATION WITH A FIRST OPERATION FOR USE IN PERFORMING A SECOND OPERATION 审中-公开
标题翻译：至少存储在与执行第二次操作中使用的第一次操作相关联的信息的部分的系统和方法
公开(公告)号：US20130188424A1
公开(公告)日：2013-07-25
申请号：US13620233
申请日：2012-09-14
申请人： Suresh Natarajan Rajan , Keith R. Schakel , Michael John Sebastian Smith , David T. Wang , Frederick Daniel Weber
发明人： Suresh Natarajan Rajan , Keith R. Schakel , Michael John Sebastian Smith , David T. Wang , Frederick Daniel Weber
IPC分类号： G11C16/06
CPC分类号： G11C16/06 , G11C7/1039 , G11C7/1078 , G11C7/1087 , G11C7/109 , G11C8/06 , G11C8/12 , G11C11/4093
摘要： A method includes: receiving first information in association with a first operation to be performed on at least one of multiple flash memory circuits; storing at least a portion of the first information; receiving second information in association with a second operation to be performed on at least one of the multiple flash memory circuits, in which the second operation is a read operation or a write operation; receiving data from the flash memory circuits based on at least the first information and storing the data in a buffer; and performing the second operation utilizing the stored portion of the first information in addition to the second information on the data in the buffer.
摘要翻译：一种方法包括：与在多个快闪存储器电路中的至少一个执行的第一操作相关联地接收第一信息; 存储所述第一信息的至少一部分; 与第二操作相关联地接收第二信息，该第二操作将在多个快闪存储器电路中的至少一个执行，其中第二操作是读取操作或写入操作; 至少基于第一信息从快闪存储器电路接收数据并将数据存储在缓冲器中; 以及除了关于缓冲器中的数据的第二信息之外，利用第一信息的存储部分执行第二操作。

30. 发明授权

US08438328B2 Emulation of abstracted DIMMs using abstracted DRAMs 有权
公开(公告)号：US08438328B2
公开(公告)日：2013-05-07
申请号：US12378328
申请日：2009-02-14
申请人： Michael J. S. Smith , Suresh Natarajan Rajan , David T. Wang
发明人： Michael J. S. Smith , Suresh Natarajan Rajan , David T. Wang
IPC分类号： G06F12/00
CPC分类号： G06F13/4239 , Y02D10/14 , Y02D10/151
摘要： One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory-related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, a number of pipeline stages, a number of banks, a mapping to physical banks, a number of ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, a number of planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device. One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices.

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