专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07348657B2 Electrostatic discharge protection networks for triple well semiconductor devices 有权
标题翻译：三阱半导体器件的静电放电保护网络
公开(公告)号：US07348657B2
公开(公告)日：2008-03-25
申请号：US11425491
申请日：2006-06-21
申请人： James P. Pequignot , Jeffrey H. Sloan , Douglas W. Stout , Steven H. Voldman
发明人： James P. Pequignot , Jeffrey H. Sloan , Douglas W. Stout , Steven H. Voldman
IPC分类号： H01L29/06
CPC分类号： H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection network that uses triple well semiconductor devices either singularly or in a series configuration. The semiconductor devices are preferably in diode junction type configuration.
摘要翻译：一种使用三重阱半导体器件的静电放电保护网络，其单体或串联配置。半导体器件优选为二极管结型。

22. 发明授权

US07348251B2 Modulated trigger device 失效
标题翻译：调制触发器
公开(公告)号：US07348251B2
公开(公告)日：2008-03-25
申请号：US11201023
申请日：2005-08-10
申请人： Steven H. Voldman , Michael J. Zierak
发明人： Steven H. Voldman , Michael J. Zierak
IPC分类号： H01L29/66
CPC分类号： H01L27/0277 , H01L29/1087 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure, a trigger device and a method of electrostatic discharge protection, the integrated circuit structure including: a substrate having a top surface defining a horizontal direction, the substrate of a first dopant type; a first horizontal layer in the substrate, the first layer of a second dopant type; and a second horizontal layer of the first dopant type, the second layer on top of the first layer and between the top surface of the substrate and the first layer, the second layer electrically modulated by the first layer.
摘要翻译：集成电路结构，触发装置和静电放电保护方法，所述集成电路结构包括：具有限定水平方向的顶表面的衬底，所述第一掺杂剂类型的衬底; 衬底中的第一水平层，第二掺杂剂型的第一层; 以及第一掺杂剂类型的第二水平层，第二层在第一层的顶部和衬底的顶表面与第一层之间，第二层由第一层电调制。

23. 发明申请

US20080002316A1 POWER CLAMP DEVICES WITH VERTICAL NPN DEVICES 审中-公开
标题翻译：具有垂直NPN器件的电源钳位器件
公开(公告)号：US20080002316A1
公开(公告)日：2008-01-03
申请号：US11427063
申请日：2006-06-28
申请人： James W. Adkisson , John J. Ellis-Monaghan , Steven H. Voldman
发明人： James W. Adkisson , John J. Ellis-Monaghan , Steven H. Voldman
IPC分类号： H02H9/00
CPC分类号： H01L27/0285
摘要： ESD power clamp devices with vertical NPN devices are disclosed. The power clamp is formed on an N type substrate and includes an N channel field effect transistor (NFET). The source and drain regions of the NFET, a P type epitaxial region under the NFET, and the N type substrate constitutes two vertical NPN devices. As such, vertical interactions of electrons are enabled to avoid the disadvantages of traditional power clamps, e.g., minority carrier cross-talk.
摘要翻译：公开了具有垂直NPN器件的ESD功率钳位器件。电源钳位形成在N型衬底上并且包括N沟道场效应晶体管（NFET）。 NFET的源极和漏极区域，NFET下的P型外延区域和N型衬底构成两个垂直NPN器件。因此，电子的垂直相互作用能够避免传统功率钳位的缺点，例如少数载流子串扰。

24. 发明申请

US20070287243A1 Semiconductor devices 失效
标题翻译：半导体器件
公开(公告)号：US20070287243A1
公开(公告)日：2007-12-13
申请号：US11422690
申请日：2006-06-07
申请人： Xuefeng Liu , Robert M. Rassel , Steven H. Voldman
发明人： Xuefeng Liu , Robert M. Rassel , Steven H. Voldman
IPC分类号： H01L21/8238
CPC分类号： H01L29/7436 , H01L27/0262 , H01L29/7378
摘要： A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The device further comprises a reach-through structure connecting the first and second sub-collectors and an N-well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure. The device further comprises N+ diffusion regions in contact with the N-well, a P+ diffusion region in contact with the N-well, and shallow trench isolation structures between the N+ and P+ diffusion regions.
摘要翻译：一种器件包括形成在衬底的上部中的第一子集电极和形成在第一外延层的上部中的第一外延层和第二子集电极的下部，以及第二外延层的下部。该装置还包括连接第一和第二子集电器的连通结构和形成在第二外延层的一部分中并与第二子集电器和达到通孔结构接触的N阱。该装置还包括与N阱接触的N +扩散区，与N阱接触的P +扩散区，以及N +和P +扩散区之间的浅沟槽隔离结构。

25. 发明授权

US07102867B2 Method, apparatus and circuit for latchup suppression in a gate-array ASIC environment 失效
标题翻译：在门阵列ASIC环境中用于闭锁抑制的方法，装置和电路
公开(公告)号：US07102867B2
公开(公告)日：2006-09-05
申请号：US10604176
申请日：2003-06-30
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： H02H9/02 , H02H3/08
CPC分类号： H01L27/0921 , H01L27/11807
摘要： An integrated circuit having a substrate (10), a power rail (18, 20), a sea of gates (12), and a latchup control isolation network electrically coupled to substrate (10). The latchup control isolation network electrically isolates sea of gates (12) from power rail (18, 20). In another embodiment, an active clamp network may be utilized to electrically isolate sea of gates (12) from power rail (18, 20). Substrate (10) includes a voltage potential. When the voltage potential is equal to or greater than a first predetermined value or the voltage potential is equal to or less than a second predetermined value, either the latchup control isolation network turns off or the active clamp network turns on thereby isolating sea of gates (12) from power rail (18, 20).
摘要翻译：具有基板（10），电力轨道（18,20），大海（12）以及电耦合到基板（10）的闭锁控制隔离网络的集成电路。闭锁控制隔离网络将闸门（12）与电力轨道（18,20）电隔离。在另一个实施例中，可以利用有源钳位网络将闸门（12）的海电与电力轨道（18,20）电隔离。基板（10）包括电压电位。当电压电位等于或大于第一预定值或电压电位等于或小于第二预定值时，闭锁控制隔离网络关闭或有源钳位网络导通，从而隔离大门（ 12）从电力轨道（18,20）。

26. 发明授权

US06731488B2 Dual emitter transistor with ESD protection 有权
标题翻译：具有ESD保护的双发射极晶体管
公开(公告)号：US06731488B2
公开(公告)日：2004-05-04
申请号：US10063225
申请日：2002-04-01
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： H02H322
CPC分类号： H01L27/0259 , H03K17/04113 , H03K17/08146
摘要： The invention provides a method and circuit design for providing ESD protection. Specifically, a dual emitter transistor is used to provide bipolar operation and ESD protection. The first emitter provides bipolar operation under normal operating conditions. The second emitter provides an alternative current path for ESD protection.
摘要翻译：本发明提供了一种用于提供ESD保护的方法和电路设计。具体来说，双发射极晶体管用于提供双极性操作和ESD保护。第一个发射器在正常工作条件下提供双极性操作。第二个发射器为ESD保护提供了一个替代电流路径。

27. 发明授权

US06704179B2 Automated hierarchical parameterized ESD network design and checking system 失效
标题翻译：自动分层参数化ESD网络设计和检查系统
公开(公告)号：US06704179B2
公开(公告)日：2004-03-09
申请号：US09683970
申请日：2002-03-07
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： H02H900
CPC分类号： G06F17/5045
摘要： A computerized method for designing electrostatic discharge (ESD) protection circuits uses a hierarchical system of parametrized cells (p-cells) which are constructed into higher level ESD networks. Lowest order p-cells pass user defined parameters to higher order p-cells to form an ESD protection circuit meeting the design criteria. Ones of the p-cells are “growable” such that they can form repetition groups of the underlying p-cell element to accommodate the design parameters. This allows for change of circuit topology as well as structure size in an automated fashion. Layout and circuit schematics are auto-generated with the user varying the number of elements in the circuit by adjusting the input parameters. The circuit topology automation allows for the customer to autogenerate new ESD circuits and ESD power clamps without additional design work. Interconnects and wiring between the circuit elements are also autogenerated.
摘要翻译：用于设计静电放电（ESD）保护电路的计算机化方法使用构建到更高级ESD网络中的参数化单元（p-cell）的分层系统。最低阶p单元将用户定义的参数传递到高阶p单元，以形成满足设计标准的ESD保护电路。 p细胞的一部分是“可生长的”，使得它们可以形成下面的p细胞元件的重复组以适应设计参数。这允许以自动化的方式改变电路拓扑结构以及结构尺寸。布局和电路原理图是通过用户通过调整输入参数来改变电路中的元件数量而自动生成的。电路拓扑自动化允许客户自动生成新的ESD电路和ESD电源钳位，无需额外的设计工作。电路元件之间的互连和接线也是自动生成的。

28. 发明授权

US06512296B1 Semiconductor structure having heterogenous silicide regions having titanium and molybdenum 失效
标题翻译：具有异质硅化物区域的具有钛和钼的半导体结构
公开(公告)号：US06512296B1
公开(公告)日：2003-01-28
申请号：US09636325
申请日：2000-08-10
申请人： Robert J. Gauthier, Jr. , Randy W. Mann , Steven H. Voldman
发明人： Robert J. Gauthier, Jr. , Randy W. Mann , Steven H. Voldman
IPC分类号： H01L2348
CPC分类号： H01L29/4933 , H01L21/28052 , H01L21/28518 , H01L21/28568 , H01L21/823418 , H01L21/823443 , H01L29/456
摘要： A process for forming heterogeneous silicide structures on a semiconductor substrate (10) includes implanting molybdenum ions into selective areas of the semiconductor substrate (10) to form molybdenum regions (73, 74, 75, 76). Titanium is then deposited over the semiconductor substrate (10). The semiconductor substrate (10) is annealed at a temperature between approximately 600° C. and approximately 700° C. During the annealing process, the titanium deposited in areas outside the molybdenum regions (73, 74, 75, 76) interacts with silicon on the substrate to form titanium silicide in a high resistivity C49 crystal phase. The titanium deposited in areas within the molybdenum regions (73, 74, 75, 76) interacts with silicon to form titanium silicide in a low resistivity C54 crystal phase because the presence of molybdenum ions in silicon lowers the energy barrier for crystal phase transformation between the C49 phase and the C54 phase.
摘要翻译：在半导体衬底（10）上形成异质硅化物结构的方法包括将钼离子注入到半导体衬底（10）的选择区域中以形成钼区（73,74,75,76）。然后将钛沉积在半导体衬底（10）上。半导体衬底（10）在大约600℃和大约700℃之间的温度下退火。在退火过程中，沉积在钼区域（73,74,75,76）之外的区域中的钛与硅该基板在高电阻率C49晶相中形成硅化钛。在钼区域（73,74,75,76）中的区域中沉积的钛与硅相互作用以在低电阻率C54晶体相中形成硅化钛，因为硅中的钼离子的存在降低了能量势垒以进行晶体相变 C49相和C54相。

29. 发明授权

US06433609B1 Double-gate low power SOI active clamp network for single power supply and multiple power supply applications 有权
标题翻译：双门低功耗SOI有源钳位网络，用于单电源和多电源应用
公开(公告)号：US06433609B1
公开(公告)日：2002-08-13
申请号：US09683105
申请日：2001-11-19
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： H03K508
CPC分类号： H03K5/08 , H01L27/0266 , H01L29/785
摘要： A double-gated low power active clamp circuit for digital circuits includes a first double-gated MOSFET serially connected between an upper power supply voltage and an input terminal to be clamped, and a second double-gated MOSFET serially connected between a lower voltage power supply and the input terminal. The voltages at the gates of the first and second double-gated MOSFETs are held at constant reference voltages by a single or double reference circuits. The clamping action can be switched on or off. The double-gated active clamping network can be implemented with a single power supply voltage, or with multiple power supply voltages. The use of the back gates of the double-gated active clamping network enables additional clamping and ESD protection for smaller generations of transistors, such as, those having dimensions below 0.1 micron. The device is particularly suited for use with dynamic threshold double-gated silicon-on-insulator, FINFET, and bulk triple well technologies.
摘要翻译：用于数字电路的双门控低功率有源钳位电路包括串联连接在上电源电压和要钳位的输入端之间的第一双门控MOSFET，以及串联连接在较低电压电源和输入端子。第一和第二双栅控MOSFET的栅极处的电压通过单个或双参考电路保持在恒定的参考电压。可以打开或关闭夹紧动作。双门控有源钳位网络可以使用单个电源电压或多个电源电压来实现。使用双门控有源钳位网络的后门可以为较小代的晶体管（例如尺寸小于0.1微米的晶体管）提供额外的钳位和ESD保护。该器件特别适用于动态阈值双门绝缘体硅，FINFET和批量三阱技术。

30. 发明授权

US06404269B1 Low power SOI ESD buffer driver networks having dynamic threshold MOSFETS 有权
标题翻译：具有动态阈值MOSFET的低功耗SOI ESD缓冲器驱动器网络
公开(公告)号：US06404269B1
公开(公告)日：2002-06-11
申请号：US09398594
申请日：1999-09-17
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： H03K301
CPC分类号： H01L27/0255 , H01L27/0266
摘要： A method and structure for a body coupled driver circuit includes a pull-up stage having a first transistor and a pull-down stage having a second transistor. The first transistor and the second transistor have bodies coupled to either a reference voltage or a pad node.
摘要翻译：用于体耦合驱动器电路的方法和结构包括具有第一晶体管的上拉级和具有第二晶体管的下拉级。第一晶体管和第二晶体管具有耦合到参考电压或焊盘节点的主体。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式