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21. 发明申请

US20070099372A1 Device having active regions of different depths 审中-公开
标题翻译：装置具有不同深度的活动区域
公开(公告)号：US20070099372A1
公开(公告)日：2007-05-03
申请号：US11590246
申请日：2006-10-31
申请人： Sailesh Chittipeddi , Seungmoo Choi
发明人： Sailesh Chittipeddi , Seungmoo Choi
IPC分类号： H01L21/8238 , H01L21/8242 , H01L29/788
CPC分类号： H01L21/84 , H01L21/76243 , H01L21/76267 , H01L27/1203
摘要： An SOI device having SOI layers at two or more different depths below the surface of active regions of the device. Transistors for high-speed digital applications may be formed in the shallower active regions and RF power or high-voltage transistors may be formed in the deeper active regions. In one embodiment, the shallower active regions are fully-depleted while the deeper active regions are partially-depleted.
摘要翻译：具有在器件的有源区域的表面下方的两个或更多个不同深度处的SOI层的SOI器件。用于高速数字应用的晶体管可以形成在较浅的有源区中，并且可以在较深的有源区中形成RF功率或高压晶体管。在一个实施例中，较浅的有源区域被完全耗尽，而较深的有源区域被部分耗尽。

22. 发明授权

US06890827B1 Method of fabricating a silicon on insulator transistor structure for imbedded DRAM 有权
标题翻译：制造用于嵌入式DRAM的绝缘体上硅晶体管结构的方法
公开(公告)号：US06890827B1
公开(公告)日：2005-05-10
申请号：US09384503
申请日：1999-08-27
申请人： Seungmoo Choi , Sailesh Merchant , Pradip K. Roy
发明人： Seungmoo Choi , Sailesh Merchant , Pradip K. Roy
IPC分类号： H01L21/8242 , H01L29/786 , H01L21/331
CPC分类号： H01L29/78696 , H01L27/10873 , H01L29/78621 , Y10S438/979
摘要： To address the above-discussed deficiencies of the prior art, the present invention provides an integrated circuit formed on a semiconductor wafer, comprising a doped base substrate; an insulator layer formed over the doped base substrate; and a doped ultra thin active layer formed on the insulator layer, the ultra thin active layer including a gate oxide, a gate formed on the gate oxide, and source and drain regions formed in the ultra thin active layer and adjacent the gate. The present invention therefore provides a semiconductor wafer that provides a doped ultra thin active layer. The lower Ioff in the DRAM transistor allows for lower heat dissipation, and the overall power requirement is decreased. Thus, the present invention provides a lower Ioff with reasonably good ion characteristics.
摘要翻译：为了解决现有技术的上述缺陷，本发明提供一种形成在半导体晶片上的集成电路，包括掺杂的基底; 在所述掺杂的基底衬底上形成的绝缘体层; 以及形成在所述绝缘体层上的掺杂的超薄有源层，所述超薄有源层包括栅极氧化物，形成在所述栅极氧化物上的栅极以及形成在所述超薄有源层中并且邻近所述栅极的源极和漏极区域。因此，本发明提供一种提供掺杂的超薄有源层的半导体晶片。 DRAM晶体管中的较低Ioff允许较低的散热，并且整体功率需求降低。因此，本发明提供具有相当好的离子特性的较低的Ioff。

23. 发明授权

US06340827B1 Diffusion barrier for use with high dielectric constant materials and electronic devices incorporating same 有权
标题翻译：用于高介电常数材料的扩散阻挡层和结合其的电子器件
公开(公告)号：US06340827B1
公开(公告)日：2002-01-22
申请号：US09478647
申请日：2000-01-06
申请人： Seungmoo Choi , Sailesh M. Merchant , Pradip K. Roy
发明人： Seungmoo Choi , Sailesh M. Merchant , Pradip K. Roy
IPC分类号： H01L3300
CPC分类号： H01L28/40 , H01L21/28568
摘要： A diffusion barrier for preventing the diffusion of oxygen from a high dielectric constant material to a titanium nitride layer. The diffusion barrier comprises one or more layers, wherein each of the one or more layers comprises a material selected from the group consisting of metal carbide, metal nitride, metal boride, metal carbo-nitride, and silicon carbide. The high dielectric constant material may be tantalum pentoxide or any perkovskite-type high dielectric constant material.
摘要翻译：用于防止氧从高介电常数材料扩散到氮化钛层的扩散屏障。扩散阻挡层包括一层或多层，其中一层或多层中的每层包括选自金属碳化物，金属氮化物，金属硼化物，金属碳氮化物和碳化硅的材料。高介电常数材料可以是五氧化二钽或任何一种钙钛矿型高介电常数材料。

24. 发明授权

US06168991A DRAM capacitor including Cu plug and Ta barrier and method of forming 有权
标题翻译：包括Cu插头和Ta阻挡层的DRAM电容器及其形成方法
公开(公告)号：US06168991A
公开(公告)日：2001-01-02
申请号：US09340062
申请日：1999-06-25
申请人： Seungmoo Choi , Sailesh M. Merchant , Pradip K. Roy
发明人： Seungmoo Choi , Sailesh M. Merchant , Pradip K. Roy
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/28568 , H01L21/76895 , H01L27/10852 , H01L27/10888 , H01L28/55 , H01L28/75
摘要： A capacitor for a DRAM cell comprises a first electrode layer, a second electrode layer, and a dielectric film. The capacitor is disposed in a first opening defined in a second dielectric layer and overlaying a first plug through a first dielectric layer. The first plug is electrically connected to a transistor. The first electrode layer is electrically connected to the first plug. The second electrode layer can act as a barrier between a second plug exposed by a second opening and the second opening. The first and second electrode layer can be formed from Ta and TaN, and the dielectric film can be formed from tantalum oxide. A plug layer electrically connected to the second electrode layer can also be included. The plug layer can be formed from copper. A method of forming the DRAM capacitor is also disclosed.
摘要翻译：用于DRAM单元的电容器包括第一电极层，第二电极层和电介质膜。电容器设置在限定在第二电介质层中的第一开口中，并且通过第一介电层覆盖第一插塞。第一插头电连接到晶体管。第一电极层电连接到第一插头。第二电极层可以用作由第二开口暴露的第二插头和第二开口之间的屏障。第一和第二电极层可以由Ta和TaN形成，并且电介质膜可以由氧化钽形成。电连接到第二电极层的插塞层也可以包括在内。插塞层可以由铜形成。还公开了形成DRAM电容器的方法。

25. 发明授权

US06072210A Integrate DRAM cell having a DRAM capacitor and a transistor 有权
标题翻译：集成具有DRAM电容器和晶体管的DRAM单元
公开(公告)号：US06072210A
公开(公告)日：2000-06-06
申请号：US220418
申请日：1998-12-24
申请人： Seungmoo Choi
发明人： Seungmoo Choi
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10852 , H01L28/91
摘要： An integrated DRAM cell comprises a DRAM capacitor and a transistor. The capacitor of the cell is formed in a first well in a dielectric layer overlying the cell transistor. The top electrode of the capacitor also serves as a barrier layer between an underlying plug in a second well in the dielectric layer. A method of forming the cell comprises the step of using a single mask for formation of the layer which acts as both the top electrode of the capacitor and the barrier layer of the second well.
摘要翻译：集成DRAM单元包括DRAM电容器和晶体管。电池的电容器形成在覆盖电池晶体管的电介质层中的第一阱中。电容器的顶部电极还用作介电层中第二阱中的下面的插塞之间的阻挡层。形成电池的方法包括使用单个掩模形成用作电容器的顶部电极和第二阱的阻挡层两者的层的步骤。

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