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21. 发明授权

US06208180B1 Core clock correction in a 2/N mode clocking scheme 有权
标题翻译：核心时钟校正在2 / N模式计时方案
公开(公告)号：US06208180B1
公开(公告)日：2001-03-27
申请号：US09170997
申请日：1998-10-13
申请人： Matthew A. Fisch , Chakrapani Pathikonda , Javed S. Barkatullah
发明人： Matthew A. Fisch , Chakrapani Pathikonda , Javed S. Barkatullah
IPC分类号： H03L700
CPC分类号： G06F1/12
摘要： A 2/N mode dock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
摘要翻译：通过使用总线时钟使能信号来选择与核心时钟信号同相和异相的总线时钟脉冲来产生总线时钟信号的2 / N模式发射器。时钟发生器保持总线时钟信号和核心时钟信号之间的同步，使得它们总是处于预定的相位关系。

22. 发明授权

US6006299A Apparatus and method for caching lock conditions in a multi-processor system 失效
标题翻译：用于在多处理器系统中缓存锁定条件的装置和方法
公开(公告)号：US6006299A
公开(公告)日：1999-12-21
申请号：US204592
申请日：1994-03-01
申请人： Wen-Hann Wang , Konrad K. Lai , Gurbir Singh , Mandar S. Joshi , Nitin V. Sarangdhar , Matthew A. Fisch
发明人： Wen-Hann Wang , Konrad K. Lai , Gurbir Singh , Mandar S. Joshi , Nitin V. Sarangdhar , Matthew A. Fisch
IPC分类号： G06F9/46 , G06F13/08
CPC分类号： G06F9/52
摘要： In a computer system, an apparatus for handling lock conditions wherein a first instruction executed by a first processor processes data that is common to a second processor while the second processor is locked from simultaneously executing a second instruction that also processes this same data. A lock bit is set when the first processor begins execution of the first instruction. Thereupon, the second processor is prevented from executing its instruction until the first processor has completed its processing of the shared data. Hence, the second processor queues its request in a buffer. The lock bit is cleared after the first processor has completed execution of its instruction. The first processor then checks the buffer for any outstanding requests. In response to the second processor's queued request, the first processor transmits a signal to the second processor indicating that the data is now not locked.
摘要翻译：在计算机系统中，一种用于处理锁定条件的装置，其中由第一处理器执行的第一指令在第二处理器被锁定时处理与第二处理器相同的数据，同时执行也处理该相同数据的第二指令。当第一个处理器开始执行第一个指令时，锁定位被置位。于是，第二处理器被阻止执行其指令，直到第一处理器完成对共享数据的处理。因此，第二处理器将其请求排队在缓冲器中。在第一个处理器完成其指令执行后，锁定位被清零。然后，第一个处理器检查缓冲区是否有任何未完成的请求。响应于第二处理器的排队请求，第一处理器向第二处理器发送指示数据现在不被锁定的信号。

23. 发明授权

US5774700A Method and apparatus for determining the timing of snoop windows in a pipelined bus 失效
标题翻译：用于确定流水线总线中的窥探窗口的定时的方法和装置
公开(公告)号：US5774700A
公开(公告)日：1998-06-30
申请号：US425370
申请日：1995-04-20
申请人： Matthew A. Fisch , Nitin V. Sarangdhar
发明人： Matthew A. Fisch , Nitin V. Sarangdhar
IPC分类号： G06F12/08 , G06F1/04
CPC分类号： G06F12/0831
摘要： A method and apparatus for determining the timing of snoop windows in a pipelined bus includes a snoop timer, a snoop counter, and snoop resolution logic. The snoop timer indicates the number of clocks until the next snoop window. The snoop counter keeps track of the number of snoop windows currently being tracked by the apparatus and is updated by the snoop resolution logic. In one embodiment, the snoop resolution logic updates the snoop counter when a snoop event occurs on the bus. In one embodiment, the apparatus also includes snoop drive logic which drives snoop result signals onto the bus during snoop windows.
摘要翻译：用于确定流水线总线中的窥探窗口的定时的方法和装置包括窥探定时器，窥探计数器和窥探分辨率逻辑。监听定时器指示下一个监听窗口之前的时钟数。窥探计数器跟踪当前由设备跟踪的窥探窗口的数量，并由窥探分辨率逻辑更新。在一个实施例中，当在总线上发生窥探事件时，窥探分辨率逻辑更新窥探计数器。在一个实施例中，该装置还包括窥探驱动逻辑，其在窥探窗口期间将窥探结果信号驱动到总线上。

24. 发明授权

US06216208B1 Prefetch queue responsive to read request sequences 失效
标题翻译：预读队列响应读请求序列
公开(公告)号：US06216208B1
公开(公告)日：2001-04-10
申请号：US08999241
申请日：1997-12-29
申请人： Robert Greiner , David L. Hill , Chinna Prudvi , Derek T. Bachand , Matthew A. Fisch
发明人： Robert Greiner , David L. Hill , Chinna Prudvi , Derek T. Bachand , Matthew A. Fisch
IPC分类号： G05F1208
CPC分类号： G06F9/383 , G06F12/0862 , G06F2212/6026
摘要： A prefetching control system provided for a processor. The prefetching queue may include an arbiter, a cache queue and a prefetch queue. The arbiter issues requests including read requests. Responsive to a read request, the cache queue issues a control signal. The prefetch queue receives the control signal and an address associated with the read request. When the received address is a member of a pattern of read requests from sequential memory locations, the prefetch queue issues a prefetch request to the arbiter.
摘要翻译：为处理器提供的预取控制系统。预取队列可以包括仲裁器，高速缓存队列和预取队列。仲裁器发出请求，包括读取请求。响应于读取请求，缓存队列发出控制信号。预取队列接收控制信号和与读取请求相关联的地址。当接收到的地址是来自顺序存储器位置的读取请求的模式的成员时，预取队列向仲裁器发出预取请求。

25. 发明授权

US06209068B1 Read line buffer and signaling protocol for processor 失效
标题翻译：用于处理器的读行缓冲器和信令协议
公开(公告)号：US06209068B1
公开(公告)日：2001-03-27
申请号：US08999242
申请日：1997-12-29
申请人： David L. Hill , Chinna Prudvi , Derek T. Bachand , Matthew A. Fisch
发明人： David L. Hill , Chinna Prudvi , Derek T. Bachand , Matthew A. Fisch
IPC分类号： G06F1216
CPC分类号： G06F12/0831
摘要： A data control method in a microprocessor is disclosed. According to the method, a request is generated on an external bus for data to be read to the processor. The requested data is read from the external bus to an intermediate memory in the processor and, thereafter, read from the intermediate memory to a destination. When the intermediate memory is full, the read of data from the external bus is stalled until the intermediate memory is no longer full. Typically, stalling is accomplished by generating a stall signal on the external bus, which may be generated during a cache coherency phase of the transaction to which the requested data relates.
摘要翻译：公开了一种微处理器中的数据控制方法。根据该方法，在外部总线上生成要向处理器读取的数据的请求。所请求的数据从外部总线读取到处理器中的中间存储器，然后从中间存储器读取到目的地。当中间存储器满时，来自外部总线的数据读取停止，直至中间存储器不再满。通常，停止是通过在外部总线上生成停止信号来实现的，该停止信号可以在所请求的数据所关联的事务的高速缓存一致性阶段期间产生。

26. 发明授权

US5834956A Core clock correction in a 2/N mode clocking scheme 失效
标题翻译：核心时钟校正在2 / N模式计时方案
公开(公告)号：US5834956A
公开(公告)日：1998-11-10
申请号：US709379
申请日：1996-09-06
申请人： Chakrapani Pathikonda , Matthew A. Fisch , Javed S. Barkatullah
发明人： Chakrapani Pathikonda , Matthew A. Fisch , Javed S. Barkatullah
IPC分类号： G06F1/12 , H03K21/00
CPC分类号： G06F1/12
摘要： A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
摘要翻译： 2 / N模式时钟发生器，其通过使用总线时钟使能信号来产生总线时钟信号，从而选择与核心时钟信号同相和异相的总线时钟脉冲。时钟发生器保持总线时钟信号和核心时钟信号之间的同步，使得它们总是处于预定的相位关系。

27. 发明授权

US5826067A Method and apparatus for preventing logic glitches in a 2/n clocking scheme 失效
标题翻译：用于在2 / n计时方案中防止逻辑故障的方法和装置
公开(公告)号：US5826067A
公开(公告)日：1998-10-20
申请号：US709262
申请日：1996-09-06
申请人： Matthew A. Fisch , Chakrapani Pathikonda
发明人： Matthew A. Fisch , Chakrapani Pathikonda
IPC分类号： G06F1/12 , G06F1/04
CPC分类号： G06F1/12
摘要： A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
摘要翻译： 2 / N模式时钟发生器，其通过使用总线时钟使能信号来产生总线时钟信号，从而选择与核心时钟信号同相和异相的总线时钟脉冲。时钟发生器保持总线时钟信号和核心时钟信号之间的同步，使得它们总是处于预定的相位关系。

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