专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20050085035A1 Heterojunction bipolar transistor and manufacturing method making the same 审中-公开
标题翻译：异质结双极晶体管和制造方法相同
公开(公告)号：US20050085035A1
公开(公告)日：2005-04-21
申请号：US10687648
申请日：2003-10-20
申请人： Chih-Chiang Shen , Chang-Jung Chu , Rui-Huang Cheng , Yong-Yin Chen , Norio Hayafuji , Chin-Kun Peng
发明人： Chih-Chiang Shen , Chang-Jung Chu , Rui-Huang Cheng , Yong-Yin Chen , Norio Hayafuji , Chin-Kun Peng
IPC分类号： H01L21/331 , H01L29/737 , H01L29/739
CPC分类号： H01L29/66318 , H01L29/7371
摘要： A method for improving a performance of a heterojunction bipolar transistor is provided. The method includes steps of providing a substrate; forming a first at least one semiconductor layer on the substrate; forming a second at least one semiconductor layer on the first at least one semiconductor layer; and inserting a thermal treatment process within the second at least one semiconductor layer so as to improve a performance of the heterojuntion bipolar transistor. Furthermore, the thermal treatment process is performed at a temperature ranged from 300° C. to 800° C.
摘要翻译：提供了一种用于改善异质结双极晶体管的性能的方法。该方法包括提供衬底的步骤; 在所述衬底上形成第一至少一个半导体层; 在所述第一至少一个半导体层上形成第二至少一个半导体层; 以及在所述第二至少一个半导体层内插入热处理工艺，以便提高所述异质双极晶体管的性能。此外，热处理过程在300℃至800℃的温度下进行。

22. 发明授权

US5874753A Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US5874753A
公开(公告)日：1999-02-23
申请号：US827059
申请日：1997-03-26
申请人： Norio Hayafuji , Yoshitsugu Yamamoto
发明人： Norio Hayafuji , Yoshitsugu Yamamoto
IPC分类号： H01L29/812 , H01L21/285 , H01L21/335 , H01L21/338 , H01L29/08 , H01L29/778 , H01L29/772
CPC分类号： H01L29/66462 , H01L21/28587 , H01L29/0891 , H01L29/7783
摘要： In a field effect transistor including active layers having a heterojunction structure with at least two different semiconductor materials, a layer for supplying electrons is disposed opposite a drain electrode, in contact with a region of the active layers including a dopant impurity producing n type conductivity. Therefore, degradation of the electrical characteristics caused by trapping of electrons in a drain ohmic contact layer due to fluorine diffusing into the semiconductor layers is suppressed by supplying electrons from the layer opposite the drain electrode, thereby improving reliability of the field effect transistor including the heterojunction structure.
摘要翻译：在包括具有至少两种不同半导体材料的异质结结构的有源层的场效应晶体管中，用于提供电子的层与漏极相对地设置，与包括产生n型导电性的掺杂剂杂质的有源层的区域相接触。因此，通过从与漏电极相对的层提供电子来抑制由于氟扩散到半导体层而在漏极欧姆接触层中捕获电子引起的电特性的劣化，从而提高包括异质结的场效应晶体管的可靠性结构体。

23. 发明授权

US5811843A Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US5811843A
公开(公告)日：1998-09-22
申请号：US805363
申请日：1997-02-24
申请人： Yoshitsugu Yamamoto , Norio Hayafuji
发明人： Yoshitsugu Yamamoto , Norio Hayafuji
IPC分类号： H01L29/812 , H01L21/338 , H01L29/778
CPC分类号： H01L29/7783
摘要： A field effect transistor includes a semi-insulating III-V compound semiconductor substrate; a channel layer disposed on the substrate; an n type electron supply layer disposed on the channel layer and comprising a mixed crystalline compound semiconductor layer including AlAs; an n type ohmic contact layer disposed on the electron supply layer; source and drain electrodes disposed on the ohmic contact layer; an opening in a region between the source and drain electrodes penetrating the ohmic contact layer; a gate electrode disposed in the opening and making a Schotty contact; and a surface protection film of a semiconductor material free of Al, In, and As, covering the opening except where the gate electrode is present. Fluorine is prevented from getting into the electron supply layer with no increase in transconductance or source resistance by providing a layer between the source and a channel, and between the gate and the channel.
摘要翻译：场效应晶体管包括半绝缘III-V化合物半导体衬底; 设置在所述基板上的沟道层; n型电子供给层，其设置在所述沟道层上，并且包括含有AlAs的混合晶体化合物半导体层; 设置在电子供给层上的n型欧姆接触层; 源极和漏极设置在欧姆接触层上; 在源极和漏极之间穿过欧姆接触层的区域中的开口; 设置在开口中并形成Schotty接触的栅电极; 以及不含有Al，In和As的半导体材料的表面保护膜，覆盖除了存在栅极之外的开口。通过在源极和通道之间以及栅极和沟道之间提供一层，防止氟通过跨导或源极电阻的增加而进入电子供给层。

24. 发明授权

US5764673A Semiconductor light emitting device 失效
标题翻译：半导体发光器件
公开(公告)号：US5764673A
公开(公告)日：1998-06-09
申请号：US937152
申请日：1997-09-25
申请人： Zempei Kawazu , Norio Hayafuji , Diethard Marx
发明人： Zempei Kawazu , Norio Hayafuji , Diethard Marx
IPC分类号： H01L33/00 , H01L33/12 , H01L33/14 , H01L33/32 , H01L33/34 , H01S5/00 , H01S5/02 , H01S5/042 , H01S5/323 , H01S3/19 , H01L31/0256
CPC分类号： H01S5/32341 , H01L33/007 , H01S2301/173 , H01S2304/04 , H01S5/0202 , H01S5/021 , H01S5/2231
摘要： A semiconductor light emitting device includes an Si substrate having opposed front and rear surfaces; an amorphous or polycrystalline first buffer layer disposed on the front surface of the Si substrate; and GaN series compound semiconductor layers successively disposed on the first buffer layer and including a light emitting region where light is produced by recombination of electrons and holes. In this light emitting device, since the Si substrate is cleavable, it is possible to produce resonator facets by cleaving. In addition, since the Si substrate is electrically conductive, a structure in which a pair of electrodes are respectively located on opposed upper and lower surfaces of the light emitting device is realized. Further, since the Si substrate is inexpensive, the light emitting device is obtained at low cost. Furthermore, since the amorphous or polycrystalline first buffer layer is disposed on the Si substrate, in the initial state of the growth of the GaN series compound semiconductor layers, plenty of growth nuclei are created, and the growth nuclei promote two-dimensional growth. As a result, high-quality GaN series compound semiconductor layers are obtained.
摘要翻译：半导体发光器件包括具有相对的前表面和后表面的Si衬底; 设置在Si衬底的前表面上的非晶或多晶第一缓冲层; 以及连续配置在第一缓冲层上的GaN系化合物半导体层，具有通过电子和空穴的复合产生光的发光区域。在该发光器件中，由于Si衬底是可切割的，所以可以通过切割产生谐振器面。此外，由于Si衬底是导电的，所以实现了一对电极分别位于发光器件的相对的上表面和下表面上的结构。此外，由于Si基板便宜，所以以低成本获得发光器件。此外，由于非晶或多晶第一缓冲层设置在Si衬底上，在GaN系化合物半导体层的生长的初始状态下，产生大量的生长核，并且生长核促进二维生长。结果，获得了高质量的GaN系化合物半导体层。

25. 发明授权

US5602414A Infrared detector having active regions and isolating regions formed of CdHgTe 失效
标题翻译：具有活性区域和由CdHgTe形成的隔离区域的红外探测器
公开(公告)号：US5602414A
公开(公告)日：1997-02-11
申请号：US260791
申请日：1994-06-16
申请人： Kotaro Mitsui , Zenpei Kawazu , Kazuo Mizuguchi , Seiji Ochi , Yuji Ohkura , Norio Hayafuji , Hirotaka Kizuki , Mari Tsugami , Akihiro Takami , Manabu Katoh
发明人： Kotaro Mitsui , Zenpei Kawazu , Kazuo Mizuguchi , Seiji Ochi , Yuji Ohkura , Norio Hayafuji , Hirotaka Kizuki , Mari Tsugami , Akihiro Takami , Manabu Katoh
IPC分类号： H01L27/14 , H01L27/146 , H01L31/10 , H01L31/00
CPC分类号： H01L27/14649
摘要： In a method for fabricating an infrared detector, initially, a CdHgTe layer of a first conductivity type is produced on a front surface of a semiconductor substrate, a plurality of spaced apart CdHgTe regions of a second conductivity type, opposite the first conductivity type, are produced at the surface of the first conductivity type CdHgTe layer, and part of the surface of the first conductivity type CdHgTe layer between the second conductivity type CdHgTe regions is selectively irradiated with a charged particle beam to evaporate Hg atoms from that part, whereby a CdHgTe separation region of the first conductivity type and having a Cd composition larger than that of the first conductivity type CdHgTe layer is produced penetrating through the first conductivity type CdHgTe layer and surrounding each of the second conductivity type CdHgTe regions. Therefore, a highly-integrated high-resolution infrared detector with no crosstalk between pixels is achieved.
摘要翻译：在红外线检测器的制造方法中，首先，在半导体基板的正面形成有与第一导电型相反的多个第二导电类型的间隔开的CdHgTe区域的第一导电型CdHgTe层，在第一导电型CdHgTe层的表面产生，并且第二导电型CdHgTe区域之间的第一导电类型CdHgTe层的表面的一部分被带电粒子束选择性地照射，以从该部分蒸发Hg原子，由此CdHgTe 产生具有比第一导电型CdHgTe层的Cd组分大的第一导电类型的分离区，穿过第一导电型CdHgTe层并围绕每个第二导电型CdHgTe区。因此，实现了在像素之间没有串扰的高度集成的高分辨率红外检测器。

26. 发明授权

US5573960A Method of manufacturing semiconductor layers by bonding without defects created by bonding 失效
标题翻译：通过接合制造半导体层而不产生通过接合产生缺陷的方法
公开(公告)号：US5573960A
公开(公告)日：1996-11-12
申请号：US500247
申请日：1995-07-10
申请人： Shigekazu Izumi , Norio Hayafuji
发明人： Shigekazu Izumi , Norio Hayafuji
IPC分类号： H01L29/73 , H01L21/306 , H01L21/331 , H01L21/58 , H01L21/68 , H01L23/373 , H01L29/737 , H01L21/265
CPC分类号： H01L21/6835 , H01L23/3735 , H01L24/26 , H01L24/83 , H01L2221/68359 , H01L2221/68363 , H01L2224/8319 , H01L2224/8385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0103 , H01L2924/01033 , H01L2924/01074 , H01L2924/0132 , H01L2924/07802 , H01L2924/10329 , H01L2924/10336 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , Y10S148/012 , Y10S148/051 , Y10S148/072 , Y10S148/15 , Y10S438/933
摘要： A method of manufacturing a semiconductor layer includes preparing a first semiconductor substrate; forming an etching stop layer on the surface of the first substrate; forming an active layer on the etching stop layer; forming a crystal defect reducing layer on the active layer; preparing a second semiconductor substrate having a heat conductivity higher than the heat conductivity of the first substrate; bonding the crystal defect reducing layer to the second substrate; selectively etching the first substrate to expose the etching stop layer; selectively etching the etching stop layer to expose the active layer, whereby the active layer is disposed on the second substrate with the crystal defect reducing layer therebetween. The heat dissipation property is significantly improved by the second substrate having a high heat conductivity and by reducing the thicknesses of the active layer and the crystal defect reducing layer. In addition, good crystallinity of the active layer and sufficient mechanical strength of the substrate are obtained.
摘要翻译：制造半导体层的方法包括：制备第一半导体衬底; 在所述第一基板的表面上形成蚀刻停止层; 在所述蚀刻停止层上形成有源层; 在有源层上形成晶体缺陷减少层; 制备导热率高于第一衬底的导热率的第二半导体衬底; 将所述晶体缺陷减少层接合到所述第二基板; 选择性地蚀刻第一衬底以暴露蚀刻停止层; 选择性地蚀刻蚀刻停止层以暴露有源层，由此有源层设置在第二衬底上，其间具有晶体缺陷降低层。通过具有高导热性的第二基板和通过减小有源层和晶体缺陷降低层的厚度，显着提高了散热性能。此外，获得了活性层的良好的结晶度和基材的足够的机械强度。

27. 发明授权

US5316967A Method for producing semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US5316967A
公开(公告)日：1994-05-31
申请号：US975109
申请日：1992-11-12
申请人： Nobuaki Kaneno , Hirotaka Kizuki , Norio Hayafuji , Tetsuo Shiba , Hitoshi Tada
发明人： Nobuaki Kaneno , Hirotaka Kizuki , Norio Hayafuji , Tetsuo Shiba , Hitoshi Tada
IPC分类号： H01L21/20 , H01L21/308 , H01S5/20 , H01S5/223 , H01S5/227 , H01S5/323
CPC分类号： H01L21/3081 , H01L21/02392 , H01L21/02395 , H01L21/02463 , H01L21/02505 , H01L21/02546 , H01L21/0262 , H01S5/2231 , H01S2304/04 , H01S5/2081 , H01S5/2277 , H01S5/32325
摘要： In a method for producing a semiconductor device, a first semiconductor layer is epitaxially grown on a semiconductor substrate, an insulating film pattern is formed on the first semiconductor layer, and portions of the first semiconductor layer are removed by wet etching using the insulating film pattern as a mask to leave a ridge having a reverse mesa shape and a width. Ends of the insulating film pattern are removed by etching to approximately the width of the ridge, a second semiconductor layer is epitaxially grown on opposite sides of the ridge, and a third semiconductor layer is epitaxially grown on the ridge and the second semiconductor layer. The second semiconductor layer is evenly grown without concave portions at opposite sides of the ridge. In addition, the third semiconductor layer is evenly grown on the ridge and the second semiconductor layer, and an electrode reliably connects the surface of the third semiconductor layer. A semiconductor device with good performance and high reliability is reproducibly manufactured.
摘要翻译：在制造半导体器件的方法中，在半导体衬底上外延生长第一半导体层，在第一半导体层上形成绝缘膜图案，并且通过使用绝缘膜图案的湿蚀刻去除第一半导体层的部分作为掩模，离开具有反台面形状和宽度的脊。绝缘膜图案的端部通过蚀刻到脊的宽度去除，在脊的相对侧上外延生长第二半导体层，并且在脊和第二半导体层上外延生长第三半导体层。第二半导体层在脊的相对侧均匀生长而没有凹部。此外，第三半导体层均匀地生长在脊和第二半导体层上，并且电极可靠地连接第三半导体层的表面。可重复地制造具有良好性能和高可靠性的半导体器件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式