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21. 发明申请

US20070230336A1 Reconfigurable circuit 有权
标题翻译：可重构电路
公开(公告)号：US20070230336A1
公开(公告)日：2007-10-04
申请号：US11545477
申请日：2006-10-11
申请人： Takashi Hanai , Tetsuo Kawano
发明人： Takashi Hanai , Tetsuo Kawano
IPC分类号： H04L12/26
CPC分类号： G06F15/7867
摘要： A reconfigurable circuit includes a network circuit for controlling connections between the output terminal and the input terminal of an arithmetic unit group, and a first selector connected between the arithmetic unit group and the network circuit. When a first control signal is in a first state, the first selector connects a first terminal of the arithmetic unit group to a first terminal of the network circuit, and also connects a second terminal of the arithmetic unit group to a second terminal of the network circuit. Meanwhile, when the first control signal is in a second state, the first selector connects the first terminal of the arithmetic unit group to the second terminal of the network circuit, and also connects the second terminal of the arithmetic unit group to the first terminal of the network circuit.
摘要翻译：可重构电路包括：网络电路，用于控制运算单元组的输出端和输入端之间的连接;以及连接在算术单元组和网络电路之间的第一选择器。当第一控制信号处于第一状态时，第一选择器将运算单元组的第一端连接到网络电路的第一端，并且将运算单元组的第二端连接到网络的第二终端电路。同时，当第一控制信号处于第二状态时，第一选择器将运算单元组的第一端连接到网络电路的第二端，并且将运算单元组的第二端连接到网络电路。

22. 发明授权

US09720879B2 Reconfigurable circuit having rows of a matrix of registers connected to corresponding ports and a semiconductor integrated circuit 有权
公开(公告)号：US09720879B2
公开(公告)日：2017-08-01
申请号：US12973730
申请日：2010-12-20
申请人： Shinichi Sutou , Ichiro Kasama , Kyoji Sato , Takashi Hanai , Kiyomitsu Katou , Takahiro Kubota , Junji Sahoda
发明人： Shinichi Sutou , Ichiro Kasama , Kyoji Sato , Takashi Hanai , Kiyomitsu Katou , Takahiro Kubota , Junji Sahoda
IPC分类号： G06F15/76 , G06F15/78 , G06F9/30 , G06F9/38
CPC分类号： G06F15/7867 , G06F9/3012 , G06F9/30141 , G06F9/3877
摘要： A reconfigurable circuit includes a plurality of processing elements and an input/output data interface unit, and the reconfigurable circuit is configured to control connections of the plurality of processing elements for each context. The input/output data interface unit is configured to hold operation input data which is input to the plurality of processing elements and operation output data which is output from the plurality of processing elements. The input/output data interface unit includes a plurality of ports, and a plurality of registers. The registers are configured to be connected to the plurality of ports, and to include m (m being an integer of 2 or more) number of banks in a depth direction.

23. 发明申请

US20130002292A1 RECONFIGURABLE INTEGRATED CIRCUIT DEVICE 有权
标题翻译：可重构集成电路设备
公开(公告)号：US20130002292A1
公开(公告)日：2013-01-03
申请号：US13458255
申请日：2012-04-27
申请人： Hayato HIGUCHI , Takashi Hanai
发明人： Hayato HIGUCHI , Takashi Hanai
IPC分类号： G06F7/38
CPC分类号： G06F15/7875 , G06F15/7867
摘要： A reconfigurable integrated circuit device includes plural processing elements each including an arithmetic circuit, and being configured in any computing state based on the configuration data; and an inter-processing element network which connects the processing elements in any state based on the configuration data. And the processing element inputs an input valid signal and an input data signal, and outputs an output valid signal and an output data signal, and includes an input data holding register, an arithmetic processing circuit, and an output data holding register which holds the computing result data, and when the configuration is updated by configuration data which makes a hold mode valid, regardless of the input valid signal, valid or invalid, the input data holding register holds the input data signal upon the update and the arithmetic processing circuit performs computing processing on the input data signal held in the input data holding register.
摘要翻译：可重构集成电路装置包括多个处理元件，每个处理元件包括运算电路，并且被配置为基于配置数据的任何计算状态; 以及基于配置数据在任何状态下连接处理元件的相互处理元件网络。并且处理元件输入输入有效信号和输入数据信号，并输出输出有效信号和输出数据信号，并且包括输入数据保持寄存器，运算处理电路和保持计算的输出数据保持寄存器结果数据，并且当通过使保持模式有效的配置数据来更新配置时，无论输入有效信号如何有效或无效，输入数据保持寄存器在更新时保持输入数据信号，并且运算处理电路执行计算对保存在输入数据保持寄存器中的输入数据信号进行处理。

24. 发明授权

US07784526B2 Sand-introducing device using air, and method and apparatus for producing mold 有权
公开(公告)号：US07784526B2
公开(公告)日：2010-08-31
申请号：US12588337
申请日：2009-10-13
申请人： Hisashi Harada , Takuya Nitta , Takashi Hanai , Minoru Hirata , Kozo Sugita , Toshihiko Oya
发明人： Hisashi Harada , Takuya Nitta , Takashi Hanai , Minoru Hirata , Kozo Sugita , Toshihiko Oya
IPC分类号： B22C15/02 , B22C15/24
CPC分类号： B22C15/24 , B22C15/28
摘要： A sand-introducing device that uses air for introducing molding sand in a molding space or spaces is provided. The device is provided with air-permeable partitioning plates that define a double-walled structure together with the wall of the body of the device. The air-permeable partitioning plates are easily produced, they can easily inject pressurized air of a desired pressure, and they will not need regular maintenance. The body of the device, which acts as a pressure tank, defines a double-walled structure together with the air-permeable partitioning plates (10, 11), thereby defining chambers (12, 13). In the sand-introducing device that uses air, while molding sand is fluidized by pressurized air injected from the air-permeable partitioning plates, it is introduced in a molding space. Each air-permeable partitioning plate is made of a porous resin or metal.

25. 发明授权

US07762307B2 Sand-introducing device using air, and method and apparatus for producing a mold 有权
标题翻译：使用空气的导砂装置，以及用于制造模具的方法和装置
公开(公告)号：US07762307B2
公开(公告)日：2010-07-27
申请号：US11882057
申请日：2007-07-30
申请人： Hisashi Harada , Takuya Nitta , Takashi Hanai , Minoru Hirata , Kozo Sugita , Toshihiko Oya
发明人： Hisashi Harada , Takuya Nitta , Takashi Hanai , Minoru Hirata , Kozo Sugita , Toshihiko Oya
IPC分类号： B22C15/02 , B22C15/24
CPC分类号： B22C15/24 , B22C15/28
摘要： A sand-introducing device that uses air for introducing molding sand in a molding space or spaces is provided. The device is provided with air-permeable partitioning plates that define a double-walled structure together with the wall of the body of the device. The air-permeable partitioning plates are easily produced, they can easily inject pressurized air of a desired pressure, and they will not need regular maintenance. The body of the device, which acts as a pressure tank, defines a double-walled structure together with the air-permeable partitioning plates (10, 11), thereby defining chambers (12, 13). In the sand-introducing device that uses air, while molding sand is fluidized by pressurized air injected from the air-permeable partitioning plates, it is introduced in a molding space. Each air-permeable partitioning plate is made of a porous resin or metal.
摘要翻译：提供了一种使用空气将模型空间中引入型砂的砂子引入装置。该装置设置有透气分隔板，其与装置的主体的壁一起限定双壁结构。透气分隔板易于制造，它们可以容易地注入所需压力的加压空气，并且不需要定期维护。用作压力罐的装置的主体与透气分隔板（10,11）一起限定双壁结构，从而限定室（12,13）。在使用空气的砂导入装置中，通过从透气性分隔板喷射的加压空气使型砂流化，将其引入成型空间。每个透气分隔板由多孔树脂或金属制成。

26. 发明授权

US08451022B2 Integrated circuit and input data controlling method for reconfigurable circuit 有权
标题翻译：用于可重构电路的集成电路和输入数据控制方法
公开(公告)号：US08451022B2
公开(公告)日：2013-05-28
申请号：US11802825
申请日：2007-05-25
申请人： Tetsuo Kawano , Takashi Hanai , Shinichi Sutou
发明人： Tetsuo Kawano , Takashi Hanai , Shinichi Sutou
IPC分类号： H03K19/173
CPC分类号： G06F17/5054
摘要： An integrated circuit according to the invention includes a reconfigurable circuit including a plurality of computing units interconnected in a reconfigurable manner, and an input data controlling section. The input data controlling section controls input data such that the data is inputted to the reconfigurable circuit in response to a configuration of the reconfigurable circuit.
摘要翻译：根据本发明的集成电路包括可重配置方式包括多个计算单元互连的可重构电路和输入数据控制部分。输入数据控制部分控制输入数据，使得响应于可重构电路的配置将数据输入到可重构电路。

27. 发明授权

US08171259B2 Multi-cluster dynamic reconfigurable circuit for context valid processing of data by clearing received data with added context change indicative signal 有权
标题翻译：多集群动态可重构电路，用于通过用添加的上下文改变指示信号清除接收到的数据来上下文有效地处理数据
公开(公告)号：US08171259B2
公开(公告)日：2012-05-01
申请号：US12394863
申请日：2009-02-27
申请人： Takashi Hanai , Shinichi Sutou
发明人： Takashi Hanai , Shinichi Sutou
IPC分类号： G06F15/16
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/3879 , G06F9/3891 , G06F9/3897 , G06F15/7867
摘要： A dynamic reconfigurable circuit includes multiple clusters each including a group of reconfigurable processing elements. The dynamic reconfigurable circuit is capable of dynamically changing a configuration of the clusters according to a context including a description of processing of the processing elements and of connection between the processing elements. A first cluster among the clusters includes a signal generating circuit that when an instruction to change the context is received, generates a report signal indicative of the instruction to change the context; a signal adding circuit that adds the report signal generated by the signal generating circuit to output data that is to be transmitted from the first cluster to a second cluster; and a data clearing circuit that, when output data to which a report signal generated by the second cluster is added is received, performs a clearing process of clearing the output data received.
摘要翻译：动态可重构电路包括多个簇，每个簇包括一组可重构处理元件。动态可重构电路能够根据包括处理元件的处理描述和处理元件之间的连接的上下文来动态地改变簇的配置。簇中的第一簇包括信号发生电路，当接收到改变上下文的指令时，产生指示改变上下文的指令的报告信号; 信号添加电路，其将由所述信号发生电路生成的所述报告信号与从所述第一簇发送到第二簇的输出数据相加; 以及数据清除电路，当接收到添加了由第二群集生成的报告信号的输出数据时，执行清除所接收的输出数据的清除处理。

28. 发明授权

US08099540B2 Reconfigurable circuit 有权
标题翻译：可重构电路
公开(公告)号：US08099540B2
公开(公告)日：2012-01-17
申请号：US11545477
申请日：2006-10-11
申请人： Takashi Hanai , Tetsuo Kawano
发明人： Takashi Hanai , Tetsuo Kawano
IPC分类号： G06F13/00 , G06F15/00 , G06F7/38
CPC分类号： G06F15/7867
摘要： A reconfigurable circuit includes a network circuit for controlling connections between the output terminal and the input terminal of an arithmetic unit group, and a first selector connected between the arithmetic unit group and the network circuit. When a first control signal is in a first state, the first selector connects a first terminal of the arithmetic unit group to a first terminal of the network circuit, and also connects a second terminal of the arithmetic unit group to a second terminal of the network circuit. Meanwhile, when the first control signal is in a second state, the first selector connects the first terminal of the arithmetic unit group to the second terminal of the network circuit, and also connects the second terminal of the arithmetic unit group to the first terminal of the network circuit.
摘要翻译：可重构电路包括：网络电路，用于控制运算单元组的输出端和输入端之间的连接;以及连接在算术单元组和网络电路之间的第一选择器。当第一控制信号处于第一状态时，第一选择器将运算单元组的第一端连接到网络电路的第一端，并且将运算单元组的第二端连接到网络的第二终端电路。同时，当第一控制信号处于第二状态时，第一选择器将运算单元组的第一端连接到网络电路的第二端，并且将运算单元组的第二端连接到网络电路。

29. 发明授权

US07996661B2 Loop processing counter with automatic start time set or trigger modes in context reconfigurable PE array 有权
标题翻译：循环处理计数器，具有自动启动时间设置或上下文可重构PE阵列中的触发模式
公开(公告)号：US07996661B2
公开(公告)日：2011-08-09
申请号：US12232462
申请日：2008-09-17
申请人： Takashi Hanai , Shinichi Sutou , Masaki Arai , Mitsuharu Wakayoshi
发明人： Takashi Hanai , Shinichi Sutou , Masaki Arai , Mitsuharu Wakayoshi
IPC分类号： G06F9/30
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3885 , G06F9/3897 , G06F15/7867
摘要： A dynamic reconfigurable circuit that implements optional processing by dynamically switching a processing content of a reconfigurable processing element (PE) and a connection content between the PEs in accordance with a context, includes: a configuration register section for setting a content of loop processing on the basis of the context, the loop processing content including an output source of an output signal from each of a set of the reconfigured PEs, an output destination of the output signal, and a condition for outputting the output signal to the output destination; and at least one counter circuit including a loop control section and an output register section that implement the set loop processing, that count the number of implementations of the loop processing implemented by the loop control section, and that output the output signal to the output destination based on the counted number of implementations and the condition.
摘要翻译：一种动态可重构电路，其通过根据上下文动态切换可重构处理元件（PE）的处理内容和PE之间的连接内容来实现可选处理，包括：配置寄存器部分，用于在上下文的基础，循环处理内容包括来自一组重新配置的PE中的每一个的输出信号的输出源，输出信号的输出目的地以及用于将输出信号输出到输出目的地的条件; 以及至少一个计数器电路，包括循环控制部分和实现设置循环处理的输出寄存器部分，其对由循环控制部分实现的循环处理的执行次数进行计数，并将输出信号输出到输出目的地基于计数的实施数量和条件。

30. 发明申请

US20080079459A1 Integrated circuit and input data controlling method for reconfigurable circuit 有权
标题翻译：用于可重构电路的集成电路和输入数据控制方法
公开(公告)号：US20080079459A1
公开(公告)日：2008-04-03
申请号：US11802825
申请日：2007-05-25
申请人： Tetsuo Kawano , Takashi Hanai , Shinichi Sutou
发明人： Tetsuo Kawano , Takashi Hanai , Shinichi Sutou
IPC分类号： H03K19/173
CPC分类号： G06F17/5054
摘要： An integrated circuit according to the invention includes a reconfigurable circuit including a plurality of computing units interconnected in a reconfigurable manner, and an input data controlling section. The input data controlling section controls input data such that the data is inputted to the reconfigurable circuit in response to a configuration of the reconfigurable circuit.
摘要翻译：根据本发明的集成电路包括可重配置方式包括多个计算单元互连的可重构电路和输入数据控制部分。输入数据控制部分控制输入数据，使得响应于可重构电路的配置将数据输入到可重构电路。

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