专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US08592866B2 Transistor 有权
标题翻译：晶体管
公开(公告)号：US08592866B2
公开(公告)日：2013-11-26
申请号：US11600102
申请日：2006-11-16
申请人： Manabu Yanagihara , Masahiro Hikita , Tetsuzo Ueda , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Manabu Yanagihara , Masahiro Hikita , Tetsuzo Ueda , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H01L29/66
CPC分类号： H01L29/7787 , H01L29/1066 , H01L29/2003 , H01L29/4175 , H01L29/432 , H01L29/66462
摘要： A transistor includes a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer and has a band gap larger than that of the first semiconductor layer, a control layer formed on the second semiconductor layer and contains p-type impurities, a gate electrode formed in contact with at least part of the control layer and a source electrode and a drain electrode formed on both sides of the control layer, respectively. A third semiconductor layer made of material having a lower etch rate than that of the control layer is formed between the control layer and the second semiconductor layer.
摘要翻译：晶体管包括形成在基板上的第一半导体层，形成在第一半导体层上并具有比第一半导体层的带隙大的带隙的第二半导体层，形成在第二半导体层上并包含p型杂质，形成为与控制层的至少一部分接触的栅极电极以及分别形成在控制层两侧的源电极和漏电极。在控制层和第二半导体层之间形成由蚀刻率低于控制层的材料制成的第三半导体层。

22. 发明授权

US08264002B2 Field-effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：US08264002B2
公开(公告)日：2012-09-11
申请号：US12880704
申请日：2010-09-13
申请人： Masahiro Hikita , Tetsuzo Ueda , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Masahiro Hikita , Tetsuzo Ueda , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H01L29/66 , H01L21/02 , H01L29/78
CPC分类号： H01L29/7786 , H01L29/0843 , H01L29/1066 , H01L29/2003 , H01L29/432 , H01L29/66462 , H01L29/7783
摘要： An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.
摘要翻译：依次形成AlN缓冲层，未掺杂的GaN层，未掺杂的AlGaN层，p型GaN层和重掺杂的p型GaN层。栅电极与重掺杂的p型GaN层形成欧姆接触。源电极和漏电极设置在未掺杂的AlGaN层上。通过在未掺杂的AlGaN层和未掺杂的GaN层和p型GaN层之间的界面处产生的二维电子气在栅极区域中形成pn结，从而可以提高栅极电压。

23. 发明申请

US20110049574A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20110049574A1
公开(公告)日：2011-03-03
申请号：US12917994
申请日：2010-11-02
申请人： Hiroaki UENO , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Hiroaki UENO , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H01L29/778
CPC分类号： H01L29/7786 , H01L29/1066 , H01L29/2003 , H01L29/452
摘要： A semiconductor device includes a first group III-V nitride semiconductor layer, a second group III-V nitride semiconductor layer having a larger band gap than the first group III-V nitride semiconductor layer and at least one ohmic electrode successively formed on a substrate. The ohmic electrode is formed so as to have a base portion penetrating the second group III-V nitride semiconductor layer and reaching a portion of the first group III-V nitride semiconductor layer disposed beneath a two-dimensional electron gas layer. An impurity doped layer is formed in portions of the first group III-V nitride semiconductor layer and the second group III-V nitride semiconductor layer in contact with the ohmic electrode.
摘要翻译：半导体器件包括第一III-V族氮化物半导体层，具有比第一III-V族氮化物半导体层更大的带隙的第二III-V族氮化物半导体层和在衬底上依次形成的至少一个欧姆电极。欧姆电极形成为具有穿透第二III-V族氮化物半导体层并且到达设置在二维电子气体层下方的第一III-V族氮化物半导体层的一部分的基极部分。在与欧姆电极接触的第一III-V族氮化物半导体层和第二III-V族氮化物半导体层的部分中形成杂质掺杂层。

24. 发明授权

US07528423B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07528423B2
公开(公告)日：2009-05-05
申请号：US11681408
申请日：2007-03-02
申请人： Hiroaki Ueno , Tetsuzo Ueda , Yasuhiro Uemoto , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara , Yutaka Hirose , Masahiro Hikita
发明人： Hiroaki Ueno , Tetsuzo Ueda , Yasuhiro Uemoto , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara , Yutaka Hirose , Masahiro Hikita
IPC分类号： H01L31/072 , H01L31/109
CPC分类号： H01L29/7786 , H01L29/2003
摘要： It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform. An insulating film 18 with a dielectric constant higher than that of the barrier layer is further inserted between a gate electrode 16 and the barrier layers 13, so that an improvement in gm and a reduction in gate leakage current can be achieved.
摘要翻译：本发明的一个目的是提供一种可以同时实现HFET的常闭模式和改进Imax的半导体器件，并进一步实现gm的改善和栅极漏电流的减小。为了在栅电极正下方的基板11的操作层12上保持薄的阻挡层13，主要用于实现常关模式并且还实现了高的Imax，它被配置成使得厚度可以通过栅极和源极区域之间以及栅极和漏极区域之间的半导体层17来增加阻挡层13。因此，与设置阻挡层的厚度均匀的FET相比，可以实现常闭模式和Imax的改善。介电常数高于阻挡层的绝缘膜18进一步插入在栅电极16和阻挡层13之间，从而可以实现gm的改善和栅极漏电流的减小。

25. 发明申请

US20080303162A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20080303162A1
公开(公告)日：2008-12-11
申请号：US12100245
申请日：2008-04-09
申请人： Hidetoshi Ishida , Manabu Yanagihara , Yasuhiro Uemoto , Daisuke Ueda
发明人： Hidetoshi Ishida , Manabu Yanagihara , Yasuhiro Uemoto , Daisuke Ueda
IPC分类号： H01L23/48
CPC分类号： H01L29/7787 , H01L29/0692 , H01L29/2003 , H01L29/402 , H01L29/405 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a layered structure including a first nitride semiconductor layer and a second nitride semiconductor layer that are sequentially formed over a substrate in this order. The second nitride semiconductor layer has a wider bandgap than the first nitride semiconductor layer. A first electrode and a second electrode are formed spaced apart from each other on the layered structure. A first insulating layer with a high breakdown field is formed in a region with electric field concentration between the first electrode and the second electrode over the layered structure. The first insulating layer has a higher breakdown field than air.
摘要翻译：半导体器件包括依次形成在衬底上的第一氮化物半导体层和第二氮化物半导体层的层状结构。第二氮化物半导体层具有比第一氮化物半导体层更宽的带隙。第一电极和第二电极在分层结构上彼此间隔开形成。在分层结构上，在第一电极和第二电极之间的电场浓度的区域中形成具有高击穿电场的第一绝缘层。第一绝缘层具有比空气更高的击穿场。

26. 发明申请

US20070210332A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20070210332A1
公开(公告)日：2007-09-13
申请号：US11681408
申请日：2007-03-02
申请人： Hiroaki UENO , Tetsuzo Ueda , Yasuhiro Uemoto , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara , Yutaka Hirose , Masahiro Hikita
发明人： Hiroaki UENO , Tetsuzo Ueda , Yasuhiro Uemoto , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara , Yutaka Hirose , Masahiro Hikita
IPC分类号： H01L31/00
CPC分类号： H01L29/7786 , H01L29/2003
摘要： It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform. An insulating film 18 with a dielectric constant higher than that of the barrier layer is further inserted between a gate electrode 16 and the barrier layers 13, so that an improvement in gm and a reduction in gate leakage current can be achieved.
摘要翻译：本发明的一个目的是提供一种半导体器件，其可以同时实现HFET的常闭模式和改进的最大值，并进一步实现gm的改善和栅极漏电流的减小。为了在栅电极正下方的基板11的操作层12上保持薄势垒层13，主要用于实现常关模式并且还实现高I max，配置成使得栅极和源极区域之间以及栅极和漏极区域之间的半导体层17可以增加阻挡层13的厚度。因此与阻挡层的厚度被设计为均匀的FET相比，可以实现常关模式和I 的改善。介电常数高于阻挡层的绝缘膜18进一步插入在栅电极16和阻挡层13之间，从而改善gm和栅极漏电流的减小可以实现。

27. 发明申请

US20060273347A1 Field-effect transistor and method for fabricating the same 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20060273347A1
公开(公告)日：2006-12-07
申请号：US11433734
申请日：2006-05-15
申请人： Masahiro Hikita , Tetsuzo Ueda , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Masahiro Hikita , Tetsuzo Ueda , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H01L31/00
CPC分类号： H01L29/7786 , H01L29/0843 , H01L29/1066 , H01L29/2003 , H01L29/432 , H01L29/66462 , H01L29/7783
摘要： An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.
摘要翻译：依次形成AlN缓冲层，未掺杂的GaN层，未掺杂的AlGaN层，p型GaN层和重掺杂的p型GaN层。栅电极与重掺杂的p型GaN层形成欧姆接触。源电极和漏电极设置在未掺杂的AlGaN层上。通过在未掺杂的AlGaN层和未掺杂的GaN层和p型GaN层之间的界面处产生的二维电子气在栅极区域中形成pn结，从而可以提高栅极电压。

28. 发明申请

US20060157729A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060157729A1
公开(公告)日：2006-07-20
申请号：US11325340
申请日：2006-01-05
申请人： Hiroaki Ueno , Tetsuzo Ueda , Yasuhiro Uemoto , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara , Yutaka Hirose , Masahiro Hikita
发明人： Hiroaki Ueno , Tetsuzo Ueda , Yasuhiro Uemoto , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara , Yutaka Hirose , Masahiro Hikita
IPC分类号： H01L33/00
CPC分类号： H01L29/7786 , H01L29/2003
摘要： It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform. An insulating film 18 with a dielectric constant higher than that of the barrier layer is further inserted between a gate electrode 16 and the barrier layers 13, so that an improvement in gm and a reduction in gate leakage current can be achieved.
摘要翻译：本发明的一个目的是提供一种半导体器件，其可以同时实现HFET的常闭模式和改进的最大值，并进一步实现gm的改善和栅极漏电流的减小。为了在栅电极正下方的基板11的操作层12上保持薄势垒层13，主要用于实现常关模式并且还实现高I max，配置成使得栅极和源极区域之间以及栅极和漏极区域之间的半导体层17可以增加阻挡层13的厚度。因此与阻挡层的厚度被设计为均匀的FET相比，可以实现常关模式和I 的改善。介电常数高于阻挡层的绝缘膜18进一步插入在栅电极16和阻挡层13之间，从而改善gm和栅泄漏电流的降低可以实现。

29. 发明申请

US20060060895A1 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060060895A1
公开(公告)日：2006-03-23
申请号：US11193417
申请日：2005-08-01
申请人： Masahiro Hikita , Hiroaki Ueno , Yutaka Hirose , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Masahiro Hikita , Hiroaki Ueno , Yutaka Hirose , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H01L31/112 , H01L29/20 , H01L29/80
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/402 , H01L29/4175
摘要： In the structure of a semiconductor device of the present invention, a first source electrode is connected to a conductive substrate through a via hole, and a second source electrode is formed. Thus, even if a high reverse voltage is applied between a gate electrode and a drain electrode, electric field concentration likely to occur at an edge of the gate electrode closer to the drain electrode can be effectively dispersed or relaxed. Moreover, the conductive substrate is used as a substrate for forming element formation layers, so that a via hole penetrating the substrate to reach the backside thereof does not have to be formed in the conductive substrate. Thus, with the strength necessary for the conductive substrate maintained, the first source electrode can be electrically connected to a backside electrode.
摘要翻译：在本发明的半导体器件的结构中，第一源极通过通孔与导电性基板连接，形成第二源电极。因此，即使在栅电极和漏极之间施加高的反向电压，也可以有效地分散或放松在栅电极的靠近漏电极的边缘处可能发生的电场集中。此外，导电性基板用作形成元件形成层的基板，从而不必在导电性基板上形成贯穿基板到达其背面的通路孔。因此，由于保持导电基板所需的强度，第一源电极可以电连接到背面电极。

30. 发明授权

US08164115B2 Nitride semiconductor device 有权
标题翻译：氮化物半导体器件
公开(公告)号：US08164115B2
公开(公告)日：2012-04-24
申请号：US13010238
申请日：2011-01-20
申请人： Masahiro Hikita , Tetsuzo Ueda , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Masahiro Hikita , Tetsuzo Ueda , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H01L21/337 , H01L21/335
CPC分类号： H01L29/7786 , H01L29/1066 , H01L29/2003 , H01L29/4175 , H01L29/432 , H01L29/66462
摘要： A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer formed over the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a larger band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and including a p-type nitride semiconductor with at least a single-layer structure; a gate electrode formed on the third nitride semiconductor layer; and a source electrode and a drain electrode formed in regions located on both sides of the gate electrode, respectively. The third nitride semiconductor layer has a thickness greater in a portion below the gate electrode than in a portion below the side of the gate electrode.
摘要翻译：氮化物半导体器件包括：衬底; 形成在所述基板上的第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更大的带隙能量的第二氮化物半导体层; 形成在所述第二氮化物半导体层上并且包括具有至少单层结构的p型氮化物半导体的第三氮化物半导体层; 形成在所述第三氮化物半导体层上的栅电极; 以及分别形成在位于栅电极两侧的区域中的源电极和漏电极。所述第三氮化物半导体层的厚度比所述栅极电极侧的部分的厚度大。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式