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21. 发明申请

US20100281202A1 WEAR-LEVELING AND BAD BLOCK MANAGEMENT OF LIMITED LIFETIME MEMORY DEVICES 有权
标题翻译：有限寿命内存设备的磨损和边框管理
公开(公告)号：US20100281202A1
公开(公告)日：2010-11-04
申请号：US12433220
申请日：2009-04-30
申请人： Bulent Abali , John P. Karidis , Luis A. Lastras-Montano
发明人： Bulent Abali , John P. Karidis , Luis A. Lastras-Montano
IPC分类号： G06F12/00 , G06F11/20 , G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7211 , G11C16/349 , G11C16/3495 , G11C29/76 , G11C29/82
摘要： Performing wear-leveling and bad block management of limited lifetime memory devices. A method for performing wear-leveling in a memory includes receiving logical memory addresses and applying a randomizing function to the logical memory addresses to generate intermediate addresses within a range of intermediate addresses. The intermediate addresses are mapped into physical addresses of a memory using an algebraic mapping. The physical addresses are within a range of physical addresses that include at least one more location than the range of intermediate addresses. The physical addresses are output for use in accessing the memory. The mapping between the intermediate addresses and the physical addresses is periodically shifted. In addition, contents of bad blocks are replaced with redundantly encoded redirection addresses.
摘要翻译：执行有限寿命内存设备的磨损均衡和坏块管理。用于在存储器中执行磨损均衡的方法包括接收逻辑存储器地址并将随机化功能应用于逻辑存储器地址以在中间地址的范围内生成中间地址。使用代数映射将中间地址映射到存储器的物理地址。物理地址在物理地址的范围内，其包括比中间地址的范围至少一个以上的位置。输出物理地址用于访问存储器。中间地址和物理地址之间的映射周期性地移位。此外，坏块的内容被替换为冗余编码的重定向地址。

22. 发明申请

US20120204071A1 WEAR-LEVELING AND BAD BLOCK MANAGEMENT OF LIMITED LIFETIME MEMORY DEVICES 有权
标题翻译：有限寿命内存设备的磨损和边框管理
公开(公告)号：US20120204071A1
公开(公告)日：2012-08-09
申请号：US13445172
申请日：2012-04-12
申请人： Bulent Abali , John P. Karidis , Luis A. Lastras-Montano
发明人： Bulent Abali , John P. Karidis , Luis A. Lastras-Montano
IPC分类号： G11C29/08 , G06F11/26
CPC分类号： G06F12/0246 , G06F2212/7211 , G11C16/349 , G11C16/3495 , G11C29/76 , G11C29/82
摘要： Performing wear-leveling and bad block management of limited lifetime memory devices. A method for performing wear-leveling in a memory includes receiving logical memory addresses and applying a randomizing function to the logical memory addresses to generate intermediate addresses within a range of intermediate addresses. The intermediate addresses are mapped into physical addresses of a memory using an algebraic mapping. The physical addresses are within a range of physical addresses that include at least one more location than the range of intermediate addresses. The physical addresses are output for use in accessing the memory. The mapping between the intermediate addresses and the physical addresses is periodically shifted. In addition, contents of bad blocks are replaced with redundantly encoded redirection addresses.
摘要翻译：执行有限寿命内存设备的磨损均衡和坏块管理。用于在存储器中执行磨损均衡的方法包括接收逻辑存储器地址并将随机化功能应用于逻辑存储器地址以在中间地址的范围内生成中间地址。使用代数映射将中间地址映射到存储器的物理地址。物理地址在物理地址的范围内，其包括比中间地址的范围至少一个以上的位置。输出物理地址用于访问存储器。中间地址和物理地址之间的映射周期性地移位。此外，坏块的内容被替换为冗余编码的重定向地址。

23. 发明申请

US20090254705A1 BUS ATTACHED COMPRESSED RANDOM ACCESS MEMORY 审中-公开
标题翻译：总线连接压缩随机存取存储器
公开(公告)号：US20090254705A1
公开(公告)日：2009-10-08
申请号：US12098900
申请日：2008-04-07
申请人： Bulent Abali , John P. Karidis , Luis A. Lastras-Montano
发明人： Bulent Abali , John P. Karidis , Luis A. Lastras-Montano
IPC分类号： G06F12/08
CPC分类号： G06F12/08 , G06F12/0897 , G06F2212/2022 , G06F2212/2024 , G06F2212/401
摘要： A computer memory system having a three-level memory hierarchy structure is disclosed. The system includes a memory controller, a volatile memory, and a non-volatile memory. The volatile memory is divided into an uncompressed data region and a compressed data region.
摘要翻译：公开了一种具有三级存储器层次结构的计算机存储器系统。该系统包括存储器控制器，易失性存储器和非易失性存储器。易失性存储器被分为未压缩数据区和压缩数据区。

24. 发明授权

US08861266B2 Planar phase-change memory cell with parallel electrical paths 有权
标题翻译：具有并联电路径的平面相变存储单元
公开(公告)号：US08861266B2
公开(公告)日：2014-10-14
申请号：US13619473
申请日：2012-09-14
申请人： Michele M. Franceschini , John P. Karidis
发明人： Michele M. Franceschini , John P. Karidis
IPC分类号： G11C11/00 , H01L45/00 , G11C8/10 , G11C11/56 , G11C13/00
CPC分类号： G11C8/10 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/1675
摘要： A method for operating a phase change memory that includes initializing a memory cell that includes: a first conductive electrode having a length greater than its width and an axis aligned with the length; a second conductive electrode having an edge oriented at an angle to the axis of the first conductive electrode; an insulator providing a separation distance between an end of the first conductive electrode and the edge of the second conductive electrode; and a phase change material covering a substantial portion of the first conductive electrode and at least a portion of the second conductive electrode. The initializing the memory cell includes creating a first amorphous material region in the phase change material. An active crystalline material region is created inside the first amorphous material region. Information is stored in the memory cell by creating a second amorphous material region inside the active crystalline material region.
摘要翻译：一种用于操作相变存储器的方法，包括初始化存储单元，所述存储单元包括：具有大于其宽度的长度的第一导电电极和与所述长度对准的轴线; 第二导电电极，其具有与第一导电电极的轴成一定角度的边缘; 绝缘体，其在所述第一导电电极的端部和所述第二导电电极的边缘之间提供间隔距离; 以及覆盖所述第一导电电极的主要部分和所述第二导电电极的至少一部分的相变材料。初始化存储单元包括在相变材料中形成第一非晶态材料区域。在第一无定形材料区域内形成活性结晶材料区域。通过在活性结晶材料区域内产生第二非晶态材料区域将信息存储在存储器单元中。

25. 发明授权

US08575008B2 Post-fabrication self-aligned initialization of integrated devices 有权
标题翻译：集成器件的后置自对准初始化
公开(公告)号：US08575008B2
公开(公告)日：2013-11-05
申请号：US12873058
申请日：2010-08-31
申请人： Michele M. Franceschini , John P. Karidis
发明人： Michele M. Franceschini , John P. Karidis
IPC分类号： H01L21/00
CPC分类号： H01L45/126 , H01L45/04 , H01L45/1226 , H01L45/144
摘要： Creating a localized region of material having a target chemical composition by defining an electrical circuit on a substrate, and depositing on the electrical circuit one or more layers of materials having one or more chemical compositions. An electrical current pulse is applied to the electrical circuit to create a self-aligned localized region having the target chemical composition. Applying the electrical current pulse causes a portion of the one or more layers of materials to be heated, resulting in the target chemical composition.
摘要翻译：通过在基板上限定电路来形成具有目标化学成分的材料的局部区域，以及在电路上沉积具有一种或多种化学成分的一层或多层材料。电流脉冲施加到电路以产生具有目标化学成分的自对准局部区域。施加电流脉冲导致一层或多层材料的一部分被加热，导致目标化学成分。

26. 发明授权

US08144508B2 Memory reading method for resistance drift mitigation 有权
标题翻译：电阻漂移缓解的记忆读取方法
公开(公告)号：US08144508B2
公开(公告)日：2012-03-27
申请号：US12984682
申请日：2011-01-05
申请人： Michele M. Franceschini , John P. Karidis , Luis A. Lastras
发明人： Michele M. Franceschini , John P. Karidis , Luis A. Lastras
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0033 , G11C2013/0052
摘要： Techniques for reading phase change memory that mitigate resistance drift. One contemplated method includes apply a plurality of electrical input signals to the memory cell. The method includes measuring a plurality of electrical output signals from the memory cell resulting from the plurality of electrical input signals. The method includes calculating an invariant component of the plurality of electrical output signals dependent on the configuration of amorphous material in the memory cell. The method also includes determining a memory state of the memory cell based on the invariant component. In one embodiment of the invention, the method further includes mapping the plurality of electrical output signals to a measurements region of a plurality of measurements regions. The measurements regions correspond to memory states of the memory cell.
摘要翻译：读取相变存储器的技术，减轻电阻漂移。一种预期的方法包括将多个电输入信号应用于存储器单元。该方法包括从多个电输入信号测量来自存储器单元的多个电输出信号。该方法包括根据存储单元中非晶材料的配置来计算多个电输出信号的不变分量。该方法还包括基于不变分量来确定存储器单元的存储器状态。在本发明的一个实施例中，该方法还包括将多个电输出信号映射到多个测量区域的测量区域。测量区域对应于存储器单元的存储器状态。

27. 发明申请

US20110317481A1 PLANAR PHASE-CHANGE MEMORY CELL WITH PARALLEL ELECTRICAL PATHS 有权
标题翻译：平面相变存储器单元并联电路
公开(公告)号：US20110317481A1
公开(公告)日：2011-12-29
申请号：US12823924
申请日：2010-06-25
申请人： Michele M. Franceschini , John P. Karidis
发明人： Michele M. Franceschini , John P. Karidis
IPC分类号： G11C11/00 , G06F17/50 , H01L45/00
CPC分类号： G11C8/10 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/1675
摘要： A planar phase change memory cell with parallel electrical paths. The memory cell includes a first conductive electrode region having a length greater than its width and an axis aligned with the length. The memory cell also includes a second conductive electrode region having an edge oriented at an angle to the axis of the first conductive electrode region. The memory cell further includes an insulator region providing a lateral separation distance between an end of the first conductive electrode region and the edge of the second conductive electrode region, the insulator region including at least part of an insulator film and the lateral separation distance is responsive to the thickness of the insulator film.
摘要翻译：具有并联电路径的平面相变存储单元。存储单元包括具有大于其宽度的长度的第一导电电极区域和与该长度对准的轴线。存储单元还包括具有与第一导电电极区域的轴成一定角度的边缘的第二导电电极区域。存储单元还包括绝缘体区域，其在第一导电电极区域的端部和第二导电电极区域的边缘之间提供横向间隔距离，绝缘体区域包括绝缘膜的至少一部分，并且横向间隔距离是响应的到绝缘膜的厚度。

28. 发明申请

US20130011993A1 PLANAR PHASE- CHANGE MEMORY CELL WITH PARALLEL ELECTRICAL PATHS 有权
标题翻译：平面相变记忆电池与并联电气
公开(公告)号：US20130011993A1
公开(公告)日：2013-01-10
申请号：US13619493
申请日：2012-09-14
申请人： Michele M. Franceschini , John P. Karidis
发明人： Michele M. Franceschini , John P. Karidis
IPC分类号： H01L21/02
CPC分类号： G11C8/10 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/1675
摘要： A method of manufacturing a phase change memory cell on a substrate. The method includes: etching a first trench in the substrate; depositing a first conductor layer in the first trench; depositing a first insulator layer over the first conductor layer in the first trench; etching a second trench in the substrate at an angle to the first trench; depositing a second insulator layer in the second trench; depositing a second conductor layer over the second insulator layer in the second trench; and depositing phase change material. The deposited phase change material is in contact with the first conductor layer and the second conductor layer.
摘要翻译：一种在衬底上制造相变存储单元的方法。该方法包括：蚀刻衬底中的第一沟槽; 在第一沟槽中沉积第一导体层; 在所述第一沟槽中的所述第一导体层上沉积第一绝缘体层; 以与第一沟槽成一定角度蚀刻衬底中的第二沟槽; 在所述第二沟槽中沉积第二绝缘体层; 在所述第二沟槽中的所述第二绝缘体层上沉积第二导体层; 并沉积相变材料。沉积的相变材料与第一导体层和第二导体层接触。

29. 发明授权

US08685785B2 Planar phase-change memory cell with parallel electrical paths 有权
标题翻译：具有并联电路径的平面相变存储单元
公开(公告)号：US08685785B2
公开(公告)日：2014-04-01
申请号：US13619493
申请日：2012-09-14
申请人： Michele M. Franceschini , John P. Karidis
发明人： Michele M. Franceschini , John P. Karidis
IPC分类号： H01L21/02
CPC分类号： G11C8/10 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/1675
摘要： A method of manufacturing a phase change memory cell on a substrate. The method includes: etching a first trench in the substrate; depositing a first conductor layer in the first trench; depositing a first insulator layer over the first conductor layer in the first trench; etching a second trench in the substrate at an angle to the first trench; depositing a second insulator layer in the second trench; depositing a second conductor layer over the second insulator layer in the second trench; and depositing phase change material. The deposited phase change material is in contact with the first conductor layer and the second conductor layer.
摘要翻译：一种在衬底上制造相变存储单元的方法。该方法包括：蚀刻衬底中的第一沟槽; 在第一沟槽中沉积第一导体层; 在所述第一沟槽中的所述第一导体层上沉积第一绝缘体层; 以与第一沟槽成一定角度蚀刻衬底中的第二沟槽; 在所述第二沟槽中沉积第二绝缘体层; 在所述第二沟槽中的所述第二绝缘体层上沉积第二导体层; 并沉积相变材料。沉积的相变材料与第一导体层和第二导体层接触。

30. 发明授权

US08624217B2 Planar phase-change memory cell with parallel electrical paths 有权
标题翻译：具有并联电路径的平面相变存储单元
公开(公告)号：US08624217B2
公开(公告)日：2014-01-07
申请号：US12823924
申请日：2010-06-25
申请人： Michele M. Franceschini , John P. Karidis
发明人： Michele M. Franceschini , John P. Karidis
IPC分类号： H01L29/06 , G11C11/00
CPC分类号： G11C8/10 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/1675
摘要： A planar phase change memory cell with parallel electrical paths. The memory cell includes a first conductive electrode region having a length greater than its width and an axis aligned with the length. The memory cell also includes a second conductive electrode region having an edge oriented at an angle to the axis of the first conductive electrode region. The memory cell further includes an insulator region providing a lateral separation distance between an end of the first conductive electrode region and the edge of the second conductive electrode region, the insulator region including at least part of an insulator film and the lateral separation distance is responsive to the thickness of the insulator film.
摘要翻译：具有并联电路径的平面相变存储单元。存储单元包括具有大于其宽度的长度的第一导电电极区域和与该长度对准的轴线。存储单元还包括具有与第一导电电极区域的轴成一定角度的边缘的第二导电电极区域。存储单元还包括绝缘体区域，其在第一导电电极区域的端部和第二导电电极区域的边缘之间提供横向间隔距离，绝缘体区域包括绝缘膜的至少一部分，并且横向间隔距离是响应的到绝缘膜的厚度。

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