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21. 发明授权

US5050072A Semaphore memory to reduce common bus contention to global memory with localized semaphores in a multiprocessor system 失效
标题翻译：信号量存储器，用于在多处理器系统中以局部信号量减少公共总线对全局内存的争用
公开(公告)号：US5050072A
公开(公告)日：1991-09-17
申请号：US207878
申请日：1988-06-17
申请人： William E. Earnshaw , Steven J. McKinney
发明人： William E. Earnshaw , Steven J. McKinney
IPC分类号： G06F9/46
CPC分类号： G06F9/52
摘要： The invention greatly reduces common bus contention by allowing the semaphore test bit and set operations to be performed on each CPU's local bus. The semaphore lock bits are stored locally in high speed SRAM on each CPU, and coherency of the lock bits is maintained through a bus monitoring logic circuit on each CPU. A CPU wishing to take possession of a semaphore performs a local read of its semaphore memory, and spins locally until the lock bit is reset at which time it performs a local write to set the bit. When the semaphore lock bit is written, it will be updated locally, and at the same time the write operation will be sent out over the common bus. The bus monitoring logic on every other CPU will recognize the write operation and simultaneously update the corresponding lock bit in each local semaphore memory. This ability to read spin locally relieves the common bus from the great amount of traffic that occurs in typical systems that maintain the semaphore lock bits in common global memory.
摘要翻译：本发明通过允许在每个CPU的本地总线上执行信号量测试位和设置操作来大大降低公共总线争用。信号量锁定位本地存储在每个CPU上的高速SRAM中，锁定位的一致性通过每个CPU上的总线监视逻辑电路进行维护。希望占据信号量的CPU会对其信号量存储器进行本地读取，并在本地进行旋转，直到锁定位复位，此时执行本地写操作即可设置该位。当信号量锁定位被写入时，它将在本地更新，同时写操作将通过公共总线发送出去。每个其他CPU上的总线监控逻辑将识别写入操作，并同时更新每个本地信号量存储器中的相应锁定位。在本地读取自旋的这种能力可以使公共总线从在通用全局存储器中维持信号量锁定位的典型系统中发生的大量流量中消除。

22. 发明授权

US4942575A Error connection device for parity protected memory systems 失效
标题翻译：奇偶校验存储器系统的错误连接设备
公开(公告)号：US4942575A
公开(公告)日：1990-07-17
申请号：US207874
申请日：1988-06-17
申请人： William E. Earnshaw , Jay Howell , Paul B. Ripy
发明人： William E. Earnshaw , Jay Howell , Paul B. Ripy
IPC分类号： G06F11/10 , G11C29/00
CPC分类号： G11C29/74 , G06F11/106
摘要： The use of a redundant memory subsystem, memory flow control, and a method of copying (srubbing) data from the location of one memory subsystem to the corresponding location in the other memory subsystem provides correction of soft errors in a parity protected memory system without degrading the performance of the memory system except when an error occurs. A copy of the correct data is also provided to the memory system when a location in either of the memory subsystems experiences a hard error.
摘要翻译：使用冗余存储器子系统，存储器流控制以及将数据从一个存储器子系统的位置复制（分配）到另一个存储器子系统中的相应位置的方法提供了校验保护存储器系统中的软错误而不降低内存系统的性能除了发生错误之外。当任何一个存储器子系统中的位置经历硬错误时，还将正确数据的副本提供给存储器系统。

23. 发明授权

US4924380A Dual rotating priority arbitration method for a multiprocessor memory bus 失效
标题翻译：用于多处理器存储器总线的双重旋转优先级仲裁方法
公开(公告)号：US4924380A
公开(公告)日：1990-05-08
申请号：US208506
申请日：1988-06-20
申请人： Steven J. McKinney , William E. Earnshaw
发明人： Steven J. McKinney , William E. Earnshaw
IPC分类号： G06F13/364
CPC分类号： G06F13/364
摘要： In a multiprocessor system with a common bus and a central arbitration controller, which samples the request status of every system agent, the arbitration controller grants bus accesses based on an arbitration scheme consisting of two rotating queues with a fixed priority between the queues.
摘要翻译：在具有公共总线和中央仲裁控制器的多处理器系统中，其对每个系统代理的请求状态进行采样，仲裁控制器基于由队列之间具有固定优先级的两个旋转队列组成的仲裁方案来授予总线访问。

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