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21. 发明授权

US07023528B2 Hybrid electronic mask 有权
标题翻译：混合电子面具
公开(公告)号：US07023528B2
公开(公告)日：2006-04-04
申请号：US10167327
申请日：2002-06-10
申请人： Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
发明人： Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
IPC分类号： G03B27/72 , G03B27/54 , G03B27/42
CPC分类号： G03F1/26 , G03F7/2014 , G03F7/70291
摘要： An electronically programmable mask for lithography has an array of individually controllable light sources aligned with an array of individually controllable liquid crystals, so that individual pixels may be turned on or off and phase-shifted to provide a desired light intensity distribution on a wafer. The mask may be used in a contact printing mode or in a reduction projection mode.
摘要翻译：用于光刻的电子可编程掩模具有与独立可控液晶阵列对准的独立可控光源的阵列，使得各个像素可以被导通或截止并相移以在晶片上提供期望的光强分布。掩模可以以接触印刷模式或缩小投影模式使用。

22. 发明授权

US06869846B2 Forming electronic structures having dual dielectric thicknesses and the structure so formed 失效
标题翻译：形成具有双介电厚度的电子结构和如此形成的结构
公开(公告)号：US06869846B2
公开(公告)日：2005-03-22
申请号：US10411850
申请日：2003-04-10
申请人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , Richard A. Strub , William R. Tonti
发明人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , Richard A. Strub , William R. Tonti
IPC分类号： H01L21/8239 , H01L21/334 , H01L21/8234 , H01L21/8242 , H01L29/94
CPC分类号： H01L29/66181 , H01L21/823462 , H01L27/10861 , H01L27/10894 , H01L29/945
摘要： A structure including a first device and a second device, wherein the second device has a dielectric thickness greater than the dielectric thickness of the first device, and the method of so forming the structure.
摘要翻译：一种包括第一装置和第二装置的结构，其中所述第二装置的电介质厚度大于所述第一装置的电介质厚度，以及形成所述结构的方法。

23. 发明授权

US06724029B2 Twin-cell flash memory structure and method 有权
标题翻译：双电池闪存结构及方法
公开(公告)号：US06724029B2
公开(公告)日：2004-04-20
申请号：US09683831
申请日：2002-02-21
申请人： Louis L. Hsu , Chung H. Lam , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Louis L. Hsu , Chung H. Lam , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L27108
CPC分类号： H01L27/11521 , G11C16/0441 , H01L27/115
摘要： A programmable memory cell structure that includes a pair of memory cells is provided. Each pair of memory cells includes a shared control gate and first and second floating gates present about the shared control gate. The first and second floating gates have respective gate regions disposed on respective sides of the control gate. Dielectric structures are present between the control gate and respective ones of the gate regions of the floating gates. The control gate and gates of the first and second floating gates are formed within a single lithographic square.
摘要翻译：提供了包括一对存储单元的可编程存储单元结构。每对存储单元包括共享控制栅极和围绕共享控制栅极存在的第一和第二浮动栅极。第一和第二浮栅具有设置在控制栅极的相应侧上的各自的栅极区域。电介质结构存在于控制栅极和浮动栅极的各个栅极区域之间。第一和第二浮动栅极的控制栅极和栅极形成在单个光刻平面内。

24. 发明授权

US06670234B2 Method of integrating volatile and non-volatile memory cells on the same substrate and a semiconductor memory device thereof 失效
标题翻译：将易失性和非易失性存储单元集成在同一衬底上的方法及其半导体存储器件
公开(公告)号：US06670234B2
公开(公告)日：2003-12-30
申请号：US09887403
申请日：2001-06-22
申请人： Louis L. Hsu , Carl J. Radens , Li-Kong Wang
发明人： Louis L. Hsu , Carl J. Radens , Li-Kong Wang
IPC分类号： H01L2100
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/1052 , H01L27/10861 , H01L27/10894 , H01L27/11546
摘要： A method for fabricating DRAM and flash memory cells on a single chip includes providing a silicon substrate, forming a trench capacitor for each of the DRAM cells in the silicon substrate, forming isolation regions in the silicon substrate which are electrically isolated from each other, forming first type wells for DRAM and flash memory cells at first predetermined regions of the silicon substrate by implanting a first type impurity in the first predetermined regions, forming second type wells for DRAM and flash memory cells at second predetermined regions in the first type wells by implanting a second type impurity in the second predetermined regions, forming oxide layers for DRAM and flash memory cells on the second type wells, forming gate electrodes for DRAM and flash memory cells on the oxide layers for DRAM and flash memory cells, and forming source and drain regions for DRAM and flash memory cells in the respective second type wells for DRAM and flash memory cells, in which the source and drain regions are associated with each of the gate electrodes for DRAM and flash memory cells.
摘要翻译：在单个芯片上制造DRAM和闪存单元的方法包括提供硅衬底，为硅衬底中的每个DRAM单元形成沟槽电容器，形成硅衬底中彼此电隔离的隔离区域，形成通过在第一预定区域中注入第一种类型的杂质，在第一种类型的阱中的第二预定区域形成用于DRAM和闪速存储单元的第二类型阱，通过植入在第二预定区域中形成第二类型杂质，在第二类型阱上形成用于DRAM和闪存单元的氧化物层，在DRAM和闪存单元的氧化物层上形成用于DRAM的闪存存储单元的栅电极，以及形成源极和漏极用于DRAM和闪速存储器单元的相应的第二类型阱中的用于DRAM和闪存单元的区域 e源极和漏极区域与用于DRAM和闪存单元的每个栅电极相关联。

25. 发明授权

US06566191B2 Forming electronic structures having dual dielectric thicknesses and the structure so formed 失效
公开(公告)号：US06566191B2
公开(公告)日：2003-05-20
申请号：US09731148
申请日：2000-12-05
申请人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , Richard A. Strub , William R. Tonti
发明人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , Richard A. Strub , William R. Tonti
IPC分类号： H01L218242
CPC分类号： H01L29/66181 , H01L21/823462 , H01L27/10861 , H01L27/10894 , H01L29/945
摘要： A structure including a first device and a second device, wherein the second device has a dielectric thickness greater than the dielectric thickness of the first device, and the method of so forming the structure.

26. 发明授权

US06541815B1 High-density dual-cell flash memory structure 失效
标题翻译：高密度双单元闪存结构
公开(公告)号：US06541815B1
公开(公告)日：2003-04-01
申请号：US09974968
申请日：2001-10-11
申请人： Jack A. Mandelman , Louis L. Hsu , Chung H. Lam , Carl J. Radens
发明人： Jack A. Mandelman , Louis L. Hsu , Chung H. Lam , Carl J. Radens
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/115 , H01L27/11556 , H01L29/7885
摘要： A 2F2 flash memory cell structure and a method of fabricating the same are provided. The 2F2 flash memory cell structure includes a Si-containing substrate having a plurality of trenches formed therein. Each trench has sidewalls that extend to a bottom wall, a length and individual segments that include two memory cell elements per segment. Each memory cell element comprises (i) a floating gate region having L-shaped gates formed on a portion of each trench sidewall; (ii) a program line overlapping one side of the L-shaped gates present at the bottom wall of each trench and extending along the entire length of the plurality of trenches; and (iii) a control gate region overlying the floating gate region. The control gate region includes gates formed on portions of the sidewalls of the trenches that are coupled to the floating gate regions. The memory cell structure further includes bitline diffusion regions formed in the Si-containing semiconductor substrate abutting each trench segment; and wordlines that lay orthogonal to the trenches. The wordlines are in contact with a top surface of each control gate region.
摘要翻译：提供了一种2F2闪存单元结构及其制造方法。 2F2闪存单元结构包括其中形成有多个沟槽的含Si衬底。每个沟槽具有延伸到底壁，长度和包括每个段的两个存储单元元件的单独段的侧壁。每个存储单元元件包括（i）具有形成在每个沟槽侧壁的一部分上的L形栅极的浮栅区域; （ii）重叠在每个沟槽的底壁处的L形门的一侧并沿多个沟槽的整个长度延伸的程序线; 和（iii）覆盖浮栅区域的控制栅极区域。控制栅极区域包括形成在沟槽的侧壁的与浮动栅极区域耦合的部分上的栅极。所述存储单元结构还包括形成在所述含Si半导体衬底中的位线邻接每个沟槽段的位线扩散区; 和与沟槽正交的字线。字线与每个控制栅极区域的顶表面接触。

27. 发明授权

US06509612B2 High dielectric constant materials as gate dielectrics (insulators) 失效
公开(公告)号：US06509612B2
公开(公告)日：2003-01-21
申请号：US09848431
申请日：2001-05-04
申请人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Joseph F. Shepard, Jr.
发明人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Joseph F. Shepard, Jr.
IPC分类号： H01L2976
CPC分类号： H01L21/28176 , H01L21/26506 , H01L21/26586 , H01L21/28194 , H01L29/512 , H01L29/517
摘要： A method and structure for a metal oxide semiconductor field effect transistor (MOSFET) includes patterning a gate stack (having a gate conductor layer and a gate dielectric) over a substrate and modifying the gate dielectric beneath the gate conductor, such that the gate dielectric has a central portion and modified dielectric regions adjacent the central portion. The modified dielectric regions have a lower dielectric constant than that of the gate dielectric and the central portion is shorter than the gate conductor.

28. 发明授权

US06452110B1 Patterning microelectronic features without using photoresists 失效
标题翻译：图案化微电子特征，而不使用光致抗蚀剂
公开(公告)号：US06452110B1
公开(公告)日：2002-09-17
申请号：US09897889
申请日：2001-07-05
申请人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Keith Kwong Hon Wong
发明人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Keith Kwong Hon Wong
IPC分类号： H05K109
CPC分类号： H05K3/02 , H01L21/288 , H01L21/32134 , H01L21/76885 , Y10T29/49155 , Y10T29/49156
摘要： A method and structure for producing metallic polymer conductor lines comprising of an alternative methodology to a traditional damascene approach, called a cloisonne or inverse damascene approach. The cloisonne approach comprises the steps of coating a photosensitive polymer such as pyrrole or aniline with a silver salt on a semiconductor substrate. Using standard photolithography and resist developing techniques, the conducting polymer is exposed to a wet chemical developer, removing a portion of the exposed conducting polymer region, leaving only conducting polymer lines on top of the substrate. Next, an insulating dielectric layer is deposited over the entire structure and a chemical mechanical polish planarization of the insulator is performed creating the conducting polymer lines. Included in another aspect of the invention is a method and structure for a self-planarizing interconnect material comprising a conductive polymer thereby reducing the number of processing steps relative to the prior art.
摘要翻译：一种用于生产金属聚合物导体线的方法和结构，其包括传统大马士革方法的替代方法，称为景泰蓝或逆大马士革方法。景泰蓝方法包括在半导体衬底上用银盐将光敏聚合物如吡咯或苯胺涂覆的步骤。使用标准光刻和抗蚀显影技术，将导电聚合物暴露于湿化学显影剂，除去暴露的导电聚合物区域的一部分，仅在基底顶部留下导电聚合物线。接下来，在整个结构上沉积绝缘电介质层，并进行绝缘体的化学机械抛光平面化，产生导电聚合物线。包括在本发明的另一方面中的是一种用于自平坦化互连材料的方法和结构，其包括导电聚合物，从而减少相对于现有技术的加工步骤的数量。

29. 发明授权

US06441421B1 High dielectric constant materials forming components of DRAM storage cells 失效
标题翻译：形成DRAM存储单元组件的高介电常数材料
公开(公告)号：US06441421B1
公开(公告)日：2002-08-27
申请号：US09858485
申请日：2001-05-17
申请人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Joseph F. Shepard, Jr.
发明人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Joseph F. Shepard, Jr.
IPC分类号： H01L27108
CPC分类号： H01L27/1085 , H01L27/10861 , H01L27/10867 , H01L27/10873 , H01L27/1203 , H01L28/55
摘要： A method and structure for simultaneously producing a dynamic random access memory device and associated transistor is disclosed. The method forms channel regions and capacitor openings in a substrate. Next, the invention deposits capacitor conductors in the capacitor openings. Then, the invention simultaneously forms a single insulator layer above the channel region and above the capacitor conductor. This single insulator layer comprises a capacitor node dielectric above the capacitor conductor and comprises a gate dielectric above the channel region.
摘要翻译：公开了一种用于同时产生动态随机存取存储器件和相关晶体管的方法和结构。该方法在衬底中形成通道区域和电容器开口。接下来，本发明在电容器开口中沉积电容器导体。然后，本发明同时在沟道区域上方和电容器导体之上形成单个绝缘体层。该单个绝缘体层包括在电容器导体上方的电容器节点电介质，并且在沟道区域上方包括栅极电介质。

30. 发明授权

US06274467B1 Dual work function gate conductors with self-aligned insulating cap 失效
标题翻译：具有自对准绝缘帽的双功能栅极导体
公开(公告)号：US06274467B1
公开(公告)日：2001-08-14
申请号：US09327080
申请日：1999-06-04
申请人： Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L2122
CPC分类号： H01L21/28035 , H01L21/28052 , H01L21/32155 , H01L21/823842
摘要： A dual work function gate conductor with a self-aligned insulating cap and method for forming the same is provided. Two diffusion regions are formed in a substrate and a gate stack is formed over the substrate between the diffusion regions. The gate stack includes a gate insulating layer formed on the substrate and a layer of polysilicon on top of the gate insulating layer. The polysilicon layer may be doped n-type remain intrinsic. A barrier layer is formed on top of the polysilicon layer and a dopant source layer is formed on top of the barrier layer. The barrier layer contains a p-type dopant. The gate stack is enclosed by an insulating cap so that a diffusion contact can be formed borderless to the gate. Activation of the dopant source layer to dope a polysilicon layer can be delayed until a desired time.
摘要翻译：提供一种具有自对准绝缘帽的双功能栅极导体及其形成方法。在衬底中形成两个扩散区域，并且在扩散区域之间的衬底上形成栅叠层。栅极堆叠包括形成在衬底上的栅极绝缘层和位于栅极绝缘层顶部的多晶硅层。多晶硅层可以掺杂n型保持固有。在多晶硅层的顶部形成阻挡层，并且在阻挡层的顶部上形成掺杂剂源层。阻挡层含有p型掺杂剂。栅极堆叠被绝缘盖封闭，使得扩散接触可以形成与栅极无边界。激发掺杂剂源层以掺杂多晶硅层可以被延迟到期望的时间。

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