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21. 发明授权

US08661229B2 Power efficient instruction prefetch mechanism 有权
标题翻译：高效的指令预取机制
公开(公告)号：US08661229B2
公开(公告)日：2014-02-25
申请号：US12434804
申请日：2009-05-04
申请人： Thomas Andrew Sartorius , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Michael Scott McIlvaine , Rodney Wayne Smith
发明人： Thomas Andrew Sartorius , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Michael Scott McIlvaine , Rodney Wayne Smith
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3844 , G06F9/3804
摘要： A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.
摘要翻译：处理器包括产生加权分支预测值的条件分支指令预测机制。对于弱加权预测，其倾向于比强加权预测不太准确，通过停止指令预取来节省与推测性填充和随后刷新高速缓存的功率相关联的功率。当流水线中评估分支条件并且已知实际的下一个地址时，指令获取继续。或者，可以从高速缓存中继续预取。为了避免基于错误预测的分支预取的指令移位良好的高速缓存数据，预取可以响应于在高速缓存未命中的情况下的弱加权预测而停止。

22. 发明授权

US08127114B2 System and method for executing instructions prior to an execution stage in a processor 有权
标题翻译：用于在处理器中的执行阶段之前执行指令的系统和方法
公开(公告)号：US08127114B2
公开(公告)日：2012-02-28
申请号：US11692685
申请日：2007-03-28
申请人： Kiran Ravi Seth , James Norris Dieffenderfer , Michael Scott McIlvaine , Nathan Samuel Nunamaker
发明人： Kiran Ravi Seth , James Norris Dieffenderfer , Michael Scott McIlvaine , Nathan Samuel Nunamaker
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F9/3885
摘要： A method of processing a plurality of instructions in multiple pipeline stages within a pipeline processor is disclosed. The method partially or wholly executes a stalled instruction in a pipeline stage that has a function other than instruction execution prior to the execution stage within the processor. Partially or wholly executing the instruction prior to the execution stage in the pipeline speeds up the execution of the instruction and allows the processor to more effectively utilize its resources, thus increasing the processor's efficiency.
摘要翻译：公开了一种在流水线处理器内的多个流水线级中处理多个指令的方法。该方法在流水线级中部分或全部地执行停止的指令，其在处理器内的执行阶段之前具有不同于指令执行的功能。在流水线执行阶段之前部分或全部执行指令可加速指令的执行，并允许处理器更有效地利用其资源，从而提高处理器的效率。

23. 发明授权

US07949861B2 Method and apparatus for managing instruction flushing in a microprocessor's instruction pipeline 有权
标题翻译：用于在微处理器指令管线中管理指令冲洗的方法和装置
公开(公告)号：US07949861B2
公开(公告)日：2011-05-24
申请号：US11149773
申请日：2005-06-10
申请人： Michael Scott McIlvaine , James Norris Dieffenderfer , Thomas Andrew Sartorius
发明人： Michael Scott McIlvaine , James Norris Dieffenderfer , Thomas Andrew Sartorius
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/3861 , G06F9/30072 , G06F9/3867 , G06F12/0855 , G06F12/0862 , G06F2212/6028
摘要： In one or more embodiments, a processor includes one or more circuits to flush instructions from an instruction pipeline on a selective basis responsive to detecting a branch misprediction, such that those instructions marked as being dependent on the branch instruction associated with the branch misprediction are flushed. Thus, the one or more circuits may be configured to mark instructions fetched into the processor's instruction pipeline(s) to indicate their branch prediction dependencies, directly or indirectly detect incorrect branch predictions, and directly or indirectly flush instructions in the instruction pipeline(s) that are marked as being dependent on an incorrect branch prediction.
摘要翻译：在一个或多个实施例中，处理器包括一个或多个电路，用于响应于检测到分支错误预测而选择性地刷新来自指令流水线的指令，使得标记为依赖于与分支错误预测相关联的分支指令的那些指令被刷新。因此，一个或多个电路可以被配置为标记被提取到处理器的指令流水线中以指示其分支预测依赖性的指令，直接或间接地检测不正确的分支预测，以及直接或间接地刷新指令流水线中的指令，被标记为依赖于不正确的分支预测。

24. 发明授权

US07624254B2 Segmented pipeline flushing for mispredicted branches 有权
标题翻译：分段管道冲洗错误预测的分支
公开(公告)号：US07624254B2
公开(公告)日：2009-11-24
申请号：US11626443
申请日：2007-01-24
申请人： Rodney Wayne Smith , James Norris Dieffenderfer , Michael Scott McIlvaine , Thomas Andrew Sartorius
发明人： Rodney Wayne Smith , James Norris Dieffenderfer , Michael Scott McIlvaine , Thomas Andrew Sartorius
IPC分类号： G06F9/38
CPC分类号： G06F9/384 , G06F9/3842 , G06F9/3863 , G06F9/3867
摘要： A processor pipeline is segmented into an upper portion—prior to instructions going out of program order—and one or more lower portions beyond the upper portion. The upper pipeline is flushed upon detecting that a branch instruction was mispredicted, minimizing the delay in fetching of instructions from the correct branch target address. The lower pipelines may continue execution until the mispredicted branch instruction confirms, at which time all uncommitted instructions are flushed from the lower pipelines. Existing exception pipeline flushing mechanisms may be utilized, by adding a mispredicted branch identifier, reducing the complexity and hardware cost of flushing the lower pipelines.
摘要翻译：处理器管线在分配给程序顺序之外的指令之前被分割成上部，并且超出上部的一个或多个下部。在检测到分支指令被错误预测时，上级流水线被刷新，从而使得从正确的分支目标地址获取指令的延迟最小化。较低的管道可以继续执行，直到错误预测的分支指令确认，此时所有未提交的指令都从较低管道冲洗。可以通过添加错误的分支标识符来减少冲洗下层管道的复杂性和硬件成本，来利用现有的异常流水线冲洗机制。

25. 发明申请

US20090210663A1 Power Efficient Instruction Prefetch Mechanism 有权
标题翻译：高效率指令预取机制
公开(公告)号：US20090210663A1
公开(公告)日：2009-08-20
申请号：US12434804
申请日：2009-05-04
申请人： Thomas Andrew Sartorius , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Michael Scott McIlvaine , Rodney Wayne Smith
发明人： Thomas Andrew Sartorius , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Michael Scott McIlvaine , Rodney Wayne Smith
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/3804
摘要： A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.
摘要翻译：处理器包括产生加权分支预测值的条件分支指令预测机制。对于弱加权预测，其倾向于比强加权预测不太准确，通过停止指令预取来节省与推测性填充和随后刷新高速缓存的功率相关联的功率。当流水线中评估分支条件并且已知实际的下一个地址时，指令获取继续。或者，可以从高速缓存中继续预取。为了避免基于错误预测的分支预取的指令移位良好的高速缓存数据，预取可以响应于在高速缓存未命中的情况下的弱加权预测而停止。

26. 发明授权

US07152155B2 System and method of correcting a branch misprediction 有权
标题翻译：校正分支错误预测的系统和方法
公开(公告)号：US07152155B2
公开(公告)日：2006-12-19
申请号：US11061981
申请日：2005-02-18
申请人： Michael Scott McIlvaine , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
发明人： Michael Scott McIlvaine , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3861
摘要： When a branch misprediction in a pipelined processor is discovered, if the mispredicted branch instruction is not the last uncommitted instruction in the pipelines, older uncommitted instructions are checked for dependency on a long latency operation. If one is discovered, all uncommitted instructions are flushed from the pipelines without waiting for the dependency to be resolved. The branch prediction is corrected, and the branch instruction and all flushed instructions older than the branch instruction are re-fetched and executed.
摘要翻译：当发现流水线处理器中的分支错误预测时，如果错误的分支指令不是管道中的最后一条未提交的指令，则会检查较长的未提交的指令对长时间延迟操作的依赖性。如果被发现，所有未提交的指令都将从管道中刷新，而不必等待解决依赖关系。纠正分支预测，并且重新获取并执行分支指令和比分支指令更早的所有刷新指令。

27. 发明授权

US08438371B2 Link stack repair of erroneous speculative update 有权
标题翻译：链接堆栈修复错误的推测更新
公开(公告)号：US08438371B2
公开(公告)日：2013-05-07
申请号：US13108227
申请日：2011-05-16
申请人： James Norris Dieffenderfer , Brian Michael Stempel , Rodney Wayne Smith
发明人： James Norris Dieffenderfer , Brian Michael Stempel , Rodney Wayne Smith
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3806 , G06F9/3861
摘要： Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining a count of the total number of uncommitted link stack write instructions in the pipeline, and a count of the number of uncommitted link stack write instructions ahead of each branch instruction. When a branch is evaluated and determined to have been mispredicted, the count associated with it is compared to the total count. A discrepancy indicates a link stack write instruction was speculatively issued into the pipeline after the mispredicted branch instruction, and pushed a link address onto the link stack. The prior link address is restored to the link stack from the link stack restore buffer.
摘要翻译：每当链接地址被写入链接堆栈时，链接堆栈条目的先前值被保存，并且在错误预测的分支之后推测地执行链路堆叠推送操作之后被还原到链路栈。通过维持流水线中未提交的链路堆栈写入指令的总数的计数以及每个分支指令之前的未提交的链路栈写入指令的数量的计数来检测该条件。当分支被评估并确定为被误判时，将与之相关联的计数与总计数进行比较。一个差异表示在错误预测的分支指令之后推测发布了一个链接堆栈写入指令，并将链路地址推送到链路堆栈上。链路堆栈恢复缓冲区中的链路栈恢复到先前的链路地址。

28. 发明授权

US08082428B2 Methods and system for resolving simultaneous predicted branch instructions 有权
标题翻译：解决同步预测分支指令的方法和系统
公开(公告)号：US08082428B2
公开(公告)日：2011-12-20
申请号：US12569365
申请日：2009-09-29
申请人： Rodney Wayne Smith , Brian Michael Stempel , James Norris Dieffenderfer , Thomas Andrew Sartorius
发明人： Rodney Wayne Smith , Brian Michael Stempel , James Norris Dieffenderfer , Thomas Andrew Sartorius
IPC分类号： G06F9/30 , G06F9/40 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/3885 , G06F9/30058 , G06F9/3844 , G06F9/3861
摘要： A method of resolving simultaneous branch predictions prior to validation of the predicted branch instruction is disclosed. The method includes processing two or more predicted branch instructions, with each predicted branch instruction having a predicted state and a corrected state. The method further includes selecting one of the corrected states. Should one of the predicted branch instructions be mispredicted, the selected corrected state is used to direct future instruction fetches.
摘要翻译：公开了一种在预测分支指令验证之前解决同步分支预测的方法。该方法包括处理两个或多个预测分支指令，每个预测分支指令具有预测状态和校正状态。该方法还包括选择一个校正状态。如果预测的分支指令之一被错误预测，则所选择的校正状态用于指示未来的指令提取。

29. 发明申请

US20090119485A1 Predecode Repair Cache For Instructions That Cross An Instruction Cache Line 有权
标题翻译：预编码修复缓存用于交叉指令缓存行的指令
公开(公告)号：US20090119485A1
公开(公告)日：2009-05-07
申请号：US11934108
申请日：2007-11-02
申请人： Rodney Wayne Smith , Brian Michael Stempel , David John Mandzak , James Norris Dieffenderfer
发明人： Rodney Wayne Smith , Brian Michael Stempel , David John Mandzak , James Norris Dieffenderfer
IPC分类号： G06F9/312
CPC分类号： G06F9/30152 , G06F9/3816 , G06F9/382
摘要： A predecode repair cache is described in a processor capable of fetching and executing variable length instructions having instructions of at least two lengths which may be mixed in a program. An instruction cache is operable to store in an instruction cache line instructions having at least a first length and a second length, the second length longer than the first length. A predecoder is operable to predecode instructions fetched from the instruction cache that have invalid predecode information to form repaired predecode information. A predecode repair cache is operable to store the repaired predecode information associated with instructions of the second length that span across two cache lines in the instruction cache. Methods for filling the predecode repair cache and for executing an instruction that spans across two cache lines are also described.
摘要翻译：在能够获取和执行具有至少两个可能在程序中混合的长度的指令的可变长度指令的处理器中描述了一个预解码修复高速缓存。指令高速缓存用于存储指令高速缓存行指令，该指令具有至少第一长度和第二长度，第二长度长于第一长度。预解码器可用于对具有无效预解码信息的指令高速缓存取出的指令进行预解码，以形成修复的预解码信息。预解码修复高速缓存可操作用于存储与跨越指令高速缓存中的两个高速缓存行的第二长度的指令相关联的修复的预解码信息。还描述了用于填充预解码修复高速缓存和用于执行跨越两个高速缓存行的指令的方法。

30. 发明申请

US20080109644A1 System and method for using a working global history register 有权
标题翻译：使用工作全球历史记录寄存器的系统和方法
公开(公告)号：US20080109644A1
公开(公告)日：2008-05-08
申请号：US11556244
申请日：2006-11-03
申请人： Brian Michael Stempel , James Norris Dieffenderfer , Thomas Andrew Sartorius , Rodney Wayne Smith
发明人： Brian Michael Stempel , James Norris Dieffenderfer , Thomas Andrew Sartorius , Rodney Wayne Smith
IPC分类号： G06F9/38
CPC分类号： G06F9/3848 , G06F9/3804 , G06F9/3806 , G06F9/3861
摘要： A method of processing branch history information is disclosed. The method retrieves branch instructions from an instruction cache and executes the branch instructions in a plurality of pipeline stages. The method verifies that a branch instruction has been identified. The method further receives branch history information during a first pipeline stage and loads the branch history information into a first register, wherein the first register. The method further loads the branch history information into the second register during the second pipeline stage.
摘要翻译：公开了处理分支历史信息的方法。该方法从指令高速缓存中检索分支指令，并在多个流水线级中执行分支指令。该方法验证分支指令已被识别。该方法还在第一流水线阶段期间接收分支历史信息，并将分支历史信息加载到第一寄存器中，其中第一寄存器。该方法在第二流水线阶段期间进一步将分支历史信息加载到第二寄存器中。

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