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21. 发明申请

US20080244571A1 VIRTUAL INTERRUPT PROCESSING IN A LAYERED VIRTUALIZATION ARCHITECTURE 有权
标题翻译：虚拟中断处理在层次化的虚拟化架构中
公开(公告)号：US20080244571A1
公开(公告)日：2008-10-02
申请号：US11694236
申请日：2007-03-30
申请人： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Dion Rodgers , Richard A. Uhlig , Lawrence O. Smith , Barry E. Huntley
发明人： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Dion Rodgers , Richard A. Uhlig , Lawrence O. Smith , Barry E. Huntley
IPC分类号： G06F9/455
CPC分类号： G06F9/45558 , G06F2009/45566
摘要： Embodiments of apparatuses, methods, and systems for processing virtual interrupts in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes virtual machine entry logic, recognition logic, and evaluation logic. The virtual machine entry logic is to transfer control of the apparatus from a host to a guest. The recognition logic is to recognize a virtual interrupt request. The evaluation logic is to determine whether to transfer control from the guest to an intervening monitor in response to the virtual interrupt request.
摘要翻译：公开了用于处理分层虚拟化架构中的虚拟中断的装置，方法和系统的实施例。在一个实施例中，装置包括虚拟机入口逻辑，识别逻辑和评估逻辑。虚拟机入口逻辑是将设备的控制从主机传送到访客。识别逻辑是识别虚拟中断请求。评估逻辑是确定是否响应于虚拟中断请求将控制从客户转移到中间监视器。

22. 发明申请

US20190095350A1 System, Apparatus And Method For Page Granular,Software Controlled Multiple Key Memory Encryption 审中-公开
公开(公告)号：US20190095350A1
公开(公告)日：2019-03-28
申请号：US15714217
申请日：2017-09-25
申请人： David M. Durham , Siddhartha Chhabra , Amy L. Santoni , Gilbert Neiger , Barry E. Huntley , Hormuzd M. Khosravi , Baiju V. Patel , Ravi L. Sahita , Gideon Gerzon , Ido Ouziel , Ioannis T. Schoinas , Rajesh M. Sankaran
发明人： David M. Durham , Siddhartha Chhabra , Amy L. Santoni , Gilbert Neiger , Barry E. Huntley , Hormuzd M. Khosravi , Baiju V. Patel , Ravi L. Sahita , Gideon Gerzon , Ido Ouziel , Ioannis T. Schoinas , Rajesh M. Sankaran
IPC分类号： G06F12/14 , G06F21/60 , G06F21/82 , G06F3/06
摘要： In one embodiment, a cryptographic circuit is adapted to receive a data line including at least an encrypted portion from a memory in response to a read request having a memory address from a first agent, obtain a key identifier for a key of the first agent from the data line, obtain the key using the key identifier, decrypt the at least encrypted portion of the data line using the key and send decrypted data of the at least encrypted portion of the data line to the first agent. Other embodiments are described and claimed.

23. 发明申请

US20160092673A1 HARDWARE SHADOW STACK SUPPORT FOR LEGACY GUESTS 有权
标题翻译：硬件阴影堆栈支持LEGACY GUESTS
公开(公告)号：US20160092673A1
公开(公告)日：2016-03-31
申请号：US14498075
申请日：2014-09-26
申请人： Michael LeMay , Barry E. Huntley
发明人： Michael LeMay , Barry E. Huntley
IPC分类号： G06F21/52 , G06F9/455
CPC分类号： G06F21/52 , G06F8/30 , G06F8/31 , G06F9/4484 , G06F9/45533 , G06F9/45558 , G06F11/3419 , G06F21/56 , G06F2009/45587
摘要： Technologies for shadow stack support for legacy guests include a computing device having a processor with shadow stack support. During execution of a call instruction, the processor determines whether a legacy stack pointer is within bounds and generates a virtual machine exit if the legacy stack pointer is out-of-bounds. If not out-of-bounds, the processor pushes a return address onto the legacy stack and onto a shadow stack protected by a hypervisor. During execution of a return instruction, the processor determines whether top return addresses of the legacy stack and the shadow stack match, and generates a virtual machine exit if the return addresses do not match. If the return addresses match, the processor pops the return addresses off of the legacy stack and off of the shadow stack. The stack out-of-bounds and the stack mismatch virtual machine exits may be handled by the hypervisor. Other embodiments are described and claimed.
摘要翻译：用于传统客户端的影子堆栈支持技术包括具有处理器的计算设备，该处理器具有阴影栈支持。在执行调用指令期间，处理器确定传统堆栈指针是否在边界内，如果传统堆栈指针超出边界，则会生成虚拟机退出。如果不是超出范围，处理器将返回地址推送到传统堆栈上，并将其保存到由管理程序保护的影子堆栈上。在执行返回指令期间，处理器确定传统堆栈和影子堆叠的顶部返回地址是否匹配，并且如果返回地址不匹配则生成虚拟机退出。如果返回地址匹配，处理器会将返回地址从传统堆栈中弹出并离开阴影栈。虚拟机管理程序可以处理堆栈超出范围和堆栈不匹配的虚拟机退出。描述和要求保护其他实施例。

24. 发明申请

US20130247040A1 VIRTUALIZATION EVENT PROCESSING IN A LAYERED VIRTUALIZATION ARCHITECTURE 审中-公开
公开(公告)号：US20130247040A1
公开(公告)日：2013-09-19
申请号：US13837526
申请日：2013-03-15
申请人： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Dion Rodgers , Richard A. Uhlig , Lawrence O. Smith , Barry E. Huntley
发明人： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Dion Rodgers , Richard A. Uhlig , Lawrence O. Smith , Barry E. Huntley
IPC分类号： G06F9/455
CPC分类号： G06F9/45533 , G06F9/3861 , G06F9/45545 , G06F9/4555 , G06F9/45558 , G06F9/4812 , G06F9/542 , G06F13/24 , G06F2009/45566
摘要： Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.

25. 发明授权

US08151264B2 Injecting virtualization events in a layered virtualization architecture 有权
标题翻译：在分层虚拟化架构中注入虚拟化事件
公开(公告)号：US08151264B2
公开(公告)日：2012-04-03
申请号：US11771806
申请日：2007-06-29
申请人： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Dion Rodgers , Barry E. Huntley , Lawrence O. Smith
发明人： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Dion Rodgers , Barry E. Huntley , Lawrence O. Smith
IPC分类号： G06F9/455
CPC分类号： G06F9/45558 , G06F2009/45566
摘要： Embodiments of apparatuses, methods, and systems for injecting virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes virtual machine entry logic, recognition logic, and evaluation logic. The virtual machine entry logic is to initiate a transfer of control of the apparatus from a host to a guest running on a virtual machine. The recognition logic is to recognize a request from the host to inject a virtualization event into the virtual machine. The evaluation logic is to identify an intervening monitor to handle the virtualization event.
摘要翻译：公开了用于在分层虚拟化架构中注入虚拟化事件的装置，方法和系统的实施例。在一个实施例中，装置包括虚拟机入口逻辑，识别逻辑和评估逻辑。虚拟机入口逻辑是启动将设备的控制从主机传送到在虚拟机上运行的客户端。识别逻辑是识别主机向虚拟机注入虚拟化事件的请求。评估逻辑是识别一个干预的监视器来处理虚拟化事件。

26. 发明申请

US20210382987A1 PROCESSOR EXTENSIONS TO PROTECT STACKS DURING RING TRANSITIONS 有权
公开(公告)号：US20210382987A1
公开(公告)日：2021-12-09
申请号：US17407035
申请日：2021-08-19
申请人： Vedvyas Shanbhogue , Jason W. Brandt , Ravi L. Sahita , Barry E. Huntley , Baiju V. Patel , Deepak K. Gupta
发明人： Vedvyas Shanbhogue , Jason W. Brandt , Ravi L. Sahita , Barry E. Huntley , Baiju V. Patel , Deepak K. Gupta
IPC分类号： G06F21/52 , G06F3/06 , G06F12/14 , G06F9/30 , G06F9/46
摘要： A processor implementing techniques for processor extensions to protect stacks during ring transitions is provided. In one embodiment, the processor includes a plurality of registers and a processor core, operatively coupled to the plurality of registers. The plurality of registers is used to store data used in privilege level transitions. Each register of the plurality of registers is associated with a privilege level. An indicator to change a first privilege level of a currently active application to a second privilege level is received. In view of the second privilege level, a shadow stack pointer (SSP) stored in a register of the plurality of registers is selected. The register is associated with the second privilege level. By using the SSP, a shadow stack for use by the processor at the second privilege level is identified.

27. 发明授权

US10515023B2 System for address mapping and translation protection 有权
公开(公告)号：US10515023B2
公开(公告)日：2019-12-24
申请号：US15088739
申请日：2016-04-01
申请人： Ravi L. Sahita , Gilbert Neiger , Vedvyas Shanbhogue , David M. Durham , Andrew V. Anderson , David A. Koufaty , Asit K. Mallick , Arumugam Thiyagarajah , Barry E. Huntley , Deepak K. Gupta , Michael Lemay , Joseph F. Cihula , Baiju V. Patel
发明人： Ravi L. Sahita , Gilbert Neiger , Vedvyas Shanbhogue , David M. Durham , Andrew V. Anderson , David A. Koufaty , Asit K. Mallick , Arumugam Thiyagarajah , Barry E. Huntley , Deepak K. Gupta , Michael Lemay , Joseph F. Cihula , Baiju V. Patel
IPC分类号： G06F12/00 , G06F12/14 , G06F12/1009 , G06F9/455 , G06F12/1027 , G06F21/78
摘要： This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.

28. 发明申请

US20180183796A1 ONBOARDING AND ACCOUNTING OF DEVICES INTO AN HPC FABRIC 审中-公开
公开(公告)号：US20180183796A1
公开(公告)日：2018-06-28
申请号：US15392379
申请日：2016-12-28
申请人： Ned M. Smith , Barry E. Huntley , Simon Red Hunt
发明人： Ned M. Smith , Barry E. Huntley , Simon Red Hunt
IPC分类号： H04L29/06 , H04L12/931 , H04L12/933 , H04L29/08
CPC分类号： H04L63/10 , H04L63/0428 , H04L67/10
摘要： A method to onboard a slave node to a high performance computing system that includes a fabric switch network that includes a fabric switch master and a group of slave nodes, wherein the fabric switch master is configured to route messages between slave nodes of the group comprising: receiving a fabric switch master address message, at an onboarding slave node, over an external network; providing an identification message, by the onboarding slave node, over the fabric switch network; receiving the identification message, at the fabric switch master, over the fabric switch network; providing the permission message, by the fabric switch master, over the fabric switch network; and receiving, a permission message, at the onboarding slave node, over the fabric switch network.

29. 发明申请

US20180181764A1 SYSTEM, APPARATUS AND METHOD FOR TRUSTED CHANNEL CREATION USING EXECUTE-ONLY CODE 审中-公开
公开(公告)号：US20180181764A1
公开(公告)日：2018-06-28
申请号：US15390846
申请日：2016-12-27
申请人： Barry E. Huntley
发明人： Barry E. Huntley
IPC分类号： G06F21/60 , G06F9/455
CPC分类号： G06F21/602 , G06F9/45558 , G06F21/606 , G06F2009/45587
摘要： In one embodiment, an apparatus includes a first virtual machine (VM) including an encryption logic to encrypt first information. The encryption logic may include a first code block stored in a first execute-only region of a memory to encrypt the first information with a first key provisioned by a trusted agent, the first key stored in the first code block. The apparatus may further include a second VM including a decryption logic to decrypt the first information, and a shared buffer to enable secure communication of the encrypted first information from the first VM to the second VM, without involvement of the trusted agent. Other embodiments are described and claimed.

30. 发明申请

US20160179665A1 CONTROL OF ENTRY INTO PROTECTED MEMORY VIEWS 有权
标题翻译：进入受保护的存储器视图的控制
公开(公告)号：US20160179665A1
公开(公告)日：2016-06-23
申请号：US14581730
申请日：2014-12-23
申请人： Michael LeMay , Ravi L. Sahita , Barry E. Huntley , David M. Durham , Vedvyas Shanbhogue
发明人： Michael LeMay , Ravi L. Sahita , Barry E. Huntley , David M. Durham , Vedvyas Shanbhogue
IPC分类号： G06F12/08 , G06F9/455
CPC分类号： G06F12/08 , G06F9/45558 , G06F12/1009 , G06F12/1491 , G06F21/79 , G06F2009/45583 , G06F2009/45591 , G06F2212/151 , G06F2212/657
摘要： Generally, this disclosure provides systems, devices, methods and computer readable media for controlled memory view switching. The system may include a memory module comprising a shared address space between a first memory view and a second memory view. The system may also include a virtual machine monitor (VMM) to maintain a list of Controlled View Switch (CVS) descriptors. The system may further include a processor to receive a memory view switch request and to execute an instruction to save processor state information and switch from the first memory view to the second memory view, wherein the second memory view is specified by an extended page table pointer (EPTP) provided by one of the CVS descriptors.
摘要翻译：通常，本公开提供了用于受控存储器视图切换的系统，设备，方法和计算机可读介质。该系统可以包括存储器模块，该存储器模块包括第一存储器视图和第二存储器视图之间的共享地址空间。该系统还可以包括维护受控视图切换（CVS）描述符的列表的虚拟机监视器（VMM）。该系统还可以包括处理器，用于接收存储器视图切换请求并且执行用于保存处理器状态信息并从第一存储器视图切换到第二存储器视图的指令，其中第二存储器视图由扩展页表指针（EPTP）由其中一个CVS描述符提供。

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