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21. 发明申请

US20140195817A1 THREE INPUT OPERAND VECTOR ADD INSTRUCTION THAT DOES NOT RAISE ARITHMETIC FLAGS FOR CRYPTOGRAPHIC APPLICATIONS 审中-公开
标题翻译：三个输入操作向量添加指令，不提供用于CRYPTOAPHAPH应用的算术标记
公开(公告)号：US20140195817A1
公开(公告)日：2014-07-10
申请号：US13996527
申请日：2011-12-23
申请人： Wajdi K. Feghali , Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Gilbert M. Wolrich , Kirk S. Yap , Sean M. Gulley , Martin G. Dixon
发明人： Wajdi K. Feghali , Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Gilbert M. Wolrich , Kirk S. Yap , Sean M. Gulley , Martin G. Dixon
IPC分类号： G06F21/60 , G06F9/30
CPC分类号： G06F21/602 , G06F9/30007 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/30181
摘要： A method is described that includes performing the following within an instruction execution pipeline implemented on a semiconductor chip: summing three input vector operands through execution of a single instruction; and, not raising any arithmetic flags even though a result of the summing creates more bits than circuitry designed to transport the summation is able to transport.
摘要翻译：描述了一种方法，其包括在半导体芯片上实现的指令执行流水线内执行以下操作：通过执行单个指令对三个输入向量操作数相加; 并且，即使求和的结果产生比设计用于传送求和的电路更多的位能够传输，也不会提高任何算术标记。

22. 发明申请

US20140053000A1 INSTRUCTIONS TO PERFORM JH CRYPTOGRAPHIC HASHING 有权
标题翻译：执行JH CRYPTOGRAPHIC HASHING的指示
公开(公告)号：US20140053000A1
公开(公告)日：2014-02-20
申请号：US13992225
申请日：2011-12-22
申请人： Kirk S. Yap , Gilbert M. Wolrich , Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
发明人： Kirk S. Yap , Gilbert M. Wolrich , Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
IPC分类号： G06F21/64
CPC分类号： G06F21/64 , H04L9/0643 , H04L2209/12
摘要： A method is described. The method includes executing one or more JH_SBOX_L instruction to perform S-Box mappings and a linear (L) transformation on a JH state and executing one or more JH_Permute instruction to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed
摘要翻译：描述了一种方法。该方法包括在JH状态下执行一个或多个JH_SBOX_L指令来执行S-Box映射和线性（L）变换，并且一旦S-Box映射和 L变换

23. 发明申请

US20140019693A1 PARALLEL PROCESSING OF A SINGLE DATA BUFFER 审中-公开
标题翻译：单个数据缓冲器的并行处理
公开(公告)号：US20140019693A1
公开(公告)日：2014-01-16
申请号：US13631761
申请日：2012-09-28
申请人： Sean M. Gulley , Wajdi K. Feghali , Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Kirk S. Yap
发明人： Sean M. Gulley , Wajdi K. Feghali , Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Kirk S. Yap
IPC分类号： G06F12/00
CPC分类号： G06F5/06 , G06F21/64 , H04L9/0643 , H04L9/3236 , H04L2209/12 , H04L2209/20
摘要： Technologies for executing a serial data processing algorithm on a single variable length data buffer includes streaming segments of the buffer into a data register, executing the algorithm on each of the segments in parallel, and combining the results of executing the algorithm on each of the segments to form the output of the serial data processing algorithm.
摘要翻译：用于在单个可变长度数据缓冲器上执行串行数据处理算法的技术包括缓冲器的流片段到数据寄存器中，并行地对每个片段执行算法，并且在每个片段上合并执行算法的结果形成串行数据处理算法的输出。

24. 发明申请

US20150098563A1 Generating Multiple Secure Hashes from a Single Data Buffer 有权
标题翻译：从单个数据缓冲区生成多个安全哈希
公开(公告)号：US20150098563A1
公开(公告)日：2015-04-09
申请号：US14050326
申请日：2013-10-09
申请人： Sean M. Gulley , Vinodh Gopal , Wajdi K. Feghali , James D. Guilford , Gilbert M. Wolrich , Kirk S. Yap
发明人： Sean M. Gulley , Vinodh Gopal , Wajdi K. Feghali , James D. Guilford , Gilbert M. Wolrich , Kirk S. Yap
IPC分类号： H04L9/06
CPC分类号： H04L9/0643 , G06F9/30007 , G06F21/72 , H04L9/3242 , H04L2209/12 , H04L2209/125 , H04L2209/20
摘要： One embodiment provides an apparatus. The apparatus includes a single instruction multiple data (SIMD) hash module configured to apportion at least a first portion of a message of length L to a number (S) of segments, the message including a plurality of sequences of data elements, each sequence including S data elements, a respective data element in each sequence apportioned to a respective segment, each segment including a number N of blocks of data elements and to hash the S segments in parallel, resulting in S segment digests, the S hash digests based, at least in part, on an initial value and to store the S hash digests; a padding module configured to pad a remainder, the remainder corresponding to a second portion of the message, the second portion related to the length L of the message, the number of segments and a block size; and a non-SIMD hash module configured to hash the padded remainder, resulting in an additional hash digest and to store the additional hash digest.
摘要翻译：一个实施例提供了一种装置。该装置包括单个指令多数据（SIMD）散列模块，其被配置为将长度为L的消息的至少第一部分分配给数量（S）个段，该消息包括多个数据元素序列，每个序列包括 S个数据元素，分配给相应段的每个序列中的相应数据元素，每个段包括N个数据元素块，并且并行地对S个段进行散列，导致S段摘要，基于S个散列摘要至少部分地在初始值上存储S哈希摘要; 填充模块，被配置为填补余数，剩余部分对应于消息的第二部分，与消息的长度L相关的第二部分，段的数量和块大小; 以及非SIMD散列模块，被配置为对填充的余数进行散列，产生附加的散列摘要并存储附加散列摘要。

25. 发明授权

US09092645B2 Efficient multiplication, exponentiation and modular reduction implementations 有权
标题翻译：有效的乘法，乘法和模块化削减实现
公开(公告)号：US09092645B2
公开(公告)日：2015-07-28
申请号：US13994782
申请日：2011-12-05
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Deniz Karakoyunlu , Martin G. Dixon , Kahraman D. Akdemir
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Deniz Karakoyunlu , Martin G. Dixon , Kahraman D. Akdemir
IPC分类号： H04L29/00 , G06F21/71 , H04L9/30
CPC分类号： G06F21/71 , G06F7/723 , H04L9/3006 , H04L2209/12
摘要： In one embodiment, the present disclosure provides a method that includes segmenting an n-bit exponent e into a first segment et and a number t of k-bit segments ei in response to a request to determine a modular exponentiation result R, wherein R is a modular exponentiation of a generator base g for the exponent e and a q-bit modulus m, wherein the generator base g equals two and k is based at least in part on a processor configured to determine the result R; iteratively determining a respective intermediate modular exponentiation result for each segment ei, wherein the determining comprises multiplication, exponentiation and a modular reduction of at least one of a multiplication result and an exponentiation result; and generating the modular exponentiation result R=ge mod m based on, at least in part, at least one respective intermediate modular exponentiation result.
摘要翻译：在一个实施例中，本公开提供了一种方法，其包括响应于确定模幂运算结果R的请求，将n位指数e分割成第一段et和数目t的k比特段ei，其中R是指数e的发生器基数g和q位模数m的模幂运算，其中发生器基g等于2，并且k至少部分地基于被配置为确定结果R的处理器; 迭代地确定每个段ei的相应的中间模幂运算结果，其中所述确定包括相乘结果和求幂结果中的至少一个的乘法，乘法和模块化减少; 并且至少部分地基于至少一个相应的中间模幂运算结果来产生模幂运算结果R = ge mod m。

26. 发明申请

US20100332578A1 Method and apparatus for performing efficient side-channel attack resistant reduction 有权
标题翻译：用于执行有效的侧信道抗攻击降低的方法和装置
公开(公告)号：US20100332578A1
公开(公告)日：2010-12-30
申请号：US12459152
申请日：2009-06-26
申请人： Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Erdinc Ozturk , Martin G. Dixon
发明人： Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Erdinc Ozturk , Martin G. Dixon
IPC分类号： G06F7/52 , G06F12/08 , G06F7/50 , H04L9/30
CPC分类号： G06F7/72 , G06F12/0802 , G06F12/14 , G06F2207/7261
摘要： A time-invariant method and apparatus for performing modular reduction that is protected against cache-based and branch-based attacks is provided. The modular reduction technique adds no performance penalty and is side-channel resistant. The side-channel resistance is provided through the use of lazy evaluation of carry bits, elimination of data-dependent branches and use of even cache accesses for all memory references.
摘要翻译：提供了一种用于执行防止基于高速缓存和基于分支的攻击的模块化降级的时不变方法和装置。模块化还原技术不会增加性能损失，并且具有侧向通道阻抗。通过使用进位位的惰性评估，消除数据相关分支以及对所有存储器引用使用甚至高速缓存访问来提供侧向通道电阻。

27. 发明授权

US08504807B2 Rotate instructions that complete execution without reading carry flag 有权
公开(公告)号：US08504807B2
公开(公告)日：2013-08-06
申请号：US12655213
申请日：2009-12-26
申请人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Bret L. Toll , Maxim Loktyukhin , Mark C. Davis , Alexandre J. Farcy
发明人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Bret L. Toll , Maxim Loktyukhin , Mark C. Davis , Alexandre J. Farcy
IPC分类号： G06F9/00
CPC分类号： G06F9/30032 , G06F9/30094 , G06F9/30098
摘要： A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

28. 发明授权

US08392494B2 Method and apparatus for performing efficient side-channel attack resistant reduction using montgomery or barrett reduction 有权
标题翻译：使用montgomery或barrett还原来执行有效的侧信道攻击抗拒降低的方法和装置
公开(公告)号：US08392494B2
公开(公告)日：2013-03-05
申请号：US12459152
申请日：2009-06-26
申请人： Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Erdinc Ozturk , Martin G. Dixon
发明人： Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Erdinc Ozturk , Martin G. Dixon
IPC分类号： G06F7/52 , G06F17/30
CPC分类号： G06F7/72 , G06F12/0802 , G06F12/14 , G06F2207/7261
摘要： A time-invariant method and apparatus for performing modular reduction that is protected against cache-based and branch-based attacks is provided. The modular reduction technique adds no performance penalty and is side-channel resistant. The side-channel resistance is provided through the use of lazy evaluation of carry bits, elimination of data-dependent branches and use of even cache accesses for all memory references.
摘要翻译：提供了一种用于执行防止基于高速缓存和基于分支的攻击的模块化降级的时不变方法和装置。模块化还原技术不会增加性能损失，并且具有侧向通道阻抗。通过使用进位位的惰性评估，消除数据相关分支以及对所有存储器引用使用甚至高速缓存访问来提供侧向通道电阻。

29. 发明申请

US20110153993A1 Add Instructions to Add Three Source Operands 有权
标题翻译：添加说明来添加三个源操作数
公开(公告)号：US20110153993A1
公开(公告)日：2011-06-23
申请号：US12645334
申请日：2009-12-22
申请人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Bret L. Toll , Maxim Loktyukhin , Mark C. Davis , Alexandre J. Farcy
发明人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Bret L. Toll , Maxim Loktyukhin , Mark C. Davis , Alexandre J. Farcy
IPC分类号： G06F9/302
CPC分类号： G06F9/3001 , G06F9/30094
摘要： A method in one aspect may include receiving an add instruction. The add instruction may indicate a first source operand, a second source operand, and a third source operand. A sum of the first, second, and third source operands may be stored as a result of the add instruction. The sum may be stored partly in a destination operand indicated by the add instruction and partly a plurality of flags. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.
摘要翻译：一方面的方法可以包括接收添加指令。加法指令可以指示第一源操作数，第二源操作数和第三源操作数。作为加法指令的结果，可以存储第一，第二和第三源操作数的总和。该和可以部分地存储在由加法指令指示的目的地操作数中，部分地存储在多个标志中。还公开了其它方法，以及机器可读介质上的装置，系统和指令。

30. 发明授权

US11080045B2 Addition instructions with independent carry chains 有权
公开(公告)号：US11080045B2
公开(公告)日：2021-08-03
申请号：US13993483
申请日：2011-12-22
申请人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Matthew C. Merten , Tong Li , Bret T. Toll, I
发明人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Matthew C. Merten , Tong Li , Bret T. Toll, I
IPC分类号： G06F9/30 , G06F9/38
摘要： A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.

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