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21. 发明授权

US5166553A Current mirror circuit employing depletion mode FETs 失效
标题翻译：采用耗尽型FET的电流镜电路
公开(公告)号：US5166553A
公开(公告)日：1992-11-24
申请号：US364461
申请日：1989-06-12
申请人： Nobuo Kotera , Kiichi Yamashita , Hirotoshi Tanaka , Satoshi Tanaka , Yasushi Hatta , Minoru Nagata
发明人： Nobuo Kotera , Kiichi Yamashita , Hirotoshi Tanaka , Satoshi Tanaka , Yasushi Hatta , Minoru Nagata
IPC分类号： G05F3/24 , G05F3/26 , H03F3/34 , H03F3/343 , H03F3/347 , H03K17/14
CPC分类号： H03K17/145 , G05F3/262
摘要： A semiconductor circuit including first and second FET's for delivering an output signal without being affected by a change in threshold voltage of the FET's is disclosed. According to one practical form of the semiconductor circuit, the drain-source current path of an additional FET whose gate and source are shorted to each other, is connected in parallel to the drain-source current path of the first FET whose gate and drain are shorted to each other, to make the voltage-current characteristic of the second FET agree with that of the parallel combination of the first and additional FET's. According to another practical form of the semiconductor circuit, a voltage dividing circuit is connected in parallel to the drain-source current path of the first FET, and a divided output voltage from the voltage dividing circuit is applied between the gate and source of each of the first and second FET's.
摘要翻译：公开了一种包括用于传递输出信号而不受FET的阈值电压变化影响的第一和第二FET的半导体电路。根据半导体电路的一种实际形式，其栅极和源极彼此短路的附加FET的漏极 - 源极电流路径并联连接到栅极和漏极的第一FET的漏极 - 源极电流路径使第二FET的电压 - 电流特性与第一和另外的FET的并联组合一致。根据半导体电路的另一种实际形式，分压电路并联连接到第一FET的漏极 - 源极电流路径，并且来自分压电路的分压输出电压施加在每个的栅极和源极之间第一和第二FET。

22. 发明授权

US4847550A Semiconductor circuit 失效
标题翻译：半导体电路
公开(公告)号：US4847550A
公开(公告)日：1989-07-11
申请号：US143802
申请日：1988-01-14
申请人： Satoshi Tanaka , Hirotoshi Tanaka , Taizo Kinoshita , Nobuo Kotera , Minoru Nagata , Kiichi Yamashita , Tomoyuki Watanabe
发明人： Satoshi Tanaka , Hirotoshi Tanaka , Taizo Kinoshita , Nobuo Kotera , Minoru Nagata , Kiichi Yamashita , Tomoyuki Watanabe
IPC分类号： G05F3/24
CPC分类号： G05F3/245 , G05F3/247
摘要： A constant voltage circuit according to this invention comprises first means attenuating or dividing fluctuating voltage and an amplifying FET, to the gate of which the output attenuated or divided by the first means is applied and whose drain is connected with the fluctuating voltage through load means. The attenuation ratio or division ratio of the first means, the mutual conductance of the amplifying FET and the impedance of the load means are so set that the voltage drop across the load means cancels the fluctuating amount of the fluctuating voltage. Consequently an output voltage, which is maintained substantially constant, is obtained at the drain of the amplifying FET, independently of fluctuations in the fluctuating voltage, and thus a constant voltage circuit can be obtained. A constant current circuit according to this invention utilizes the constant voltage circuit described above. The output voltage of the constant voltage circuit is supplied to the gate of the constant current FET. Consequently a current, which is maintained substantially constant, flows through the drain-source path of this constant current FET and thus a constant current circuit can be obtained.

23. 发明授权

US4701719A Differential amplification circuit 失效
标题翻译：差分放大电路
公开(公告)号：US4701719A
公开(公告)日：1987-10-20
申请号：US883724
申请日：1986-07-09
申请人： Minoru Nagata
发明人： Minoru Nagata
IPC分类号： H03F3/45
CPC分类号： H03F3/45511 , H03F3/45085 , H03F3/45502 , H03F2203/45392 , H03F2203/45402 , H03F2203/45418 , H03F2203/45424 , H03F2203/45702
摘要： A first differential amplifier amplifies the differential signal component of the input signal supplied to input terminals. The differential component is then supplied to output terminals. The first differential amplifier comprises a first differential pair of transistors for producing a differential output current proportional to the input signal, and two load impedance elements connected to the outputs of the transistors of the first differential pair, for converting the output current to a voltage output. A current source is coupled to both load impedance elements. The in-phase component provided at the output terminals is detected by a detector circuit. A second differential amplifier detects the difference between the in-phase component and a reference value. This difference changes the output current of the current source, thereby controlling the in-phase component.
摘要翻译：第一差分放大器放大提供给输入端的输入信号的差分信号分量。然后将差分分量提供给输出端。第一差分放大器包括用于产生与输入信号成比例的差分输出电流的第一差分对晶体管和连接到第一差分对的晶体管的输出的两个负载阻抗元件，用于将输出电流转换为电压输出。电流源耦合到两个负载阻抗元件。在输出端子处提供的同相分量由检测器电路检测。第二差分放大器检测同相分量和参考值之间的差异。该差异改变了电流源的输出电流，从而控制了同相分量。

24. 发明授权

US4317055A High-voltage circuit for insulated gate field-effect transistor 失效
标题翻译：绝缘栅场效应晶体管高压电路
公开(公告)号：US4317055A
公开(公告)日：1982-02-23
申请号：US36972
申请日：1979-05-08
申请人： Isao Yoshida , Minoru Nagata , Shikayuki Ochi , Hisao Katto
发明人： Isao Yoshida , Minoru Nagata , Shikayuki Ochi , Hisao Katto
IPC分类号： H03F3/345 , H03F1/22 , H03F3/34 , H03F3/42 , H03K3/353 , H01L29/78 , H03F3/16 , H03K17/687
CPC分类号： H03K17/567 , H03F1/22 , H03F1/223 , H03F3/42 , H03F3/423 , H01L2924/0002
摘要： A high-voltage circuit for insulated gate field-effect transistors (MOSFETs) is provided wherein two MOSFETs are connected in series, the source and gate of the first MOSFET being respectively used as a source terminal and gate terminal of the high-voltage circuit, the drain of the second MOSFET being used as a drain terminal of the circuit. First and second resistors are connected in series between the source terminal and the drain terminal, and a biasing voltage supply is connected between the juncture of both the resistors and the gate of the second MOSFET. By virtue of these connections the "on" resistance of the high-voltage circuit is improved due to the effect of the biasing voltage effect in bringing the second MOSFET into an "on" condition.
摘要翻译：提供了一种用于绝缘栅场效应晶体管（MOSFET）的高电压电路，其中两个MOSFET串联连接，第一MOSFET的源极和栅极分别用作高压电路的源极端子和栅极端子，第二MOSFET的漏极用作电路的漏极端子。第一和第二电阻器串联在源极端子和漏极端子之间，偏置电压源连接在两个电阻器和第二个MOSFET的栅极之间。由于这些连接，由于在使第二MOSFET处于“导通”状态时偏置电压效应的影响，高压电路的“导通”电阻得到改善。

25. 发明授权

US08427227B2 Temperature compensation circuit 失效
标题翻译：温度补偿电路
公开(公告)号：US08427227B2
公开(公告)日：2013-04-23
申请号：US13403121
申请日：2012-02-23
申请人： Koji Horie , Minoru Nagata
发明人： Koji Horie , Minoru Nagata
IPC分类号： G05F3/02 , H03K17/14
CPC分类号： H03F1/302 , H03F3/195 , H03F3/245 , H03F2200/447 , H03F2200/451
摘要： In one embodiment, a temperature compensation circuit includes a bias circuit configured to output a bias current having a current value increasing in proportion to an absolute temperature in a low-temperature region, and having a greater current value than the current value proportional to the absolute temperature in a high-temperature region, and a transistor which is supplied with the bias current. The bias circuit includes first to third transistors, a fourth transistor through which a first current flows, a fifth transistor, a sixth transistor through which a second current flows, and a control circuit having a connection terminal capable of being connected with an external resistor for adjusting a magnitude of the second current. The bias circuit generates a third current by adding the first current to the second current, and outputs the bias current that is the third current or a fourth current depending on the third current.
摘要翻译：在一个实施例中，温度补偿电路包括偏置电路，该偏置电路被配置为输出具有与低温区域中的绝对温度成比例增加的电流值的偏置电流，并且具有比与绝对值成比例的电流值更大的电流值高温区域的温度，以及被提供偏置电流的晶体管。偏置电路包括第一至第三晶体管，第一电流流经的第四晶体管，第五晶体管，第二电流流经的第六晶体管，以及具有能够与外部电阻器连接的连接端子的控制电路，调整第二电流的大小。偏置电路通过将第一电流加到第二电流来产生第三电流，并根据第三电流输出作为第三电流或第四电流的偏置电流。

26. 发明申请

US20110304387A1 CURRENT MIRROR CIRCUIT 失效
标题翻译：当前镜像电路
公开(公告)号：US20110304387A1
公开(公告)日：2011-12-15
申请号：US13046953
申请日：2011-03-14
申请人： Kenichi Hirashiki , Norio Hagiwara , Tsutomu Nakashima , Minoru Nagata
发明人： Kenichi Hirashiki , Norio Hagiwara , Tsutomu Nakashima , Minoru Nagata
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： In one embodiment, a current mirror circuit includes first to fourth insulated gate field effect transistors (FETs), and a bias circuit. The gate electrodes of the first and second FETs are connected to each other. The source electrode of the third FET is connected to the drain electrode of the first FET, and the drain electrode of the third FET is connected to the gate electrodes of the first and second FETs and a current input terminal. The gate electrode of the fourth FET is connected to the gate electrode of the third FET, the source electrode of the fourth FET is connected to the drain electrode of the second FET, and the drain electrode of the fourth FET becomes a current output terminal. The bias circuit is configured to provide a bias voltage to the gate electrodes of the third and fourth FETs.
摘要翻译：在一个实施例中，电流镜电路包括第一至第四绝缘栅场效应晶体管（FET）和偏置电路。第一和第二FET的栅电极彼此连接。第三FET的源电极连接到第一FET的漏电极，第三FET的漏电极连接到第一和第二FET的栅电极以及电流输入端。第四FET的栅电极与第三FET的栅电极连接，第四FET的源电极与第二FET的漏极连接，第四FET的漏极成为电流输出端。偏置电路被配置为向第三和第四FET的栅电极提供偏置电压。

27. 发明授权

US07487225B2 Registering device and method, information processing device and method, providing device and method, and program storage medium 有权
标题翻译：注册装置和方法，信息处理装置和方法，提供装置和方法以及程序存储介质
公开(公告)号：US07487225B2
公开(公告)日：2009-02-03
申请号：US09926007
申请日：2000-12-05
申请人： Mitsuhiro Nishibe , Hirokazu Tsuchiya , Takuya Kajikawa , Atsushi Sakaida , Minoru Nagata , Motohiro Ohama , Yoshimichi Kitaya , Yoshihiro Tamura
发明人： Mitsuhiro Nishibe , Hirokazu Tsuchiya , Takuya Kajikawa , Atsushi Sakaida , Minoru Nagata , Motohiro Ohama , Yoshimichi Kitaya , Yoshihiro Tamura
IPC分类号： G06F15/16 , G06F11/30 , H04L9/00
CPC分类号： G06F21/10 , G06F2221/2117 , G06Q30/02 , H04L63/102 , H04L2463/101
摘要： On receiving from a personal computer (1) a request for transmitting data for displaying a picture for inputting a user's profile in association with an MGID and an APID for specifying the personal computer (1), an EMD registration server (3) selects data recorded in correspondence to the APID based on the received APID and transmits the selected data to the personal computer (1). The EMD registration server (3) receivers the user's profile inputted based on the data from the personal computer (1) and records the user's profile in correspondence to the MGID.
摘要翻译：在从个人计算机（1）接收到用于发送用于显示用于与MGID相关联地输入用户简档的图像的数据的请求和用于指定个人计算机（1）的APID的情况下，EMD注册服务器（3）选择记录的数据基于所接收的APID对应于APID，并将所选择的数据发送到个人计算机（1）。 EMD注册服务器（3）基于来自个人计算机（1）的数据接收输入的用户简档，并记录与MGID对应的用户简档。

28. 发明申请

US20050076096A1 Registering device and method, information processing device and method, providing device and method, and program storage medium 有权
标题翻译：注册装置和方法，信息处理装置和方法，提供装置和方法以及程序存储介质
公开(公告)号：US20050076096A1
公开(公告)日：2005-04-07
申请号：US09926007
申请日：2000-12-05
申请人： Mitsuhiro Nishibe , Hirokazu Tsuchiya , Takuya Kajikawa , Atsushi Sakaida , Minoru Nagata , Motohiro Ohama , Yoshimichi Kitaya , Yoshihiro Tamura
发明人： Mitsuhiro Nishibe , Hirokazu Tsuchiya , Takuya Kajikawa , Atsushi Sakaida , Minoru Nagata , Motohiro Ohama , Yoshimichi Kitaya , Yoshihiro Tamura
IPC分类号： G06F21/10 , G06Q30/00 , H04L29/06 , G06F15/16 , G06F15/167
CPC分类号： G06F21/10 , G06F2221/2117 , G06Q30/02 , H04L63/102 , H04L2463/101
摘要： On receiving from a personal computer (1) a request for transmitting data for displaying a picture for inputting a user's profile in association with an MGID and an APID for specifying the personal computer (1), an EMD registration server (3) selects data recorded in correspondence to the APID based on the received APID and transmits the selected data to the personal computer (1). The EMD registration server (3) receivers the user's profile inputted based on the data from the personal computer (1) and records the user's profile in correspondence to the MGID.
摘要翻译：在从个人计算机（1）接收到发送用于显示用于与MGID相关联地输入用户简档的图像的数据的请求和用于指定个人计算机（1）的APID时，EMD注册服务器（3）选择记录的数据基于所接收的APID对应于APID，并将所选择的数据发送到个人计算机（1）。 EMD注册服务器（3）基于来自个人计算机（1）的数据接收输入的用户简档，并记录与MGID对应的用户简档。

29. 发明授权

US5949484A Portable terminal apparatus for multimedia communication 失效
标题翻译：便携式终端设备，用于多媒体通信
公开(公告)号：US5949484A
公开(公告)日：1999-09-07
申请号：US913161
申请日：1997-09-08
申请人： Yuichiro Nakaya , Yukio Fujii , Minoru Nagata , Masanori Maruyama
发明人： Yuichiro Nakaya , Yukio Fujii , Minoru Nagata , Masanori Maruyama
IPC分类号： H04N7/14 , H04N7/56 , H04N19/00 , H04N19/102 , H04N19/105 , H04N19/107 , H04N19/12 , H04N19/132 , H04N19/134 , H04N19/196 , H04N19/46 , H04N19/50 , H04N19/503 , H04N19/61 , H04N19/625 , H04N19/70 , H04N21/442 , H04N7/12 , H04M11/00
CPC分类号： H04N7/56 , H04N19/162 , H04N19/164 , H04N19/176 , H04N19/61 , H04N7/142 , H04N19/107 , H04N2007/145
摘要： The electric power consumption by a terminal used for communication of multimedia information is controlled by changing the quality of transmitted information. The terminal is provided with input (101, 102, 106 and 107) through which such information as images and sounds is inputted, channel control sections (123 and 124) which output the input information to channels and receive information from the channels, output (103, 104, 108, 109 and 105) which output the information received from the channels in the form of images, sounds, etc., a codec (110) which is provided between the input and output and the control sections, encodes the input information in one of multiple encoding modes in which electric power is differently consumed, and decodes the information inputted from the channels, and a control section (133) which controls the selection of the encoding mode. This terminal can continue information communication for a required period of time at minimum power consumption at the sacrifice of the quality of transmitted information. Therefore, either the power consumption or quality of information can be adequately selected according to the transmission.
摘要翻译： PCT No.PCT / JP95 / 00376 Sec。 371日期：1997年9月8日 102（e）1997年9月8日PCT PCT 1995年3月8日PCT公布。 WO96 / 27987 PCT公开号日期1996年9月12日通过改变发送信息的质量来控制用于多媒体信息通信的终端的电力消耗。终端设置有输入图像和声音等信息的输入（101,102,106和107），将输入信息输出到信道并从信道接收信息的信道控制部分（123和124），输出（ 103,104,108,109和105），其以图像，声音等的形式输出从信道接收的信息，提供在输入和输出与控制部分之间的编解码器（110），对输入以不同的方式消耗电力的多种编码模式之一的信息，以及对从该信道输入的信息进行解码;以及控制部，控制编码模式的选择。该终端可以在牺牲所发送的信息的质量的情况下，以最小功耗持续所需时间段的信息通信。因此，可以根据传输来适当地选择功耗或信息质量。

30. 发明授权

US4881044A Amplifying circuit 失效
标题翻译：放大电路
公开(公告)号：US4881044A
公开(公告)日：1989-11-14
申请号：US139790
申请日：1987-12-30
申请人： Taizo Kinoshita , Satoshi Tanaka , Hirotoshi Tanaka , Nobuo Kotera , Minoru Nagata
发明人： Taizo Kinoshita , Satoshi Tanaka , Hirotoshi Tanaka , Nobuo Kotera , Minoru Nagata
IPC分类号： H03F3/45
CPC分类号： H03F3/45385
摘要： A wide-band and high-gain differential amplifier adapted to amplifying transmitted optical signals of the GHz band is constituted by GaAs MESFET's.Two MESFET's Q1 and Q2 are differentially connected to each other. Drains of Q1 and Q2 are connected to load resistances R.sub.L and R.sub.L via a source-drain path of other MESFET's Q3 and Q4 whose gates are grounded in AC-wise.Current by-passing means 4, 4 are connected to the sources of other MESFET's Q3, Q4. DC bias currents of the differential pair of MESFET's Q1, Q2 are set to relatively large values to increase the mutual conductance gm of the differential pair of MESFET's Q1, Q2. Despite a large DC bias current, the current by-passing means 4, 4 decrease the DC voltage drops across the load resistances R.sub.L, R.sub.L, and enable the differntial amplifier to operate on a low power source voltage.

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