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21. 发明授权

US06831851B2 Mask ROM 有权
标题翻译：面具ROM
公开(公告)号：US06831851B2
公开(公告)日：2004-12-14
申请号：US10386554
申请日：2003-03-13
申请人： Fuh-Cheng Jong , Kent Kuohua Chang
发明人： Fuh-Cheng Jong , Kent Kuohua Chang
IPC分类号： G11C1700
CPC分类号： G11C17/12 , G11C7/18
摘要： The mask ROM of the present is comprises by a plurality of word lines arranged in a grid, a plurality of memory units arranged between the word lines, each memory unit having a drain corresponding, a plurality of first bit lines arranged in parallel and extending in a direction diagonal to the word lines and above the drains, a plurality of second bit lines arranged in parallel and extending in a direction diagonal to the word lines and above the drains, a plurality of first nodes alternately arranged on the first bit lines, a plurality of second nodes alternately arranged on the second bit lines and the second nodes and the first nodes are arranged alternately; a plurality of third bit lines joined to the first bit lines, and a plurality of fourth bit lines joined to the second bit lines.
摘要翻译：本发明的掩模ROM由排列成网格的多个字线，布置在字线之间的多个存储单元组成，每个存储单元具有对应的漏极，多个第一位线并行布置并且延伸与字线对应的方向和排水沟上方的方向，并列排列并沿与字线对角线方向并在排水沟上方延伸的多个第二位线，交替布置在第一位线上的多个第一节点，交替布置在第二位线上的多个第二节点和第二节点和第一节点交替布置; 连接到第一位线的多个第三位线，以及连接到第二位线的多个第四位线。

22. 发明授权

US06812099B2 Method for fabricating non-volatile memory having P-type floating gate 有权
标题翻译：一种用于制造具有P型浮动栅极的非易失性存储器的方法
公开(公告)号：US06812099B2
公开(公告)日：2004-11-02
申请号：US10139119
申请日：2002-05-02
申请人： Hung-Sui Lin , Nian-Kai Zous , Tao-Cheng Lu , Kent Kuohua Chang
发明人： Hung-Sui Lin , Nian-Kai Zous , Tao-Cheng Lu , Kent Kuohua Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： A method for fabricating a non-volatile memory having a P-type floating gate is described. A tunneling layer is formed on a substrate and then a first patterned polysilicon layer is formed on the tunneling layer. A buried drain is formed in the substrate beside the first polysilicon layer and then an insulating structure is formed on the tunneling layer on the buried drain. Thereafter, a second polysilicon layer is formed on the first polysilicon layer to constitute a floating gate together with the first polysilicon layer. A P-type ion is implanted into the second polysilicon layer and then a dielectric layer and a control gate are sequentially formed on the floating gate. A thermal process is then performed to make the P-type, ion in the second polysilicon layer diffuse into the first polysilicon layer.
摘要翻译：描述了一种用于制造具有P型浮动栅极的非易失性存储器的方法。在衬底上形成隧道层，然后在隧道层上形成第一图案化多晶硅层。在第一多晶硅层旁边的衬底中形成掩埋漏极，然后在埋漏极上的隧穿层上形成绝缘结构。此后，在第一多晶硅层上形成第二多晶硅层，以与第一多晶硅层一起构成浮置栅极。将P型离子注入到第二多晶硅层中，然后在浮栅上依次形成电介质层和控制栅。然后进行热处理以使第二多晶硅层中的P型离子扩散到第一多晶硅层中。

23. 发明授权

US06777285B2 Memory device and method for fabricating the same 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US06777285B2
公开(公告)日：2004-08-17
申请号：US10604365
申请日：2003-07-15
申请人： Weng-Hsing Huang , Kent Kuohua Chang
发明人： Weng-Hsing Huang , Kent Kuohua Chang
IPC分类号： H01L218244
CPC分类号： H01L21/76897 , H01L27/105 , H01L27/1052 , H01L27/10885 , Y10S257/905
摘要： A memory device and a method for fabricating the same are described. The memory device includes a substrate, buried bit lines, word line structures, a dielectric layer, conductive lines in trenches and self-aligned contacts. The buried bit lines are located in the substrate, and the word line structures are disposed on the substrate crossing over the buried bit lines. Each word line structure consists of a word line, a gate oxide layer, a capping layer and a spacer. Each conductive line is disposed in the dielectric layer and over a buried bit line, and crosses over the capping layers. The dielectric layer is disposed between the word line structures and between the conductive lines. Each self-aligned contact is disposed under a conductive line and between two adjacent word lines to electrically connect the conductive line and the corresponding buried bit line.
摘要翻译：描述了一种存储器件及其制造方法。存储器件包括衬底，掩埋位线，字线结构，电介质层，沟槽中的导线和自对准触点。掩埋位线位于衬底中，并且字线结构设置在穿过掩埋位线的衬底上。每个字线结构由字线，栅极氧化物层，覆盖层和间隔物组成。每个导电线设置在电介质层中并在掩埋位线之上，并且跨越覆盖层。电介质层设置在字线结构之间和导线之间。每个自对准触点设置在导电线之间和两个相邻字线之间，以电连接导线和相应的掩埋位线。

24. 发明授权

US06773933B2 Method of boosting wafer cleaning efficiency and increasing process yield 有权
标题翻译：提高晶圆清洗效率和提高工艺产量的方法
公开(公告)号：US06773933B2
公开(公告)日：2004-08-10
申请号：US10064369
申请日：2002-07-08
申请人： Szu-Tsun Ma , Kent Kuohua Chang
发明人： Szu-Tsun Ma , Kent Kuohua Chang
IPC分类号： H01L2166
CPC分类号： H01L21/02043 , H01L22/34
摘要： A method of boosting wafer-cleaning efficiency and increasing process yield. Different types of process particles are deposited on a test wafer. The test wafer is cleaned in a cleaning operation. The test wafer is scanned to determine the types of process particles that are completely removed and the types of process particles that remain over the test wafer. The results of wafer scanning are used to provide an assessment of the efficiency of the cleaning operation. Operation parameters of the cleaning operation are adjusted to maximize the wafer-cleaning efficiency.
摘要翻译：提高晶圆清洗效率和提高工艺成品率的方法。不同类型的工艺颗粒沉积在测试晶片上。在清洁操作中清洁测试晶片。扫描测试晶片以确定完全去除的工艺颗粒的类型和保留在测试晶片上的工艺颗粒的类型。晶片扫描的结果用于提供清洁操作的效率的评估。调整清洁操作的操作参数以最大化晶片清洁效率。

25. 发明授权

US06500711B1 Fabrication method for an interpoly dielectric layer 有权
标题翻译：互聚电介质层的制造方法
公开(公告)号：US06500711B1
公开(公告)日：2002-12-31
申请号：US10078034
申请日：2002-02-15
申请人： Kent Kuohua Chang
发明人： Kent Kuohua Chang
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/3144 , H01L21/32105 , H01L21/3211
摘要： A fabrication method for an interpoly dielectric layer, wherein the method provides a substrate having a first polysilicon layer already formed thereon. An interpoly dielectric layer is then formed on the first polysilicon layer, wherein the interpoly dielectric layer is formed using an argon gas/oxygen gas/ammonia gas plasma, a krypton gas/oxygen gas/ammonia gas plasma, an argon gas/oxygen gas plasma or a krypton gas/oxygen gas plasma. After this, a second polysilicon layer is formed on the interpoly dielectric layer.
摘要翻译：一种互聚电介质层的制造方法，其中该方法提供了具有已经在其上形成的第一多晶硅层的衬底。然后在第一多晶硅层上形成间隔电介质层，其中使用氩气/氧气/氨气等离子体，氪气/氧气/氨气等离子体，氩气/氧气等离子体或氪气/氧气等离子体。之后，在多晶硅电介质层上形成第二多晶硅层。

26. 发明授权

US06461949B1 Method for fabricating a nitride read-only-memory (NROM) 有权
标题翻译：氮化物只读存储器（NROM）的制造方法
公开(公告)号：US06461949B1
公开(公告)日：2002-10-08
申请号：US09820305
申请日：2001-03-29
申请人： Kent Kuohua Chang , Chia-Hsing Chen
发明人： Kent Kuohua Chang , Chia-Hsing Chen
IPC分类号： H01L214763
CPC分类号： H01L27/11568 , H01L21/3143 , H01L27/115
摘要： The present invention provides a method of fabricating an improved gate of a nitride read only memory (NROM) in a semiconductor wafer. A bottom oxide and a silicon nitride layer are first formed on the surface of a silicon substrate in the semiconductor wafer, respectively, followed by injecting a tantalum penta ethoxide (Ta(OC2H5)5), under the condition of 300 mTorr and 200-650° C., to form a tantalum pentaoxide (Ta2O5) layer as a top oxide layer. The top oxide layer, silicon nitride layer and the bottom oxide layer compose an oxide-nitride-oxide (ONO) dielectric structure. Finally, a gate conductor layer is formed on the surface of the ONO structure to complete the fabrication of the NROM of the present invention. The tantalum pentaoxide has a high dielectric constant and is used to reduce the control gate voltage and thermal budget so as to increase the coupling ratio and yield of the semiconductor wafer.
摘要翻译：本发明提供一种在半导体晶片中制造氮化物只读存储器（NROM）的改进栅极的方法。首先在半导体晶片中的硅衬底的表面上分别形成底部氧化物和氮化硅层，然后在300mTorr和200-650的条件下注入五乙氧基钽（Ta（OC 2 H 5）5）以形成作为顶部氧化物层的五氧化钽（Ta 2 O 5）层。顶部氧化物层，氮化硅层和底部氧化物层构成氧化物 - 氧化物 - 氧化物（ONO）电介质结构。最后，在ONO结构的表面上形成栅极导体层，以完成本发明的NROM的制造。五氧化二钽具有高介电常数，用于降低控制栅极电压和热预算，以增加半导体晶片的耦合比和产率。

27. 发明授权

US06323047B1 Method for monitoring second gate over-etch in a semiconductor device 有权
公开(公告)号：US06323047B1
公开(公告)日：2001-11-27
申请号：US09368247
申请日：1999-08-03
申请人： John JianShi Wang , Kent Kuohua Chang , Hao Fang
发明人： John JianShi Wang , Kent Kuohua Chang , Hao Fang
IPC分类号： H01L2166
CPC分类号： H01L27/11526 , H01L21/32137 , H01L22/34 , H01L27/115 , H01L27/11521 , H01L27/11531
摘要： The present invention provides a method for monitoring for a second gate over etch in a flash memory device. The method includes providing at least one select transistor stack structure in the core area of the substrate and at least one monitor structure in the monitor area of the substrate; determining a thickness of a select gate layer of the at least one monitor structure; and determining if a second gate over etch occurred upon the thickness of the select gate layer of the at least one monitor structure. The select gate layer of the monitor structure is the same select gate layer of the select transistor stack structure. The select gate thickness of the select transistor stack structure may be determined by measuring the thickness at the monitor structure. This measurement is possible at the monitor area because the monitor structures are placed far enough apart to support measuring instruments. With the method in accordance with the present invention, a second gate over etch and its extent can be monitored without destroying the device. The method requires less time than conventional monitoring methods and is also less costly.

28. 发明授权

US06204159B1 Method of forming select gate to improve reliability and performance for NAND type flash memory devices 有权
标题翻译：形成选择栅极以提高NAND型闪存器件的可靠性和性能的方法
公开(公告)号：US06204159B1
公开(公告)日：2001-03-20
申请号：US09349603
申请日：1999-07-09
申请人： Kent Kuohua Chang , Kenneth Wo-Wai Au , Yuesong He
发明人： Kent Kuohua Chang , Kenneth Wo-Wai Au , Yuesong He
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11529 , H01L27/11546
摘要： In one embodiment, the present invention relates to a method of forming a NAND type flash memory device, involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a core region and a periphery region, the core region including a flash memory cell area and a select gate area and the periphery region including a high voltage transistor area and low voltage transistor area; depositing a first doped amorphous silicon layer over at least a portion of the first oxide layer; depositing a dielectric layer over at least a portion of the first doped amorphous silicon layer; removing portions of the first oxide layer, the first doped amorphous silicon layer, and the dielectric layer in the select gate area of the core region and the high voltage transistor area and the low voltage transistor area the periphery region; growing a second oxide layer over at least a portion of the substrate in the select gate area of the core region and the high voltage transistor area and the low voltage transistor area the periphery region; removing portions of the second oxide layer in the select gate area of the core region and the low voltage transistor area the periphery region; growing a third oxide layer over at least a portion of the substrate in the select gate area of the core region and the low voltage transistor area of the periphery region; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer, the second oxide layer and the third oxide layer; and forming a flash memory cell in the flash memory cell area of the core region, a select gate transistor in the select gate area of the core region, a low voltage transistor in the low voltage transistor area of the periphery region, and a high voltage transistor in the high voltage transistor area of the periphery region.
摘要翻译：在一个实施例中，本发明涉及一种形成NAND型快闪存储器件的方法，包括以下步骤：在衬底的至少一部分上生长第一氧化层，所述衬底包括芯区域和周边区域，芯区域包括闪存单元区域和选择栅极区域，并且包括高压晶体管区域和低压晶体管区域的周边区域; 在所述第一氧化物层的至少一部分上沉积第一掺杂非晶硅层; 在所述第一掺杂非晶硅层的至少一部分上沉积介电层; 去除所述芯区域的所述选择栅极区域中的所述第一氧化物层，所述第一掺杂非晶硅层和所述介电层的部分，以及所述高压晶体管区域和所述低电压晶体管区域的外围区域; 在所述芯区域的所述选择栅极区域中的所述衬底的至少一部分和所述高压晶体管区域和所述低电压晶体管区域的外围区域上生长第二氧化物层; 去除芯区域的选择栅极区域中的第二氧化物层的部分和外围区域的低电压晶体管区域; 在芯区域的选择栅极区域和外围区域的低电压晶体管区域的至少一部分衬底上生长第三氧化物层; 在所述电介质层，所述第二氧化物层和所述第三氧化物层的至少一部分上沉积第二掺杂非晶硅层; 以及在芯区的闪速存储单元区域中形成闪速存储单元，在芯区的选择栅极区中的选择栅极晶体管，外围区的低电压晶体管区中的低电压晶体管，以及高电压晶体管在周边区域的高压晶体管区域。

29. 发明授权

US6162684A Ammonia annealed and wet oxidized LPCVD oxide to replace ono films for high integrated flash memory devices 失效
标题翻译：氨退火和湿氧化LPCVD氧化物以替代用于高集成闪存器件的膜
公开(公告)号：US6162684A
公开(公告)日：2000-12-19
申请号：US266714
申请日：1999-03-11
申请人： Kent Kuohua Chang , David Chi , Chin-Yang Sun
发明人： Kent Kuohua Chang , David Chi , Chin-Yang Sun
IPC分类号： H01L21/28 , H01L21/314 , H01L29/51 , H01L21/336
CPC分类号： H01L21/28202 , H01L21/28211 , H01L21/28273 , H01L21/3144 , H01L29/511 , H01L29/518
摘要： In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer, the insulating layer comprising an oxide layer made by low pressure chemical vapor deposition at a temperature from about 600.degree. C. to about 850.degree. C. using SiH.sub.4 and N.sub.2 O, annealing in an NH.sub.3 atmosphere at a temperature from about 800.degree. C. to about 900.degree. C., and wet oxidizing using O.sub.2 and H.sub.2 at a temperature from about 820.degree. C. to about 880.degree. C.; forming a second polysilicon layer over the insulating layer; etching at least the first polysilicon layer, the second polysilicon layer and the insulating layer, thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, thereby forming at least one memory cell.
摘要翻译：在一个实施例中，本发明涉及一种形成闪速存储器单元的方法，包括在衬底上形成隧道氧化物的步骤; 在隧道氧化物上形成第一多晶硅层; 在所述第一多晶硅层上形成绝缘层，所述绝缘层包括通过使用SiH 4和N 2 O在约600℃至约850℃的温度下由低压化学气相沉积制成的氧化物层，在NH 3气氛中退火温度为约800℃至约900℃，并在约820℃至约880℃的温度下使用O 2和H 2进行湿氧化。在所述绝缘层上形成第二多晶硅层; 至少蚀刻第一多晶硅层，第二多晶硅层和绝缘层，从而限定至少一个堆叠栅极结构; 以及在衬底中形成源区和漏区，由此形成至少一个存储单元。

30. 发明授权

US6146795A Method for manufacturing memory devices 有权
标题翻译：制造存储器件的方法
公开(公告)号：US6146795A
公开(公告)日：2000-11-14
申请号：US146032
申请日：1998-09-02
申请人： Jiahua Huang , Yuesong He , Kent Kuohua Chang
发明人： Jiahua Huang , Yuesong He , Kent Kuohua Chang
IPC分类号： G03F7/36 , G03F7/40
CPC分类号： G03F7/40 , G03F7/36
摘要： Tunnel oxide degradation is reduced by reducing residual photoresist material in open areas of a mask pattern. Embodiments include detecting residual photoresist in an exposed underlying region of a substrate by x-ray spectroscopy and descumming in response to detected residual photoresist.
摘要翻译：通过在掩模图案的开放区域中减少残留光致抗蚀剂材料来减少隧道氧化物降解。实施例包括通过X射线光谱检测在基底的暴露下面的区域中的残留光致抗蚀剂，并响应于检测到的残留光致抗蚀剂除去。

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