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21. 发明授权

US06769093B1 Synchronization of a communications system 有权
标题翻译：通信系统的同步
公开(公告)号：US06769093B1
公开(公告)日：2004-07-27
申请号：US09788171
申请日：2001-02-14
申请人： Abraham Krieger
发明人： Abraham Krieger
IPC分类号： H04L700
CPC分类号： H04N21/4382 , H04J3/0608 , H04L1/005 , H04L1/0065 , H04L1/0075 , H04N21/2383
摘要： A receiver in which sync data detection logic detects unencoded sync data at block boundaries of blocks encoded symbols received over a communications channel. Based on the detection of the sync data, the sync data detection logic determine synchronization information for one or more components of the receiver. It may also determine one or more system parameters by counting the number of symbols between successive instances of the sync data.
摘要翻译：一种接收机，其中同步数据检测逻辑在通过通信信道接收的块编码符号的块边界处检测未编码的同步数据。基于同步数据的检测，同步数据检测逻辑确定接收机的一个或多个组件的同步信息。它还可以通过对同步数据的连续实例之间的符号数进行计数来确定一个或多个系统参数。

22. 发明授权

US07564892B1 Satellite transcoder 失效
标题翻译：卫星代码转换器
公开(公告)号：US07564892B1
公开(公告)日：2009-07-21
申请号：US10611400
申请日：2003-06-30
申请人： Mats Lidstrom , Lior Levin , Abraham Krieger
发明人： Mats Lidstrom , Lior Levin , Abraham Krieger
IPC分类号： H04B3/36
CPC分类号： H04B1/18 , H04N21/2383 , H04N21/4382
摘要： A transcoder is described for converting a received first digital signal with a first modulation and encoding scheme to a second digital signal with a second modulation and encoding scheme. The transcoder may include a demodulator that produces a demodulated digital stream of data from the received first digital signal and a modulator in signal communication with the demodulator, where the modulator modulates the digital stream of data with the second modulation and encoding scheme. Additionally, the transcoder may include an upconverter in signal communication with the modulator, where the upconverter produces the second digital signal.
摘要翻译：描述了一种代码转换器，用于利用第二调制和编码方案将接收到的具有第一调制和编码方案的第一数字信号转换为第二数字信号。代码转换器可以包括解调器，其从接收到的第一数字信号产生解调的数字数据流，以及调制器与解调器进行信号通信，其中调制器利用第二调制和编码方案对数字数据流进行调制。此外，代码转换器可以包括与调制器进行信号通信的上变频器，其中上变频器产生第二数字信号。

23. 发明授权

US07310768B2 Iterative decoder employing multiple external code error checks to lower the error floor 有权
标题翻译：迭代解码器采用多个外部代码错误检查来降低错误的底数
公开(公告)号：US07310768B2
公开(公告)日：2007-12-18
申请号：US10892738
申请日：2004-07-16
申请人： Donald Brian Eidson , Abraham Krieger , Ramaswamy Murali
发明人： Donald Brian Eidson , Abraham Krieger , Ramaswamy Murali
IPC分类号： H03M13/03
CPC分类号： H04L1/005 , H03M13/09 , H03M13/15 , H03M13/2936 , H03M13/2948 , H03M13/2972 , H03M13/3776 , H03M13/3994 , H04L1/0054 , H04L1/0061 , H04L1/0065 , H04L1/0066
摘要： Iterative decoder employing multiple external code error checks to lower the error floor and/or improve decoding performance. Data block redundancy, sometimes via a cyclic redundancy check (CRC) or Reed Solomon (RS) code, enables enhanced iterative decoding performance. Improved decoding performance is achieved during interim iterations before the final iteration. A correctly decoded CRC block, indicating a decoded segment is correct with a high degree of certainty, assigns a very high confidence level to the bits in this segment and is fed back to inner and/or outer decoders (with interleaving, when appropriate) for improved iterative decoding. High confidence bits may be scattered throughout inner decoded frames to influence other bit decisions in subsequent iterations. Turbo decoders typically operate relatively well at regions where the BER is high; the invention improves iterative decoder operation at lower BERs, lowering the ‘BER floor’ that is sometimes problematic with conventional turbo decoders.
摘要翻译：迭代解码器采用多个外部码错误检查来降低错误帧和/或提高解码性能。有时通过循环冗余校验（CRC）或Reed Solomon（RS）代码进行数据块冗余，可实现增强的迭代解码性能。在最终迭代之前的中间迭代期间，可以实现改进的解码性能。一个正确解码的CRC块，指示解码的段是高度确定的正确的，为该段中的位分配非常高的置信度水平，并将其反馈给内部和/或外部解码器（适当时进行交织），以便改进的迭代解码。高置信位可能散布在整个内部解码帧中，以影响后续迭代中的其他位决策。 Turbo解码器通常在BER高的区域相对较好地工作; 本发明改进了在较低BER下的迭代解码器操作，降低了常规turbo解码器有时成问题的“BER地面”。

24. 发明授权

US07065703B2 Synchronization of a communications system 有权
标题翻译：通信系统的同步
公开(公告)号：US07065703B2
公开(公告)日：2006-06-20
申请号：US10893673
申请日：2004-07-15
申请人： Abraham Krieger
发明人： Abraham Krieger
IPC分类号： H04L7/00
CPC分类号： H04J3/0608
摘要： A receiver in which sync data detection logic detects unencoded sync data at block boundaries of blocks encoded symbols received over a communications channel. Based on the detection of the sync data, the sync data detection logic determine synchronization information for one or more components of the receiver. It may also determine one or more system parameters by counting the number of symbols between successive instances of the sync data.
摘要翻译：一种接收机，其中同步数据检测逻辑在通过通信信道接收的块编码符号的块边界处检测未编码的同步数据。基于同步数据的检测，同步数据检测逻辑确定接收机的一个或多个组件的同步信息。它还可以通过对同步数据的连续实例之间的符号数进行计数来确定一个或多个系统参数。

25. 发明授权

US07958424B2 Multi-channel LDPC decoder architecture 有权
标题翻译：多通道LDPC解码器架构
公开(公告)号：US07958424B2
公开(公告)日：2011-06-07
申请号：US11303876
申请日：2005-12-16
申请人： Shachar Kons , Gadi Kalit , Eran Arad , Shimon Gur , Yoav GoldenBerg , Abraham Krieger
发明人： Shachar Kons , Gadi Kalit , Eran Arad , Shimon Gur , Yoav GoldenBerg , Abraham Krieger
IPC分类号： H03M13/00
CPC分类号： H03M13/114 , H03M13/6502 , H03M13/6561
摘要： A multi-channel decoder system has a decoder core at least a portion of which is configurable as a LDPC decoder that, during decoding processing, divides check nodes of a node representation of a LDPC code into a plurality of groups, and, during an iteration, sequentially processes the groups while processing in parallel the check nodes within each group, thus improving decoding throughput.
摘要翻译：多通道解码器系统具有解码器核心，其至少一部分可配置为LDPC解码器，其在解码处理期间将LDPC码的节点表示的校验节点分成多个组，并且在迭代期间在并行处理各组中的校验节点的同时顺序处理组，从而提高解码吞吐量。

26. 发明授权

US07568147B2 Iterative decoder employing multiple external code error checks to lower the error floor 有权
标题翻译：迭代解码器采用多个外部代码错误检查来降低错误的底数
公开(公告)号：US07568147B2
公开(公告)日：2009-07-28
申请号：US11944320
申请日：2007-11-21
申请人： Donald Brian Eidson , Abraham Krieger , Ramaswamy Murali
发明人： Donald Brian Eidson , Abraham Krieger , Ramaswamy Murali
IPC分类号： H03M13/03
CPC分类号： H04L1/005 , H03M13/09 , H03M13/15 , H03M13/2936 , H03M13/2948 , H03M13/2972 , H03M13/3776 , H03M13/3994 , H04L1/0054 , H04L1/0061 , H04L1/0065 , H04L1/0066
摘要： Iterative decoder employing multiple external code error checks to lower the error floor and/or improve decoding performance. Data block redundancy, sometimes via a cyclic redundancy check (CRC) or Reed Solomon (RS) code, enables enhanced iterative decoding performance. Improved decoding performance is achieved during interim iterations before the final iteration. A correctly decoded CRC block, indicating a decoded segment is correct with a high degree of certainty, assigns a very high confidence level to the bits in this segment and is fed back to inner and/or outer decoders (with interleaving, when appropriate) for improved iterative decoding. High confidence bits may be scattered throughout inner decoded frames to influence other bit decisions in subsequent iterations. Turbo decoders typically operate relatively well at regions where the BER is high; the invention improves iterative decoder operation at lower BERs, lowering the ‘BER floor’ that is sometimes problematic with conventional turbo decoders.
摘要翻译：迭代解码器采用多个外部码错误检查来降低错误帧和/或提高解码性能。有时通过循环冗余校验（CRC）或Reed Solomon（RS）代码进行数据块冗余，可实现增强的迭代解码性能。在最终迭代之前的中间迭代期间，可以实现改进的解码性能。一个正确解码的CRC块，指示解码的段是高度确定的正确的，为该段中的位分配非常高的置信度水平，并将其反馈给内部和/或外部解码器（适当时进行交织），以便改进的迭代解码。高置信位可能散布在整个内部解码帧中，以影响后续迭代中的其他位决策。 Turbo解码器通常在BER高的区域相对较好地工作; 本发明改进了在较低BER下的迭代解码器操作，降低了常规turbo解码器有时成问题的“BER地面”。

27. 发明授权

US07231005B2 Symbol reliability determination and symbol pre-selection based on reliability criteria 有权
标题翻译：基于可靠性标准的符号可靠性确定和符号预选
公开(公告)号：US07231005B2
公开(公告)日：2007-06-12
申请号：US10368017
申请日：2003-02-14
申请人： Donald Brian Eidson , Ramaswamy Murali , Abraham Krieger , Magnus H. Berggren
发明人： Donald Brian Eidson , Ramaswamy Murali , Abraham Krieger , Magnus H. Berggren
IPC分类号： H03D1/00 , H04L27/06
CPC分类号： H04L1/0054 , H04L1/0055 , H04L25/025 , H04L25/067 , H04L2025/03598
摘要： A method and apparatus for processing demodulated data comprising received symbol data is disclosed. A decoder is used to compute estimated symbols and corresponding reliability metrics. The reliability metrics are transformed into reliability weights. Optionally, residuals relating to the difference between the received symbol data and the estimated symbols are computed. Output data are generated comprising any combination of the following: estimated symbols, reliability weights, residuals, and received symbol data. The residuals may be weighted by the reliability metrics and used by demodulation or error compensation loops to instantaneously reduce or increase the bandwidth of these loops.
摘要翻译：公开了一种用于处理包括接收符号数据的解调数据的方法和装置。解码器用于计算估计符号和相应的可靠性度量。可靠性度量被转化为可靠性权重。可选地，计算与接收的符号数据和估计的符号之间的差有关的残差。产生输出数据，包括以下任意组合：估计符号，可靠性权重，残差和接收到的符号数据。可以通过可靠度度量对残差进行加权，并由解调或误差补偿回路使用，以瞬时减少或增加这些回路的带宽。

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