专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20120146186A1 THERMALLY CONTROLLED REFRACTORY METAL RESISTOR 有权
标题翻译：热控制的金属电阻器
公开(公告)号：US20120146186A1
公开(公告)日：2012-06-14
申请号：US12962722
申请日：2010-12-08
申请人： Joseph M. Lukaitis , Deborah M. Massey , Timothy D. Sullivan , Ping-Chuan Wang , Kimball M. Watson
发明人： Joseph M. Lukaitis , Deborah M. Massey , Timothy D. Sullivan , Ping-Chuan Wang , Kimball M. Watson
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L28/20 , H01L23/3677 , H01L23/5228 , H01L27/0211 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors.
摘要翻译：制造该结构的结构和方法包括：半导体衬底，其具有限定水平方向的顶表面和从最接近半导体衬底的顶表面的最底层到距离顶表面最远的最高水平层叠的多个互连层。每个互连层包括在垂直于水平方向的垂直方向上彼此物理连接的垂直金属导体。最底层的垂直导体物理地连接到衬底的顶表面，垂直导体形成连接到半导体衬底的散热片。一个电阻器被包含在最上层的上方的层中。垂直导体在电阻器的向下垂直电阻器占位面下对准，并且每个互连级别还包括位于水平方向上并且连接到垂直导体的水平金属导体。

22. 发明申请

US20120091556A1 VERTICAL SILICIDE E-FUSE 有权
标题翻译：垂直硅胶电子保险丝
公开(公告)号：US20120091556A1
公开(公告)日：2012-04-19
申请号：US12904435
申请日：2010-10-14
申请人： Ephrem G. Gebreselasie , Joseph M. Lukaitis , Robert R. Robison , William R. Tonti , Ping-Chuan Wang
发明人： Ephrem G. Gebreselasie , Joseph M. Lukaitis , Robert R. Robison , William R. Tonti , Ping-Chuan Wang
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An apparatus and a method of manufacturing an e-fuse includes a substrate, a patterned gate insulator on the substrate, and a patterned gate conductor on the patterned gate insulator. The patterned gate conductor has sidewalls and a top. A silicide contacts the sidewalls of the patterned gate conductor, the top of the patterned gate conductor, and a region of the substrate adjacent the patterned gate insulator and the patterned gate conductor.
摘要翻译：一种制造电熔丝的装置和方法包括：衬底，衬底上的图案化栅极绝缘体，以及图案化栅极绝缘体上的图案化栅极导体。图案化的栅极导体具有侧壁和顶部。硅化物接触图案化栅极导体的侧壁，图案化栅极导体的顶部以及与图案化栅极绝缘体和图案化栅极导体相邻的衬底区域。

23. 发明授权

US08592947B2 Thermally controlled refractory metal resistor 有权
$Thermally controlled refractory metal resistor$
标题翻译：耐热耐火金属电阻
公开(公告)号：US08592947B2
公开(公告)日：2013-11-26
申请号：US12962722
申请日：2010-12-08
申请人： Joseph M. Lukaitis , Deborah M. Massey , Timothy D. Sullivan , Ping-Chuan Wang , Kimball M. Watson
发明人： Joseph M. Lukaitis , Deborah M. Massey , Timothy D. Sullivan , Ping-Chuan Wang , Kimball M. Watson
IPC分类号： H01L23/36
CPC分类号： H01L28/20 , H01L23/3677 , H01L23/5228 , H01L27/0211 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors.
摘要翻译：制造该结构的结构和方法包括：半导体衬底，其具有限定水平方向的顶表面和从最接近半导体衬底的顶表面的最底层到距离顶表面最远的最高水平层叠的多个互连层。每个互连层包括在垂直于水平方向的垂直方向上彼此物理连接的垂直金属导体。最底层的垂直导体物理地连接到衬底的顶表面，垂直导体形成连接到半导体衬底的散热片。一个电阻器被包含在最上层的上方的层中。垂直导体在电阻器的向下垂直电阻器占位面下对准，并且每个互连级别还包括位于水平方向上并且连接到垂直导体的水平金属导体。

24. 发明授权

US08530319B2 Vertical silicide e-fuse 有权
标题翻译：垂直硅化物电熔丝
公开(公告)号：US08530319B2
公开(公告)日：2013-09-10
申请号：US12904435
申请日：2010-10-14
申请人： Ephrem G. Gebreselasie , Joseph M. Lukaitis , Robert R. Robison , William R. Tonti , Ping-Chuan Wang
发明人： Ephrem G. Gebreselasie , Joseph M. Lukaitis , Robert R. Robison , William R. Tonti , Ping-Chuan Wang
IPC分类号： H01L21/20 , H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An apparatus and a method of manufacturing an e-fuse includes a substrate, a patterned gate insulator on the substrate, and a patterned gate conductor on the patterned gate insulator. The patterned gate conductor has sidewalls and a top. A silicide contacts the sidewalls of the patterned gate conductor, the top of the patterned gate conductor, and a region of the substrate adjacent the patterned gate insulator and the patterned gate conductor.
摘要翻译：一种制造电熔丝的装置和方法包括：衬底，衬底上的图案化栅极绝缘体，以及图案化栅极绝缘体上的图案化栅极导体。图案化的栅极导体具有侧壁和顶部。硅化物接触图案化栅极导体的侧壁，图案化栅极导体的顶部以及与图案化栅极绝缘体和图案化栅极导体相邻的衬底的区域。

25. 发明申请

US20090072406A1 INTERCONNECT STRUCTURE WITH IMPROVED ELECTROMIGRATION RESISTANCE AND METHOD OF FABRICATING SAME 审中-公开
标题翻译：具有改进的电阻率的互连结构及其制造方法
公开(公告)号：US20090072406A1
公开(公告)日：2009-03-19
申请号：US11856970
申请日：2007-09-18
申请人： Chih-Chao Yang , Ping-Chuan Wang , Kaushik Chanda
发明人： Chih-Chao Yang , Ping-Chuan Wang , Kaushik Chanda
IPC分类号： H01L21/31
CPC分类号： H01L21/76843 , H01L21/76846 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in which the electromigration resistance thereof is improved without introducing a gouging feature within the interconnect structure is provided. The interconnect structure includes a metallic interfacial layer that is at least horizontally present at the bottom of an opening located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer does not form an alloy with an underlying conductive material that is embedded within the first dielectric material. In some embodiments of the present invention, the metallic interfacial layer is also present on exposed sidewalls of the second dielectric material that is located atop the first dielectric material. Atop the metallic interfacial layer there is present a diffusion barrier liner. In some embodiments, the diffusion barrier liner includes a lower layer of a metallic nitride and an upper layer of a metal. In accordance with the present invention, the metallic interfacial layer also does not form an alloy with any portion of the diffusion barrier liner.
摘要翻译：提供了一种互连结构，其中在不引入互连结构内的气蚀特征的情况下，其电迁移阻力得到改善。互连结构包括金属界面层，其至少水平存在于位于第二介电材料内的开口的底部，该第二电介质材料位于第一电介质材料的顶部，该第一介电材料包括嵌入其中的第一导电材料。金属界面层不与嵌入在第一介电材料内的下面的导电材料形成合金。在本发明的一些实施例中，金属界面层也存在于位于第一介电材料顶部的第二介电材料的暴露的侧壁上。在金属界面层顶部存在扩散阻挡层。在一些实施例中，扩散阻挡衬里包括金属氮化物的下层和金属的上层。根据本发明，金属界面层也不与扩散阻挡衬里的任何部分形成合金。

26. 发明申请

US20060254053A1 POST CHEMICAL MECHANICAL POLISHING ETCH FOR IMPROVED TIME DEPENDENT DIELECTRIC BREAKDOWN RELIABILITY 失效
标题翻译：后期化学机械抛光蚀刻改进时间依赖介质断开可靠性
公开(公告)号：US20060254053A1
公开(公告)日：2006-11-16
申请号：US10908392
申请日：2005-05-10
申请人： Kaushik Chanda , James Demarest , Ronald Filippi , Roy Iggulden , Edward Kiewra , Ping-Chuan Wang , Yun-Yu Wang
发明人： Kaushik Chanda , James Demarest , Ronald Filippi , Roy Iggulden , Edward Kiewra , Ping-Chuan Wang , Yun-Yu Wang
IPC分类号： H05K3/02 , H01K3/10 , B24B1/00
CPC分类号： B24B37/042 , H01L21/31144 , H01L21/76834 , H01L21/7684 , H01L21/76849 , H01L21/76852 , H01L21/76885 , Y10T29/49156 , Y10T29/49165 , Y10T29/49204
摘要： Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.
摘要翻译：公开了一种镶嵌和双镶嵌工艺，其中两者都结合使用剥离层以在金属互连线之间移除痕量的残余材料。释放层沉积在电介质层上。释放层包括有机材料，电介质材料，金属或金属氮化物。沟槽蚀刻到电介质层中。沟槽内衬衬里，填充导体。导体和衬里材料从剥离层抛光。然而，痕量的剩余材料可能会残留。去除脱模层（例如，通过适当的溶剂或湿蚀刻工艺）以除去残留的材料。如果沟槽形成为使得剥离层与沟槽的壁重叠，则当除去剥离层时，可以沉积另外的介电层，加强围绕金属互连线的顶部的拐角。

27. 发明授权

US08304863B2 Electromigration immune through-substrate vias 有权
标题翻译：电迁移免疫穿透通孔
公开(公告)号：US08304863B2
公开(公告)日：2012-11-06
申请号：US12702463
申请日：2010-02-09
申请人： Ronald G. Filippi , John A. Fitzsimmons , Kevin Kolvenbach , Ping-Chuan Wang
发明人： Ronald G. Filippi , John A. Fitzsimmons , Kevin Kolvenbach , Ping-Chuan Wang
IPC分类号： H01L29/40
CPC分类号： H01L25/0657 , H01L21/76898 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/10253 , H01L2924/1301 , H01L2924/1305 , H01L2924/00 , H01L2224/05552
摘要： A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.
摘要翻译：贯穿衬底通孔（TSV）结构包括至少两个嵌入衬底中的导电通路段，并且通过它们之间的导电阻挡层彼此分离。每个单独的导电通路段的长度通常等于或小于导电材料的漂浮长度，使得由每个导电阻挡层产生的应力引起的后向流动力抵消每个导电通路段中的电迁移力。因此，TSV结构免于电迁移，并且在三维堆叠的芯片之间提供可靠的电连接。

28. 发明授权

US08237283B2 Structure and method of reducing electromigration cracking and extrusion effects in semiconductor devices 失效
标题翻译：减少半导体器件中电迁移破裂和挤出效应的结构和方法
公开(公告)号：US08237283B2
公开(公告)日：2012-08-07
申请号：US11758206
申请日：2007-06-05
申请人： Kaushik Chandra , Ronald G. Filippi , Wai-Lin Li , Ping-Chuan Wang , Chih-Chao Yang
发明人： Kaushik Chandra , Ronald G. Filippi , Wai-Lin Li , Ping-Chuan Wang , Chih-Chao Yang
IPC分类号： H01L23/52
CPC分类号： H01L23/528 , H01L21/7682 , H01L21/76831 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer.
摘要翻译：用于减少半导体器件中的电迁移破裂和挤出效应的结构包括形成在第一介电层中的第一金属线; 形成在第一金属线和第一介电层上的盖层; 形成在所述盖层上的第二电介质层; 以及形成在第二介电层中的空隙，停止在盖层上，其中，空隙以如下方式定位，以便隔离由于第一金属线的电迁移效应引起的结构损坏，包括一种或多种金属挤压的效果来自第一金属线的材料和帽层相对于第一介电层分层的裂纹。

29. 发明申请

US20110254168A1 INTEGRATED CIRCUIT INTERCONNECT STRUCTURE 有权
标题翻译：集成电路互连结构
公开(公告)号：US20110254168A1
公开(公告)日：2011-10-20
申请号：US12760594
申请日：2010-04-15
申请人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
发明人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
IPC分类号： H01L23/522 , H01L21/768 , G06F17/50
CPC分类号： H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.
摘要翻译：一种集成电路（IC）互连结构，其包括位于电介质中并且在一端耦合到高电流器件的第一通孔和位于电介质中的缓冲金属段，并在其相对端耦合到第一通孔。缓冲金属段包括在其上形成ILD干酪糖化图案的多个电绝缘介电层（ILD）焊盘以引导电流。 IC互连结构还包括位于介质上的第二通孔，该电介质形成在缓冲金属段上并且在一端耦合到缓冲金属段，并且金属电源线形成在电介质中，并在其相对端耦合到第二通孔。缓冲金属片段上的ILD焊盘的使用使得能够沿着金属电源线更均匀地分布电流。

30. 发明授权

US08912658B2 Interconnect structure with enhanced reliability 有权
标题翻译：互连结构，增强可靠性
公开(公告)号：US08912658B2
公开(公告)日：2014-12-16
申请号：US12915510
申请日：2010-10-29
申请人： Ronald Filippi , Ping-Chuan Wang , Griselda Bonilla , Kaushik Chanda , Robert D. Edwards , Andrew H. Simon
发明人： Ronald Filippi , Ping-Chuan Wang , Griselda Bonilla , Kaushik Chanda , Robert D. Edwards , Andrew H. Simon
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/532 , H01L21/768
CPC分类号： H01L21/76834 , H01L21/76819 , H01L21/76829 , H01L21/76849 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided.
摘要翻译：一种改进的互连结构，其包括具有嵌入其中的导电特征的介电层，所述导电特征具有与介电层的第二顶表面基本共面的第一顶表面; 金属盖层直接位于第一顶表面上，其中金属盖层基本上不延伸到第二顶表面上; 位于所述第二顶表面上的第一电介质盖层，其中所述第一电介质盖层基本上不延伸到所述第一顶表面上，并且所述第一电介质盖层比所述金属盖层厚; 以及金属盖层和第一电介质盖层上的第二电介质盖层。还提供了形成互连结构的方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式