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21. 发明申请

US20120126363A1 STRUCTURE OF METAL E-FUSE 失效
标题翻译：金属电子熔断器的结构
公开(公告)号：US20120126363A1
公开(公告)日：2012-05-24
申请号：US12952317
申请日：2010-11-23
申请人： Ping-Chuan Wang , Chunyan E. Tian , Ronald Filippi , Wai-ki Li
发明人： Ping-Chuan Wang , Chunyan E. Tian , Ronald Filippi , Wai-ki Li
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Structures of electronic fuses (e-fuse) are provided. An un-programmed e-fuse includes a via of a first conductive material having a bottom and sidewalls with a portion of the sidewalls being covered by a conductive liner and the bottom of the via being formed on top of a dielectric layer, and a first and a second conductive path of a second conductive material formed on top of the dielectric layer with the first and second conductive paths being conductively connected through, and only through, the via at the sidewalls. A programmed e-fuse includes a via; a first conductive path at a first side of the via and being separated from sidewalls of the via by a void; and a second conductive path at a second different side of the via and being in conductive contact with the via through sidewalls of the via.
摘要翻译：提供电子保险丝（e-fuse）的结构。未编程的电子熔断器包括具有底部和侧壁的第一导电材料的通孔，侧壁的一部分被导电衬垫覆盖，并且通孔的底部形成在电介质层的顶部上，并且第一以及形成在电介质层顶部上的第二导电材料的第二导电路径，其中第一和第二导电路径通过侧壁导通地连接，并且仅通过通孔。编程的电子熔丝包括通孔; 在通孔的第一侧处的第一导电路径，并且通过空隙与通路的侧壁分离; 以及在所述通孔的第二不同侧的第二导电路径，并且与通孔通过所述通孔的侧壁导电接触。

22. 发明申请

US20100327445A1 STRUCTURE OF POWER GRID FOR SEMICONDUCTOR DEVICES AND METHOD OF MAKING THE SAME 有权
标题翻译：半导体器件的电源结构及其制造方法
公开(公告)号：US20100327445A1
公开(公告)日：2010-12-30
申请号：US12491372
申请日：2009-06-25
申请人： Ronald Filippi , Wai-kin Li , Ping-Chuan Wang
发明人： Ronald Filippi , Wai-kin Li , Ping-Chuan Wang
IPC分类号： H01L23/535 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76847 , H01L21/76852 , H01L23/5286 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided.
摘要翻译：本发明的一个实施例提供一种半导体结构，其可以包括形成在电介质层内部的第一导电材料的支柱; 具有底部的第二导电材料的通孔和具有底部的侧壁，并且侧壁被导电衬垫覆盖，并且底部直接形成在螺柱的顶部上并且通过导电衬套与通孔接触; 以及一个或多个第三导电材料的导电路径，所述第三导电材料在所述导电衬套的侧壁处通过所述导电衬套连接到所述通孔。还提供了制造半导体结构的方法。

23. 发明授权

US08349723B2 Structure of power grid for semiconductor devices and method of making the same 失效
标题翻译：半导体器件电网结构及其制作方法
公开(公告)号：US08349723B2
公开(公告)日：2013-01-08
申请号：US13342221
申请日：2012-01-03
申请人： Ronald Filippi , Wai-kin Li , Ping-Chuan Wang
发明人： Ronald Filippi , Wai-kin Li , Ping-Chuan Wang
IPC分类号： H01L21/4763
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76847 , H01L21/76852 , H01L23/5286 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided.
摘要翻译：本发明的一个实施例提供一种半导体结构，其可以包括形成在电介质层内部的第一导电材料的支柱; 具有底部的第二导电材料的通孔和具有底部的侧壁，并且侧壁被导电衬垫覆盖，并且底部直接形成在螺柱的顶部上并且通过导电衬套与通孔接触; 以及一个或多个第三导电材料的导电路径，所述第三导电材料在所述导电衬套的侧壁处通过所述导电衬套连接到所述通孔。还提供了制造半导体结构的方法。

24. 发明授权

US08299567B2 Structure of metal e-fuse 失效
标题翻译：金属电熔丝的结构
公开(公告)号：US08299567B2
公开(公告)日：2012-10-30
申请号：US12952317
申请日：2010-11-23
申请人： Ping-Chuan Wang , Chunyan E Tian , Ronald Filippi , Wai-kin Li
发明人： Ping-Chuan Wang , Chunyan E Tian , Ronald Filippi , Wai-kin Li
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Structures of electronic fuses (e-fuse) are provided. An un-programmed e-fuse includes a via of a first conductive material having a bottom and sidewalls with a portion of the sidewalls being covered by a conductive liner and the bottom of the via being formed on top of a dielectric layer, and a first and a second conductive path of a second conductive material formed on top of the dielectric layer with the first and second conductive paths being conductively connected through, and only through, the via at the sidewalls. A programmed e-fuse includes a via; a first conductive path at a first side of the via and being separated from sidewalls of the via by a void; and a second conductive path at a second different side of the via and being in conductive contact with the via through sidewalls of the via.
摘要翻译：提供电子保险丝（e-fuse）的结构。未编程的电子熔断器包括具有底部和侧壁的第一导电材料的通孔，侧壁的一部分被导电衬垫覆盖，并且通孔的底部形成在电介质层的顶部上，并且第一以及形成在电介质层顶部上的第二导电材料的第二导电路径，其中第一和第二导电路径通过侧壁导通地连接，并且仅通过通孔。编程的电子熔丝包括通孔; 在通孔的第一侧处的第一导电路径，并且通过空隙与通路的侧壁分离; 以及在所述通孔的第二不同侧的第二导电路径，并且与通孔通过所述通孔的侧壁导电接触。

25. 发明授权

US08164190B2 Structure of power grid for semiconductor devices and method of making the same 有权
标题翻译：半导体器件电网结构及其制作方法
公开(公告)号：US08164190B2
公开(公告)日：2012-04-24
申请号：US12491372
申请日：2009-06-25
申请人： Ronald Filippi , Wai-kin Li , Ping-Chuan Wang
发明人： Ronald Filippi , Wai-kin Li , Ping-Chuan Wang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76847 , H01L21/76852 , H01L23/5286 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided.
摘要翻译：本发明的一个实施例提供一种半导体结构，其可以包括形成在电介质层内部的第一导电材料的支柱; 具有底部的第二导电材料的通孔和具有底部的侧壁，并且侧壁被导电衬垫覆盖，并且底部直接形成在螺柱的顶部上并且通过导电衬套与通孔接触; 以及一个或多个第三导电材料的导电路径，所述第三导电材料在所述导电衬套的侧壁处通过导电衬套连接到通孔。还提供了制造半导体结构的方法。

26. 发明申请

US20050116342A1 Device interconnection 审中-公开
公开(公告)号：US20050116342A1
公开(公告)日：2005-06-02
申请号：US11024067
申请日：2004-12-28
申请人： Lawrence Clevenger , Ronald Filippi , Mark Hoinkis , Jeffery Hurd , Roy Iggulden , Herbert Palm , Hans Poetzlberger , Kenneth Rodbell , Florian Schnabel , Stefan Weber , Ebrahim Mehter
发明人： Lawrence Clevenger , Ronald Filippi , Mark Hoinkis , Jeffery Hurd , Roy Iggulden , Herbert Palm , Hans Poetzlberger , Kenneth Rodbell , Florian Schnabel , Stefan Weber , Ebrahim Mehter
IPC分类号： H01L21/28 , H01L21/768 , H01L23/485 , H01L23/532 , H01L21/44 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76849 , H01L21/76876 , H01L23/485 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A conductor for interconnecting integrated circuit components having improved reliability. The conductor includes a liner surrounding at least three surfaces of the conductor, producing a low textured conductor. It has been found that low textured conductor results in improved electromigration lifetime.

27. 发明申请

US20050086628A1 Method of extracting properties of back end of line (BEOL) chip architecture 失效
标题翻译：提取后端（BEOL）芯片架构性能的方法
公开(公告)号：US20050086628A1
公开(公告)日：2005-04-21
申请号：US10687475
申请日：2003-10-16
申请人： Ronald Filippi , Giovanni Fiorenza , Xiao Liu , Conal Murray , Gregory Northrop , Thomas Shaw , Richard Wachnik , Mary Yvonne Wisniewski
发明人： Ronald Filippi , Giovanni Fiorenza , Xiao Liu , Conal Murray , Gregory Northrop , Thomas Shaw , Richard Wachnik , Mary Yvonne Wisniewski
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5018
摘要： A method for analyzing circuit designs includes discretizing a design representation into pixel elements representative of a structure in the design and determining at least one property for each pixel element representing a portion of the design. Then, a response of the design is determined due to local properties across the design.
摘要翻译：用于分析电路设计的方法包括将设计表示离散成代表设计中的结构的像素元素，并且为表示设计的一部分的每个像素元素确定至少一个属性。然后，由于设计中的局部属性，确定了设计的响应。

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