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21. 发明申请

US20050041514A1 Low-power consumption semiconductor memory device 失效
标题翻译：低功耗半导体存储器件
公开(公告)号：US20050041514A1
公开(公告)日：2005-02-24
申请号：US10949365
申请日：2004-09-27
申请人： Takeshi Fujino , Kazutami Arimoto , Hiroki Shimano
发明人： Takeshi Fujino , Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C11/405 , G11C7/12 , G11C11/409 , G11C11/4094 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C5/00
CPC分类号： G11C11/4094 , G11C7/12
摘要： A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.
摘要翻译：存储单元单元包括用于彼此存储互补数据的第一存储元件和第二存储元件。在选择状态下，第一和第二存储元件分别连接到互补位线。在待机状态下，位线被预充电到对应于存储在存储单元单元中的数据的电压（Vcc或GND）。可以实现即使在低电源电压下稳定运行的无刷新，低电流消耗的半导体存储器件。

22. 发明授权

US06744684B2 Semiconductor memory device with simple refresh control 有权
公开(公告)号：US06744684B2
公开(公告)日：2004-06-01
申请号：US09777694
申请日：2001-02-07
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C700
CPC分类号： G11C11/40615 , G11C11/406 , G11C2207/104
摘要： A self refresh timer is set constantly to an operation state to render a refresh request signal FAY active periodically. When contention occurs between the refresh request signal FAY and an externally applied read or write command, a row selection related circuit/command generation related circuit controls a row related control signal so that a refresh operation is carried out after, for example, the read or write operation ends. A submemory array SMA is divided more small than that of the conventional case, and the refresh cycle ends in a shorter period of time. Therefore, a read operation and a refresh operation can be completed within a read cycle time. A DRAM core that can be employed with control as simple as that of an SRAM can be realized.

23. 发明授权

US06483139B1 Semiconductor memory device formed on semiconductor substrate 有权
标题翻译：形成在半导体衬底上的半导体存储器件
公开(公告)号：US06483139B1
公开(公告)日：2002-11-19
申请号：US09983294
申请日：2001-10-23
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： H01L2976
CPC分类号： G11C11/4085 , G11C11/4076 , G11C2207/2281 , H01L27/10805
摘要： In a memory cell contained in a memory circuit portion of a system LSI, a gate electrode of an N-channel MOS transistor and a cell plate electrode of a capacitor are formed by the same interconnection layer. Thus, the system LSI can be produced using the CMOS logic process alone so that the system LSI including the memory circuit portion having a relatively large capacity can be produced at a low cost.
摘要翻译：在包含在系统LSI的存储电路部分的存储单元中，N沟道MOS晶体管的栅电极和电容器的单元板电极由相同的互连层形成。因此，可以仅使用CMOS逻辑处理来制造系统LSI，从而可以以低成本制造包括具有相对大容量的存储器电路部分的系统LSI。

24. 发明授权

US06459113B1 Semiconductor integrated circuit device and method of manufacturing the same, and cell size calculation method for DRAM memory cells 失效
标题翻译：半导体集成电路器件及其制造方法，以及DRAM存储单元的单元尺寸计算方法
公开(公告)号：US06459113B1
公开(公告)日：2002-10-01
申请号：US09760804
申请日：2001-01-17
申请人： Toshinori Morihara , Hiroki Shimano , Kazutami Arimoto
发明人： Toshinori Morihara , Hiroki Shimano , Kazutami Arimoto
IPC分类号： H01L27108
CPC分类号： H01L27/10805 , H01L27/0207
摘要： There is provided a semiconductor integrated circuit device comprising: a field placement creating a field pattern in an array form by closest packing on a first conductance-type semiconductor substrate, the field pattern including a plurality of memory cells which define an active area and a device isolation region of a field effect transistor, and which are arranged in a predetermined pitch in the longitudinal and transverse directions, respectively, each memory cell having a pattern of a certain length-to-width size; a cell plate placement providing a capacitor structure between a second conductance-type diffusion region formed by an impurity implant to the active area and a cell plate electrode formed so as to cover part of the active area with a predetermined cell plate pattern through a capacitor dielectric, the cell plate pattern extending in the transverse direction with a certain length size; and a word line placement in which a word line pattern is arranged in the transverse direction of a vacant zone of the active area in which the cell plate electrode is not formed and serves as a gate electrode of the field effect transistor on the active area, the word line pattern being formed through a gate oxide at a predetermined interval, wherein the layout of a cell array of the memory cells is provided by a closest packing cell configuration.
摘要翻译：提供了一种半导体集成电路器件，包括：场放置，通过在第一导电型半导体衬底上的最密堆积产生阵列形式的场图案，场图案包括限定有源区域的多个存储单元和器件隔离区域，并且分别以纵向和横向方向以预定间距布置，每个存储单元具有一定长度至宽度尺寸的图案; 在通过杂质注入形成的第二电导型扩散区域与有源区域之间提供电容器结构的单元板布置和通过电容器电介质以预定的单元板图案覆盖部分有源区域形成的单元板电极，细胞板图案以一定的长度尺寸在横向上延伸; 以及字线图案，其中在没有形成单元板电极的有源区域的空白区域的横向上布置字线图案，并且用作有源区域上的场效应晶体管的栅电极，所述字线图案是以预定间隔通过栅极氧化物形成的，其中所述存储单元的单元阵列的布局由最接近的封装单元配置提供。

25. 发明授权

US06404684B2 Test interface circuit and semiconductor integrated circuit device including the same 失效
标题翻译：测试接口电路和包括其的半导体集成电路器件
公开(公告)号：US06404684B2
公开(公告)日：2002-06-11
申请号：US09741147
申请日：2000-12-21
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C700
CPC分类号： G01R31/3172 , G01R31/31723 , G11C29/1201 , G11C29/12015 , G11C29/14 , G11C29/28 , G11C29/48 , G11C2029/0401
摘要： In a test interface circuit arranged between an embedded memory and a test data input/output (I/O) terminal, a first-in first-out circuit for successively storing test data is arranged for controlling a latency of data read from the embedded memory. The test interface circuit for the embedded memory can reduce the number of test data I/O terminals, and can increase the executable test patterns.
摘要翻译：在布置在嵌入式存储器和测试数据输入/输出（I / O））端子之间的测试接口电路中，布置用于连续存储测试数据的先进先出电路，用于控制从嵌入式存储器读取的数据的等待时间。用于嵌入式存储器的测试接口电路可以减少测试数据I / O端子的数量，并且可以增加可执行测试模式。

26. 发明授权

US06377483B1 Semiconductor memory device having improved memory cell and bit line pitch 失效
公开(公告)号：US06377483B1
公开(公告)日：2002-04-23
申请号：US09769416
申请日：2001-01-26
申请人： Kazutami Arimoto , Hiroki Shimano , Toshinori Morihara
发明人： Kazutami Arimoto , Hiroki Shimano , Toshinori Morihara
IPC分类号： G11C1124
CPC分类号： G11C5/063 , G11C7/18 , G11C8/14 , H01L27/10897
摘要： Tow bit lines are arranged in each column in which memory cells are disposed. For selecting a first group sub-word line, only a sense amplifier on one sense amplifier band is activated and for selecting a second group sub-word line, only a sense amplifier on the other sense amplifier band is activated. A storage node is formed under a bit line.

27. 发明授权

US08274841B2 Semiconductor signal processing device 有权
公开(公告)号：US08274841B2
公开(公告)日：2012-09-25
申请号：US13354028
申请日：2012-01-19
申请人： Hiroki Shimano , Kazutami Arimoto
发明人： Hiroki Shimano , Kazutami Arimoto
IPC分类号： G11C7/00 , G11C7/22
CPC分类号： G11C8/04 , G11C8/12 , G11C11/1675 , G11C11/405 , G11C11/4076 , G11C11/5607 , G11C15/02 , G11C15/046 , G11C2211/4016 , H01L27/0207 , H01L27/1203
摘要： A unit operator cell includes a plurality of SOI (Silicon on Insulator) transistors, write data is stored in a body region of at least two SOI transistors, and the storage SOI transistors are connected in series with each other to a read port or each of the storage SOI transistors is singly connected to the read port. Therefore, an AND operation result or a NOT operation result of data stored in the unit operator cells can be obtained, and operation processing can be performed only by writing and reading data. A semiconductor signal processing device that can perform logic operation processing and arithmetic operation processing at high speed is implemented with low power consumption and a small occupation area.

28. 发明申请

US20110085364A1 SEMICONDUCTOR SIGNAL PROCESSING APPARATUS 失效
标题翻译：半导体信号处理设备
公开(公告)号：US20110085364A1
公开(公告)日：2011-04-14
申请号：US12900915
申请日：2010-10-08
申请人： Hiroki Shimano , Kazutami Arimoto
发明人： Hiroki Shimano , Kazutami Arimoto
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： A pair of operator cells each having a series-coupled circuit of first and second transistors is used as a storage unit. To-be-retrieved data and retrieval data are respectively stored in the first and second transistors, and mutually complementary data items are stored in the operator cells of the storage unit. The operator cells supply currents according to the result of an AND operation between the stored data items to corresponding bit lines, and the read data from the storage unit corresponds to the result of an EXOR operation between the retrieval data and the to-be-retrieved data. The currents flowing in the corresponding bit lines are amplified with sense amplifier circuits to drive local match lines. In the individual sub-blocks of an operator cell array, data items having different pattern lengths can be stored. The potentials of the local match lines are selected according to the data pattern lengths, and match retrieval is performed for the data items having the different pattern lengths.
摘要翻译：每个具有第一和第二晶体管的串联耦合电路的一对操作单元被用作存储单元。待检索的数据和检索数据分别存储在第一和第二晶体管中，相互补充的数据项存储在存储单元的操作员单元中。操作员单元根据存储的数据项与对应的位线之间的AND运算结果来提供电流，并且来自存储单元的读取数据对应于检索数据和待检索的EXOR操作的结果数据。在对应位线中流动的电流用读出放大器电路放大，以驱动局部匹配线。在操作员单元阵列的各个子块中，可以存储具有不同图案长度的数据项。根据数据图案长度选择局部匹配线的电位，并且对具有不同图案长度的数据项执行匹配检索。

29. 发明授权

US07738312B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07738312B2
公开(公告)日：2010-06-15
申请号：US12000343
申请日：2007-12-12
申请人： Hiroki Shimano , Fukashi Morishita , Kazutami Arimoto
发明人： Hiroki Shimano , Fukashi Morishita , Kazutami Arimoto
IPC分类号： G11C8/00
CPC分类号： G11C8/16 , G11C5/063 , G11C7/12 , G11C7/18 , G11C11/405 , G11C11/4094 , G11C11/4097 , G11C2211/4016 , H01L21/84 , H01L27/0207 , H01L27/108 , H01L27/10802 , H01L27/1203 , H01L29/7841
摘要： One memory cell is formed of a first port access transistor, a second port access transistor and a storage transistor coupled commonly to these access transistors. The first port access transistor is coupled to a first electrode of the storage transistor, and the second port access transistor is coupled to a third electrode of the storage transistor. These first and second port access transistors enter a selected state when first and second port word lines are selected, respectively, to couple corresponding second and third electrodes of the corresponding storage transistor to first and second port bit lines, respectively. A dual-port memory cell of which scalability can follow miniaturization in a process can be provided.
摘要翻译：一个存储单元由第一端口存取晶体管，第二端口存取晶体管和与这些存取晶体管共同耦合的存储晶体管形成。第一端口存取晶体管耦合到存储晶体管的第一电极，第二端口存取晶体管耦合到存储晶体管的第三电极。当分别选择第一和第二端口字线时，这些第一和第二端口存取晶体管进入选择状态，以将相应的存储晶体管的相应的第二和第三电极分别耦合到第一和第二端口位线。可以提供一种双端口存储单元，其可扩展性可以在一个过程中跟随小型化。

30. 发明授权

US07248495B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07248495B2
公开(公告)日：2007-07-24
申请号：US11397811
申请日：2006-04-05
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C11/24
CPC分类号： G11C7/18 , G11C8/14 , G11C11/4085 , G11C11/4087 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/108 , H01L27/1085 , H01L27/10873 , H01L27/10882
摘要： Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.
摘要翻译：构成存储单元板的导体线的导电线和构成存储单元板电极的导线被形成在包括多个存储单元的存储器件的同一互连层中，每个存储单元均包括用于以电荷形式存储数据的电容器。通过将存储单元的电容器形成为平面电容器配置，由于电容器而导致的步骤被去除。因此，可以通过CMOS工艺形成动态半导体存储器件，并且实现适合于与逻辑合并的动态半导体存储器件。 1位的数据由两个存储单元存储，即使由于平面型电容器而使存储单元的电容值减小，也可以可靠地存储数据。

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