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21. 发明授权

US08059465B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08059465B2
公开(公告)日：2011-11-15
申请号：US12571800
申请日：2009-10-01
申请人： Katsuaki Isobe , Masatsugu Kojima
发明人： Katsuaki Isobe , Masatsugu Kojima
IPC分类号： G11C11/34
CPC分类号： G11C16/30 , G11C16/225
摘要： When a voltage level detector detects that a supply voltage reaches a recovery voltage level that requires a recovery operation, a signal generator generates a recovery operation instructing signal for instructing the recovery operation. The recovery operation instructing signal is invalidated if a certain operation mode is executed and validated in other cases.
摘要翻译：当电压电平检测器检测到电源电压达到需要恢复操作的恢复电压电平时，信号发生器产生用于指示恢复操作的恢复操作指令信号。如果某些操作模式在其他情况下被执行和验证，则恢复操作指令信号无效。

22. 发明申请

US20110211395A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110211395A1
公开(公告)日：2011-09-01
申请号：US13036525
申请日：2011-02-28
申请人： Makoto MIAKASHI , Katsuaki Isobe , Noboru Shibata
发明人： Makoto MIAKASHI , Katsuaki Isobe , Noboru Shibata
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3436
摘要： A semiconductor memory device, in which interference between adjoining cells can be reduced and an expansion of a chip area can be suppressed, comprising: a memory cell array in which plural memory cells connected to plural word lines and plural bit lines are disposed in a matrix form; sense amplifiers each of which is to be connected to each of the bit lines; a control circuit which controls voltages of the word lines and the bit lines, and programs data into the memory cells or reads data from the memory cells; wherein the plural bit lines include at least a first, a second, a third and a fourth bit lines adjoining to each other, and the sense amplifiers include at least a first and a second sense amplifiers, a first and a fourth selection transistors which are provided between the first and the fourth bit lines and the first sense amplifier, and connect the first and the fourth bit lines to the first sense amplifier; and a second and a third selection transistors which are provided between the second and the third bit lines and the second sense amplifier, and connect the second and the third bit lines to the second sense amplifier.
摘要翻译：一种半导体存储器件，其中可以减少相邻单元之间的干扰并且可以抑制芯片面积的扩大，其包括：存储单元阵列，其中连接到多个字线和多个位线的多个存储器单元被布置在矩阵中形成; 读出放大器中的每一个将连接到每个位线; 控制电路，其控制字线和位线的电压，并将数据编程到存储器单元中或从存储器单元读取数据; 其中所述多个位线至少包括彼此相邻的第一，第二，第三和第四位线，并且所述读出放大器至少包括第一和第二读出放大器，第一和第四选择晶体管是设置在第一和第四位线与第一读出放大器之间，并将第一和第四位线连接到第一读出放大器; 以及设置在第二和第三位线和第二读出放大器之间的第二和第三选择晶体管，并将第二和第三位线连接到第二读出放大器。

23. 发明授权

US07961516B2 NAND flash memory and memory system 失效
标题翻译： NAND闪存和内存系统
公开(公告)号：US07961516B2
公开(公告)日：2011-06-14
申请号：US12327136
申请日：2008-12-03
申请人： Katsuaki Isobe
发明人： Katsuaki Isobe
IPC分类号： G11C11/34
CPC分类号： G11C8/12 , G11C8/08 , G11C11/5621 , G11C16/3418 , G11C16/3431 , G11C29/00
摘要： A NAND flash memory comprising blocks which are units of writing and deletion of data, the block comprising: memory cells from which data corresponding to values of held threshold voltages can be read by applying a reading voltage to control gates of the memory cells; source-side selection gate transistors connected between a common source line and the memory cells; drain-side selection gate transistors connected between a bit line and the memory cells; and monitor cells which are configured as the memory cells and have a threshold voltage set according to monitor data, and from which data corresponding to values of held threshold voltages can be read by applying a decision voltage to control gates of the monitor cells.
摘要翻译：一种NAND闪存，包括作为写入和删除数据的单元的块，所述块包括：存储单元，通过对所述存储单元的控制栅施加读取电压，可读取与保持的阈值电压的值对应的数据; 连接在公共源极线与存储器单元之间的源极侧选择栅极晶体管; 连接在位线和存储单元之间的漏极侧选择栅极晶体管; 并且监视被配置为存储单元并且根据监视数据设置阈值电压的单元，并且可以通过向控制监视单元的控制门施加判定电压来读取与保持的阈值电压的值相对应的数据。

24. 发明授权

US07907436B2 Nonvolatile semiconductor storage device and data writing method therefor 有权
标题翻译：非易失性半导体存储器件及其数据写入方法
公开(公告)号：US07907436B2
公开(公告)日：2011-03-15
申请号：US12370111
申请日：2009-02-12
申请人： Hiroshi Maejima , Katsuaki Isobe , Hideo Mukai
发明人： Hiroshi Maejima , Katsuaki Isobe , Hideo Mukai
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C7/00 , G11C13/0004 , G11C13/0011 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2213/31 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A nonvolatile semiconductor storage device includes: a first wire and a second wire intersecting each other; a memory cell which is disposed at each intersection of the first wire and the second wire and electrically rewritable and in which a variable resistor for memorizing a resistance value as data in a nonvolatile manner and a rectifying device are connected in series; and a control circuit which applies a voltage necessary for writing of data to the first and second wires. The control circuit precharges a non-selected second wire up to a standby voltage larger than a reference voltage prior to a set operation for programming only a variable resistor connected to selected first and second wires by supplying the reference voltage to a non-selected first wire and the selected second wire, applying a program voltage necessary for programming of the selected variable resistor based on the reference voltage to the selected first wire and applying a control voltage which prevents the rectifying device from turning ON based on the program voltage to the non-selected second wire.
摘要翻译：非易失性半导体存储装置包括：第一线和彼此交叉的第二线; 存储单元，其配置在所述第一配线和所述第二配线的各交叉点并且是电可重写的，并且其中存储用作非易失性数据的电阻值的可变电阻器和整流装置串联连接; 以及控制电路，其向第一和第二导线施加写入数据所需的电压。控制电路在设置操作之前将未选择的第二线预充电到大于参考电压的待机电压，以仅通过将参考电压提供给未选择的第一线来仅编程连接到所选择的第一和第二线的可变电阻器和所选择的第二线路，基于参考电压将所选择的可变电阻器编程所需的编程电压施加到所选择的第一线路，并施加防止整流装置导通的控制电压，选择第二根线。

25. 发明授权

US07616493B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07616493B2
公开(公告)日：2009-11-10
申请号：US11763489
申请日：2007-06-15
申请人： Katsuaki Isobe , Masatsugu Kojima
发明人： Katsuaki Isobe , Masatsugu Kojima
IPC分类号： G11C16/04
CPC分类号： G11C16/30 , G11C16/225
摘要： When a voltage level detector detects that a supply voltage reaches a recovery voltage level that requires a recovery operation, a signal generator generates a recovery operation instructing signal for instructing the recovery operation. The recovery operation instructing signal is invalidated if a certain operation mode is executed and validated in other cases.
摘要翻译：当电压电平检测器检测到电源电压达到需要恢复操作的恢复电压电平时，信号发生器产生用于指示恢复操作的恢复操作指令信号。如果某些操作模式在其他情况下被执行和验证，则恢复操作指令信号无效。

26. 发明申请

US20090141553A1 SEMICONDUCTOR STORAGE DEVICE PROVIDED WITH MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE 有权
标题翻译：具有电荷积累层和控制栅的存储单元提供的半导体存储器件
公开(公告)号：US20090141553A1
公开(公告)日：2009-06-04
申请号：US12365590
申请日：2009-02-04
申请人： Katsuaki Isobe , Noboru Shibata
发明人： Katsuaki Isobe , Noboru Shibata
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5635 , G11C16/12 , G11C16/16 , G11C16/3418
摘要： A semiconductor memory device includes memory cell transistors, a first selection transistor, and word lines. Each of the memory cell transistors has a stacked gate including a charge accumulation layer and a control gate, and is configured to retain at least two levels of “0” data and “1” data according to a threshold voltage. The threshold voltage corresponding to the “0” data being the lowest threshold voltage in the levels retained by each of the memory cell transistors. The first selection transistor has a current path connected in series to one of the memory cell transistors. Each of the word lines is connected to the control gate of one of the memory cell transistors. upper limit values of threshold voltages of the memory cell transistors retaining the “0” data being different from one another in each word line.
摘要翻译：半导体存储器件包括存储单元晶体管，第一选择晶体管和字线。每个存储单元晶体管具有包括电荷累积层和控制栅极的堆叠栅极，并且被配置为根据阈值电压保持至少两个级别的“0”数据和“1”数据。对应于“0”数据的阈值电压是由每个存储单元晶体管保持的电平中的最低阈值电压。第一选择晶体管具有与存储单元晶体管之一串联连接的电流通路。每个字线连接到存储单元晶体管之一的控制栅极。保持“0”数据的存储单元晶体管的阈值电压的上限值在每个字线中彼此不同。

27. 发明授权

US07388790B2 Semiconductor memory device and dynamic latch refresh method thereof 有权
标题翻译：半导体存储器件及其动态锁存刷新方法
公开(公告)号：US07388790B2
公开(公告)日：2008-06-17
申请号：US11510733
申请日：2006-08-28
申请人： Hiroshi Maejima , Noboru Shibata , Katsuaki Isobe
发明人： Hiroshi Maejima , Noboru Shibata , Katsuaki Isobe
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G11C16/0483 , G11C29/70 , G11C29/832 , G11C2211/565 , H01L27/105 , H01L27/115
摘要： A semiconductor integrated circuit device includes dynamic latches, switch circuit, capacitor, first static latch, and first transfer gate. In refreshing data of the dynamic latches, data stored in the first static latch is moved to the second node through the first transfer gate and saved. The data of the dynamic latch is bootstrapped. The bootstrapped data is transferred to the first node to distribute charges, thereby setting the potential of the first node. The set potential is written back to the dynamic latch to refresh it. The saved data of the second node is moved to the first node through the first transfer gate and written back to the first static latch.
摘要翻译：半导体集成电路器件包括动态锁存器，开关电路，电容器，第一静态锁存器和第一传输门。在动态锁存器的刷新数据中，存储在第一静态锁存器中的数据通过第一传送门移动到第二节点并被保存。动态锁存器的数据被自举。自举数据被传送到第一节点以分配费用，从而设置第一节点的电位。设置电位被写回到动态锁存器来刷新它。第二节点的保存数据通过第一传输门移动到第一节点并写回到第一静态锁存器。

28. 发明授权

US07236409B2 Semiconductor memory device provided with constant-current circuit having current trimming function 失效
标题翻译：具有具有电流修整功能的恒流电路的半导体存储器件
公开(公告)号：US07236409B2
公开(公告)日：2007-06-26
申请号：US11045383
申请日：2005-01-31
申请人： Katsuaki Isobe
发明人： Katsuaki Isobe
IPC分类号： G11C7/00
CPC分类号： G11C29/028 , G11C29/02 , G11C2029/5006
摘要： A semiconductor memory device includes a memory cell unit including at least one semiconductor memory cell, a voltage generating circuit which produces an operating voltage to which reference is made in performing a predetermined operation on the memory cell unit. The device further includes a constant-current circuit capable of a current trimming operation and adapted to supply a constant current to the voltage generating circuit.
摘要翻译：半导体存储器件包括存储单元单元，该存储单元单元包括至少一个半导体存储单元，产生电路的电压产生电路，该电压产生电路在对存储单元单元执行预定操作时进行参考。该装置还包括能够进行电流调整操作并适于向电压产生电路提供恒定电流的恒流电路。

29. 发明授权

US07190234B2 Current supply circuit, ring oscillator, nonvolatile semiconductor device and electronic card and electronic device 失效
标题翻译：电流供应电路，环形振荡器，非易失性半导体器件和电子卡及电子器件
公开(公告)号：US07190234B2
公开(公告)日：2007-03-13
申请号：US10930801
申请日：2004-09-01
申请人： Katsuaki Isobe
发明人： Katsuaki Isobe
IPC分类号： H03L7/099
CPC分类号： H03K3/0322 , G11C16/30 , H03K3/011
摘要： A current supply circuit is disclosed, which comprises a first circuit configured to generate a first current having a positive dependence with respect to a power supply voltage and not depending upon a variation in temperature and in threshold value of a transistor used, a second circuit configured to generate a second current having a positive dependence greater than that of the first current with respect to the power supply voltage and not depending upon a variation in temperature and in threshold value of a transistor used, and a third circuit configured to subtract the second current form the first current to generate a third current having a negative dependence with respect to the power supply voltage.
摘要翻译：公开了一种电流供应电路，其包括第一电路，其被配置为产生相对于电源电压具有正依赖性的第一电流，并且不依赖于所使用的晶体管的温度变化和阈值，第二电路配置产生相对于电源电压具有大于第一电流的正相关性的第二电流，而不是依赖于所使用的晶体管的温度变化和阈值，以及第三电路，被配置为减去第二电流形成第一电流以产生相对于电源电压具有负依赖性的第三电流。

30. 发明申请

US20050088245A1 Current supply circuit, ring oscillator, nonvolatile semiconductor device and electronic card and electronic device 失效
标题翻译：电流供应电路，环形振荡器，非易失性半导体器件和电子卡及电子器件
公开(公告)号：US20050088245A1
公开(公告)日：2005-04-28
申请号：US10930801
申请日：2004-09-01
申请人： Katsuaki Isobe
发明人： Katsuaki Isobe
IPC分类号： G11C16/06 , G05F3/24 , G05F3/26 , G11C16/30 , H03K3/011 , H03K3/03 , H03B1/00 , H03L5/00
CPC分类号： H03K3/0322 , G11C16/30 , H03K3/011
摘要： A current supply circuit is disclosed, which comprises a first circuit configured to generate a first current having a positive dependence with respect to a power supply voltage and not depending upon a variation in temperature and in threshold value of a transistor used, a second circuit configured to generate a second current having a positive dependence greater than that of the first current with respect to the power supply voltage and not depending upon a variation in temperature and in threshold value of a transistor used, and a third circuit configured to subtract the second current form the first current to generate a third current having a negative dependence with respect to the power supply voltage.
摘要翻译：公开了一种电流供应电路，其包括第一电路，其被配置为产生相对于电源电压具有正依赖性的第一电流，并且不依赖于所使用的晶体管的温度变化和阈值，第二电路配置产生相对于电源电压具有大于第一电流的正相关性的第二电流，而不是依赖于所使用的晶体管的温度变化和阈值，以及第三电路，被配置为减去第二电流形成第一电流以产生相对于电源电压具有负依赖性的第三电流。

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