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21. 发明授权

US09882737B2 Network system 有权
公开(公告)号：US09882737B2
公开(公告)日：2018-01-30
申请号：US14003518
申请日：2012-01-19
申请人： Jun Suzuki , Youichi Hidaka , Junichi Higuchi , Takashi Yoshikawa , Teruyuki Baba , Nobuharu Kami
发明人： Jun Suzuki , Youichi Hidaka , Junichi Higuchi , Takashi Yoshikawa , Teruyuki Baba , Nobuharu Kami
IPC分类号： H04L12/40 , H04L12/26 , G06F13/38
CPC分类号： H04L12/40 , G06F13/385 , G06F2213/0026 , G06F2213/3808 , H04L43/0817
摘要： A network system of the present invention includes a computer and a device connected via a network, and a system management device. The computer and the device include, respectively, bridges that encapsulate transmission/reception data transmitted and received to and from each other and transmit and receive the data to and from each other via the network. Each of the bridges includes a control data transmitting means for generating control data for controlling the state of the system based on control auxiliary data issued from the computer or the device and used for controlling the state of the system, and transmitting the control data to the system management device via the network. The system management device includes a system controlling means for controlling the state of the system in accordance with the control data received thereby.

22. 发明申请

US20120263182A1 Communication Apparatus, Communication System, Absent Packet Detecting Method and Absent Packet Detecting Program 审中-公开
标题翻译：通信设备，通信系统，缺席分组检测方法和缺席分组检测程序
公开(公告)号：US20120263182A1
公开(公告)日：2012-10-18
申请号：US13531637
申请日：2012-06-25
申请人： Nobuyuki Enomoto , Hideyuki Shimonishi , Junichi Higuchi , Youichi Hidaka , Jun Suzuki , Takashi Yoshikawa
发明人： Nobuyuki Enomoto , Hideyuki Shimonishi , Junichi Higuchi , Youichi Hidaka , Jun Suzuki , Takashi Yoshikawa
IPC分类号： H04L12/56
CPC分类号： H04L1/1841 , H04L1/1874 , H04L1/188 , H04L45/24 , H04L45/28 , H04L2001/0096
摘要： Any packet loss is detected very quickly by means of only a series of sequence number in a multi-path environment where a transmitter and a receiver are connected to each other by way of a plurality of networks when no inversion of sequence arises in any of the networks. A communication apparatus includes a plurality of sequence buffers arranged at each network to accumulate packets until a sequence acknowledgement and an absence detecting section adapted to determine the occurrence of an absence of a packet when one or more packets are accumulated in all the sequence buffers. With this arrangement, the absence detecting section of the receiver monitors the packets staying in the sequence guaranteeing buffer arranged in each of the network, paying attention to the characteristic that packets are stored in the sequence buffers of all the networks when a packet loss takes place.
摘要翻译：在多路径环境中只有一系列的序列号，任何分组丢失被非常快速地检测到，其中发射机和接收机通过多个网络彼此连接，当序列的任何网络。通信装置包括布置在每个网络处的多个序列缓冲器，用于累积分组，直到序列确认和不存在检测部分适于在所有序列缓冲器中累积一个或多个分组时确定是否存在分组。利用这种安排，接收机的缺席检测部分监视保留在每个网络中的序列保证缓冲器中的数据包，注意发生分组丢失时分组存储在所有网络的序列缓冲器中的特性。

23. 发明申请

US20100180062A1 INTERNET CONNECTION SWITCH AND INTERNET CONNECTION SYSTEM 有权
标题翻译：互联网连接开关和互联网连接系统
公开(公告)号：US20100180062A1
公开(公告)日：2010-07-15
申请号：US12376609
申请日：2007-08-08
申请人： Youichi Hidaka , Jun Suzuki , Junichi Higuchi , Takashi Yoshikawa
发明人： Youichi Hidaka , Jun Suzuki , Junichi Higuchi , Takashi Yoshikawa
IPC分类号： G06F13/36 , G06F13/00
CPC分类号： G06F13/4022
摘要： A switch (304) includes a plurality of bridges (3041, 3042, 3043, 3044, 3045) and a switch forwarding mechanism (20). Each of the bridges transmits and receives a TLP frame complying with PCI express to and from a device connected to each of the bridges. The switch forwarding mechanism includes a plurality of ports (1, 2, 3, 4, 5) to which the bridges are connected, respectively, selects an output port in dependence on a combination of destination information on the TLP frame input from one of the plurality of ports and the port which input the TLP frame, and outputs the TLP frame from the selected output port.
摘要翻译：开关（304）包括多个桥（3041,3042,3043,3044,3045）和开关转发机构（20）。每个桥接器向连接到每个桥接器的设备发送和接收符合PCI express的TLP帧。交换机转发机制包括分别连接到所述网桥的多个端口（1,2,3,4,5），根据从其中一个桥接器输入的TLP帧上的目的地信息的组合，选择输出端口多个端口和输入TLP帧的端口，并从所选择的输出端口输出TLP帧。

24. 发明申请

US20090059928A1 COMMUNICATION APPARATUS, COMMUNICATION SYSTEM, ABSENT PACKET DETECTING METHOD AND ABSENT PACKET DETECTING PROGRAM 有权
标题翻译：通信设备，通信系统，无需分组检测方法和无需分组检测程序
公开(公告)号：US20090059928A1
公开(公告)日：2009-03-05
申请号：US12200508
申请日：2008-08-28
申请人： Nobuyuki Enomoto , Hideyuki Shimonishi , Junichi Higuchi , Youichi Hidaka , Jun Suzuki , Takashi Yoshikawa
发明人： Nobuyuki Enomoto , Hideyuki Shimonishi , Junichi Higuchi , Youichi Hidaka , Jun Suzuki , Takashi Yoshikawa
IPC分类号： H04L12/56
CPC分类号： H04L1/1841 , H04L1/1874 , H04L1/188 , H04L45/24 , H04L45/28 , H04L2001/0096
摘要： Any packet loss is detected very quickly by means of only a series of sequence number in a multi-path environment where a transmitter and a receiver are connected to each other by way of a plurality of networks when no inversion of sequence arises in any of the networks. A communication apparatus includes a plurality of sequence buffers arranged at each network to accumulate packets until a sequence acknowledgement and an absence detecting section adapted to determine the occurrence of an absence of a packet when one or more packets are accumulated in all the sequence buffers. With this arrangement, the absence detecting section of the receiver monitors the packets staying in the sequence guaranteeing buffer arranged in each of the network, paying attention to the characteristic that packets are stored in the sequence buffers of all the networks when a packet loss takes place.
摘要翻译：在多路径环境中只有一系列的序列号，任何分组丢失被非常快速地检测到，其中发射机和接收机通过多个网络彼此连接，当序列的任何网络。通信装置包括布置在每个网络处的多个序列缓冲器，用于累积分组，直到序列确认和不存在检测部分适于在所有序列缓冲器中累积一个或多个分组时确定是否存在分组。利用这种安排，接收机的不存在检测部分监视保留在每个网络中的序列保证缓冲器中的数据包，注意发生分组丢失时分组存储在所有网络的序列缓冲器中的特性。

25. 发明授权

US08352667B2 I/O connection system and I/O connection method 有权
标题翻译： I / O连接系统和I / O连接方式
公开(公告)号：US08352667B2
公开(公告)日：2013-01-08
申请号：US12739843
申请日：2008-10-27
申请人： Jun Suzuki , Youichi Hidaka , Takashi Yoshikawa
发明人： Jun Suzuki , Youichi Hidaka , Takashi Yoshikawa
IPC分类号： G06F13/36
CPC分类号： G06F13/4027 , H04L41/0806 , H04L41/0853
摘要： Upstream network interfaces (2-1-2-N) and downstream network interfaces (5-1-5-M) have an upstream PCI-PCI bridge function and a downstream PCI-PCI bridge function, respectively. These network interfaces (2-1-2-N, 5-1-5-M) and a network (3) are incorporated in a system as a single multi-root PCI express switch. The network (3) tunnels TLPs (Transaction Layer Packets) between the upstream network interfaces (2-1-2-N) and the downstream network interfaces (5-1-5-M) or between the downstream network interfaces (5-1-5-M). This enables to distribute and connect a plurality of computers and a plurality of I/Os on a large scale without changing software, root complexes, and I/Os.
摘要翻译：上游网络接口（2-1-2-N）和下游网络接口（5-1-5-M）分别具有上行PCI-PCI桥接功能和下游PCI-PCI桥接功能。这些网络接口（2-1-2-N，5-1-5-M）和网络（3）作为单个多根PCI快速交换机并入系统中。网络（3）在上游网络接口（2-1-2-N）和下游网络接口（5-1-5-M）之间或下游网络接口（5-1）之间隧道TLP（事务层报文） -5-M）。这使得能够大规模地分发和连接多个计算机和多个I / O，而不需要改变软件，根机构和I / O。

26. 发明申请

US20100257302A1 I/O CONNECTION SYSTEM AND I/O CONNECTION METHOD 有权
标题翻译： I / O连接系统和I / O连接方法
公开(公告)号：US20100257302A1
公开(公告)日：2010-10-07
申请号：US12739843
申请日：2008-10-27
申请人： Jun Suzuki , Youichi Hidaka , Takashi Yoshikawa
发明人： Jun Suzuki , Youichi Hidaka , Takashi Yoshikawa
IPC分类号： G06F13/36
CPC分类号： G06F13/4027 , H04L41/0806 , H04L41/0853
摘要： Upstream network interfaces (2-1-2-N) and downstream network interfaces (5-1-5-M) have an upstream PCI-PCI bridge function and a downstream PCI-PCI bridge function, respectively. These network interfaces (2-1-2-N, 5-1-5-M) and a network (3) are incorporated in a system as a single multi-root PCI express switch. The network (3) tunnels TLPs (Transaction Layer Packets) between the upstream network interfaces (2-1-2-N) and the downstream network interfaces (5-1-5-M) or between the downstream network interfaces (5-1-5-M). This enables to distribute and connect a plurality of computers and a plurality of I/Os on a large scale without changing software, root complexes, and I/Os.
摘要翻译：上游网络接口（2-1-2-N）和下游网络接口（5-1-5-M）分别具有上行PCI-PCI桥接功能和下游PCI-PCI桥接功能。这些网络接口（2-1-2-N，5-1-5-M）和网络（3）作为单个多根PCI快速交换机并入系统中。网络（3）在上游网络接口（2-1-2-N）和下游网络接口（5-1-5-M）之间或下游网络接口（5-1）之间隧道TLP（事务层报文） -5-M）。这使得能够大规模地分发和连接多个计算机和多个I / O，而不需要改变软件，根机构和I / O。

27. 发明授权

US08775712B2 Bus connecting device for connecting host with external device 有权
标题翻译：总线连接装置，用于连接主机与外部设备
公开(公告)号：US08775712B2
公开(公告)日：2014-07-08
申请号：US12098750
申请日：2008-04-07
申请人： Jun Suzuki , Youichi Hidaka , Takashi Yoshikawa
发明人： Jun Suzuki , Youichi Hidaka , Takashi Yoshikawa
IPC分类号： G06F13/00
CPC分类号： G06F13/4027
摘要： A detecting unit detects a connection of an external device to a connection port and stores the connection in a bridge state storage unit. This setting is autonomously completed by a device before an initial configuration is started by a host. A data transfer unit receives initial configuration data of a link-connection bridge from the host. Data is transferred to the linked-uplink-connection bridge with reference to the bridge state storage unit, data to a bridge which is not linked up is wasted, or an Unsupported Request is returned to the host to represent the absence of the link-connection bridge.
摘要翻译：检测单元检测外部设备到连接端口的连接并将连接存储在桥接状态存储单元中。在主机启动初始配置之前，此设置由设备自动完成。数据传送单元从主机接收链路连接桥的初始配置数据。参考桥状态存储单元将数据传送到链接上行链路连接桥，浪费不连接到桥的数据，或者向主机返回不支持请求以表示链路连接的缺失桥。

28. 发明申请

US20130346643A1 DATA CONTROL SYSTEM, DATA CONTROL METHOD, AND DATA CONTROL PROGRAM 有权
标题翻译：数据控制系统，数据控制方法和数据控制程序
公开(公告)号：US20130346643A1
公开(公告)日：2013-12-26
申请号：US14002945
申请日：2012-02-23
申请人： Jun Suzuki , Masahiko Takahashi , Youichi Hidaka , Teruyuki Baba , Takashi Yoshikawa
发明人： Jun Suzuki , Masahiko Takahashi , Youichi Hidaka , Teruyuki Baba , Takashi Yoshikawa
IPC分类号： G06F13/16
CPC分类号： G06F13/16 , G06F13/102 , G06F13/28 , G06F2213/0026
摘要： A CPU 80 controls data transfer from a first device to a second device in a kernel mode. A main memory 90 stores data to be transferred from the first device to the second device. The CPU 80 has: a first device control means 81 which controls the first device; a second device control means which controls the second device; and a data transfer control means 83 which makes a read instruction which instructs the first device control means 81 to store data read from the first device in the main memory 3, and makes a write instruction which instructs the second device control means 82 to write the data stored in the main memory 3 in the second device.
摘要翻译： CPU 80以内核模式控制从第一设备到第二设备的数据传输。主存储器90存储要从第一设备传送到第二设备的数据。 CPU80具有：控制第一装置的第一装置控制装置81; 控制第二装置的第二装置控制装置; 以及数据传送控制装置83，其使得指令第一装置控制装置81将从第一装置读取的数据存储在主存储器3中的读取指令，并且进行指示第二装置控制装置82写入的写指令存储在第二装置中的主存储器3中的数据。

29. 发明授权

US08683110B2 I/O system and I/O control method 有权
标题翻译： I / O系统和I / O控制方式
公开(公告)号：US08683110B2
公开(公告)日：2014-03-25
申请号：US12674337
申请日：2008-08-25
申请人： Jun Suzuki , Youichi Hidaka , Takashi Yoshikawa
发明人： Jun Suzuki , Youichi Hidaka , Takashi Yoshikawa
IPC分类号： G06F13/36
CPC分类号： G06F13/12
摘要： Virtual Functions (VFs) 602-1 to 602-N of an I/O device are separately allocated to a plurality of computers 1-1 to 1-N. In an address swap table 506, a root domain that is an address space of the computer 1 and mapping information of an I/O domain that is an address space unique to the I/O device 6 are registered. Mapping is set with the VFs 602-1 to 602-N as units. When accessing the VFs 602-1 to 602-N of the I/O device 6 to which each of the computers 1-1 to 1-N is allocated, an I/O packet transfer unit 701 checks the address swap table 506 to swap source/destination addresses recorded in packet headers.
摘要翻译： I / O设备的虚拟功能（VF）602-1至602-N分别分配给多个计算机1-1至1-N。在地址交换表506中，登记作为计算机1的地址空间的根域和作为I / O装置6唯一的地址空间的I / O域的映射信息。映射以VFS 602-1至602-N为单位设置。当访问分配了计算机1-1至1-N中的每一个的I / O设备6的VFS 602-1至602-N时，I / O分组传送单元701检查地址交换表506以交换记录在报头中的源/目的地址。

30. 发明授权

US09280498B2 Data control system, data control method, and data control program 有权
标题翻译：数据控制系统，数据控制方法和数据控制程序
公开(公告)号：US09280498B2
公开(公告)日：2016-03-08
申请号：US14002945
申请日：2012-02-23
申请人： Jun Suzuki , Masahiko Takahashi , Youichi Hidaka , Teruyuki Baba , Takashi Yoshikawa
发明人： Jun Suzuki , Masahiko Takahashi , Youichi Hidaka , Teruyuki Baba , Takashi Yoshikawa
IPC分类号： G06F13/28 , G06F13/16 , G06F13/10
CPC分类号： G06F13/16 , G06F13/102 , G06F13/28 , G06F2213/0026
摘要： A CPU 80 controls data transfer from a first device to a second device in a kernel mode. A main memory 90 stores data to be transferred from the first device to the second device. The CPU 80 has: a first device control means 81 which controls the first device; a second device control means which controls the second device; and a data transfer control means 83 which makes a read instruction which instructs the first device control means 81 to store data read from the first device in the main memory 3, and makes a write instruction which instructs the second device control means 82 to write the data stored in the main memory 3 in the second device.
摘要翻译： CPU 80以内核模式控制从第一设备到第二设备的数据传输。主存储器90存储要从第一设备传送到第二设备的数据。 CPU80具有：控制第一装置的第一装置控制装置81; 控制第二装置的第二装置控制装置; 以及数据传送控制装置83，其使得指令第一装置控制装置81将从第一装置读取的数据存储在主存储器3中的读取指令，并且进行指示第二装置控制装置82写入的写指令存储在第二装置中的主存储器3中的数据。

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