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    • 22. 发明授权
    • Copper wiring module control
    • 铜接线模块控制
    • US08005634B2
    • 2011-08-23
    • US11627353
    • 2007-01-25
    • Arulkumar ShanmugasundramSuketu A. Parikh
    • Arulkumar ShanmugasundramSuketu A. Parikh
    • G01N37/00
    • B24B37/042B24B49/00C23F3/00H01L21/2885H01L21/67253H01L21/67276H01L22/20H01L2924/0002H01L2924/00
    • Techniques for controlling an output property during wafer processing include forwarding feedforward and feedback information between functional units in a wafer manufacturing facility. At least some embodiments of the invention envision implementing such techniques in a copper wiring module to optimize a sheet resistance or an interconnect line resistance. Initially, a first wafer property is measured during or after processing by a plating process. Subsequently, the wafer is forwarded to a polishing process. A second wafer property is then measured during or after processing by the second process. At least one of these first and second wafer properties are used to optimize the second process. Specifically, one or more target parameters of a second process recipe are adjusted in a manner that obtains a desired final output property on the wafer by using these first and second wafer properties.
    • 用于在晶片处理期间控制输出特性的技术包括在晶片制造设备中的功能单元之间转发前馈和反馈信息。 本发明的至少一些实施例设想在铜布线模块中实现这种技术以优化薄层电阻或互连线电阻。 最初,通过电镀工艺在处理期间或之后测量第一晶片性质。 随后,将晶片转发到抛光工艺。 然后在第二工艺处理期间或之后测量第二晶片特性。 这些第一和第二晶片特性中的至少一个用于优化第二过程。 具体地,以通过使用这些第一和第二晶片特性在晶片上获得期望的最终输出特性的方式调整第二处理配方的一个或多个目标参数。
    • 25. 发明申请
    • Copper Wiring Module Control
    • 铜线接线模块控制
    • US20070122921A1
    • 2007-05-31
    • US11627353
    • 2007-01-25
    • Arulkumar ShanmugasundramSuketu Parikh
    • Arulkumar ShanmugasundramSuketu Parikh
    • H01L21/66
    • B24B37/042B24B49/00C23F3/00H01L21/2885H01L21/67253H01L21/67276H01L22/20H01L2924/0002H01L2924/00
    • Techniques for controlling an output property during wafer processing include forwarding feedforward and feedback information between functional units in a wafer manufacturing facility. At least some embodiments of the invention envision implementing such techniques in a copper wiring module to optimize a sheet resistance or an interconnect line resistance. Initially, a first wafer property is measured during or after processing by a plating process. Subsequently, the wafer is forwarded to a polishing process. A second wafer property is then measured during or after processing by the second process. At least one of these first and second wafer properties are used to optimize the second process. Specifically, one or more target parameters of a second process recipe are adjusted in a manner that obtains a desired final output property on the wafer by using these first and second wafer properties.
    • 用于在晶片处理期间控制输出特性的技术包括在晶片制造设备中的功能单元之间转发前馈和反馈信息。 本发明的至少一些实施例设想在铜布线模块中实现这种技术以优化薄层电阻或互连线电阻。 最初,通过电镀工艺在处理期间或之后测量第一晶片性质。 随后,将晶片转发到抛光工艺。 然后在第二工艺处理期间或之后测量第二晶片特性。 这些第一和第二晶片特性中的至少一个用于优化第二过程。 具体地,以通过使用这些第一和第二晶片特性在晶片上获得期望的最终输出特性的方式调整第二处理配方的一个或多个目标参数。