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21. 发明申请

US20140051213A1 Techniques for Metal Gate Work Function Engineering to Enable Multiple Threshold Voltage Nanowire FET Devices 有权
标题翻译：金属栅极工作功能工程技术开启多阈值电压纳米线FET器件
公开(公告)号：US20140051213A1
公开(公告)日：2014-02-20
申请号：US13588724
申请日：2012-08-17
申请人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L21/336
CPC分类号： H01L29/16 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/068 , H01L29/4232 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： A method of fabricating a nanowire FET device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are etched in the SOI layer. The nanowires are suspended over the BOX. An interfacial oxide is formed surrounding each of the nanowires. A conformal gate dielectric is deposited on the interfacial oxide. A conformal first gate material is deposited on the conformal gate dielectric. A work function setting material is deposited on the conformal first gate material. A second gate material is deposited on the work function setting material to form at least one gate stack over the nanowires. A volume of the conformal first gate material and/or a volume of the work function setting material in the gate stack are/is proportional to a pitch of the nanowires.
摘要翻译：制造纳米线FET器件的方法包括以下步骤。提供了具有在BOX上的SOI层的SOI晶片。在SOI层中蚀刻纳米线和焊盘。纳米线悬挂在BOX上。围绕每个纳米线形成界面氧化物。共形栅电介质沉积在界面氧化物上。保形第一栅极材料沉积在保形栅极电介质上。工件功能设定材料沉积在保形第一栅极材料上。第二栅极材料沉积在功函数设定材料上以在纳米线上形成至少一个栅叠层。栅极堆叠中的共形第一栅极材料的体积和/或功函数设定材料的体积与纳米线的间距成比例。

22. 发明申请

US20140048882A1 TECHNIQUES FOR GATE WORKFUNCTION ENGINEERING TO REDUCE SHORT CHANNEL EFFECTS IN PLANAR CMOS DEVICES 有权
标题翻译：门工功能工程技术降低平面CMOS器件中的短路通道效应
公开(公告)号：US20140048882A1
公开(公告)日：2014-02-20
申请号：US13617283
申请日：2012-09-14
申请人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L29/78
CPC分类号： H01L29/66545 , H01L21/823842 , H01L21/82385 , H01L21/84 , H01L27/1203
摘要： In one aspect, a CMOS device is provided. The CMOS device includes a SOI wafer having a SOI layer over a BOX; one or more active areas formed in the SOI layer in which one or more FET devices are formed, each of the FET devices having an interfacial oxide on the SOI layer and a gate stack on the interfacial oxide layer, the gate stack having (i) a conformal gate dielectric layer present on a top and sides of the gate stack, (ii) a conformal gate metal layer lining the gate dielectric layer, and (iii) a conformal workfunction setting metal layer lining the conformal gate metal layer. A volume of the conformal gate metal layer and/or a volume of the conformal workfunction setting metal layer present in the gate stack are/is proportional to a length of the gate stack.
摘要翻译：在一个方面，提供一种CMOS器件。 CMOS器件包括在BOX上具有SOI层的SOI晶片; 形成在其中形成有一个或多个FET器件的SOI层中的一个或多个有源区，每个FET器件在SOI层上具有界面氧化物，在界面氧化物层上具有栅极堆叠，所述栅极堆叠具有（i）存在于栅极堆叠的顶部和侧面上的共形栅极电介质层，（ii）衬在栅极介电层的共形栅极金属层，以及（iii）在保形栅极金属层之上的共形功函数设定金属层。存在于栅极堆叠中的共形栅极金属层的体积和/或共形功函数设定金属层的体积与栅极堆叠的长度成比例。

23. 发明申请

US20130328116A1 DRAM WITH A NANOWIRE ACCESS TRANSISTOR 有权
标题翻译：具有纳米访问晶体管的DRAM
公开(公告)号：US20130328116A1
公开(公告)日：2013-12-12
申请号：US13490759
申请日：2012-06-07
申请人： Josephine B. Chang , Jeffrey W. Sleight
发明人： Josephine B. Chang , Jeffrey W. Sleight
IPC分类号： H01L27/108 , H01L21/8242 , B82Y99/00
CPC分类号： H01L27/10805 , B82Y10/00 , H01L21/84 , H01L27/0207 , H01L27/10873 , H01L27/1203 , H01L29/0673 , H01L29/66439 , H01L29/775 , H01L29/945 , Y10S977/89 , Y10S977/943
摘要： A semiconductor nanowire is formed integrally with a wraparound semiconductor portion that contacts sidewalls of a conductive cap structure located at an upper portion of a deep trench and contacting an inner electrode of a deep trench capacitor. The semiconductor nanowire is suspended from above a buried insulator layer. A gate dielectric layer is formed on the surfaces of the patterned semiconductor material structure including the semiconductor nanowire and the wraparound semiconductor portion. A wraparound gate electrode portion is formed around a center portion of the semiconductor nanowire and gate spacers are formed. Physically exposed portions of the patterned semiconductor material structure are removed, and selective epitaxy and metallization are performed to connect a source-side end of the semiconductor nanowire to the conductive cap structure.
摘要翻译：半导体纳米线与环绕半导体部分整体形成，该环绕半导体部分接触位于深沟槽的上部并且与深沟槽电容器的内部电极接触的导电盖结构的侧壁。半导体纳米线从掩埋绝缘体层的上方悬挂。在包括半导体纳米线和环绕半导体部分的图案化半导体材料结构的表面上形成栅极电介质层。围绕半导体纳米线的中心部分形成环形栅电极部分，形成栅极间隔物。去除图案化的半导体材料结构的物理曝光部分，并且执行选择性外延和金属化以将半导体纳米线的源极端部连接到导电帽结构。

24. 发明申请

US20130256797A1 Asymmetric FET Formed Through Use of Variable Pitch Gate for Use as Logic Device and Test Structure 有权
标题翻译：通过使用可变间距门形成的非对称FET用作逻辑器件和测试结构
公开(公告)号：US20130256797A1
公开(公告)日：2013-10-03
申请号：US13441048
申请日：2012-04-06
申请人： Josephine B. Chang , Chung-Hsun Lin , Isaac Lauer , Jeffrey W. Sleight
发明人： Josephine B. Chang , Chung-Hsun Lin , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L21/823437 , H01L22/34 , H01L27/0207 , H01L27/1203
摘要： Asymmetric FET devices and methods for fabrication thereof that employ a variable pitch gate are provided. In one aspect, a FET device is provided. The FET device includes a wafer; a plurality of active areas formed in the wafer; a plurality of gate stacks on the wafer, wherein at least one of the gate stacks is present over each of the active areas, and wherein the gate stacks have an irregular gate-to-gate spacing such that for at least a given one of the active areas a gate-to-gate spacing on a source side of the given active area is greater than a gate-to-gate spacing on a drain side of the given active area; spacers on opposite sides of the gate stacks; and an angled implant in the source side of the given active area.
摘要翻译：提供了非对称FET器件及其制造方法，其采用可变间距栅极。一方面，提供一种FET器件。 FET器件包括晶片; 形成在晶片中的多个有源区; 晶片上的多个栅极堆叠，其中至少一个栅极堆叠存在于每个有源区域上，并且其中栅极堆叠具有不规则的栅极至栅极间隔，使得对于至少一个有源区域在给定有源区域的源极侧上的栅极至栅极间隔大于给定有源区域的漏极侧上的栅极至栅极间隔; 栅极堆叠的相对侧上的间隔物; 以及在给定活动区域的源侧的成角度的植入物。

25. 发明授权

US08536029B1 Nanowire FET and finFET 有权
标题翻译：纳米线FET和finFET
公开(公告)号：US08536029B1
公开(公告)日：2013-09-17
申请号：US13529334
申请日：2012-06-21
申请人： Josephine B. Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/845 , B82Y10/00 , H01L27/1211 , H01L29/0673 , H01L29/42392 , H01L29/775 , H01L29/78696
摘要： A method includes thinning a first region of an active layer, for form a stepped surface in the active layer defined by the first region and a second region of the active layer, depositing an planarizing layer on the active layer that defines a planar surface disposed on the active layer, etching to define nanowires and pads in the first region of the active layer, suspending the nanowires over the BOX layer, etching fins in the second region of the active layer forming a first gate stack that surrounds portion of each of the nanowires, forming a second gate stack covering a portion of the fins, and growing an epitaxial material wherein the epitaxial material defines source and drain regions of the nanowire FET and source and drain regions of the finFET.
摘要翻译：一种方法包括使有源层的第一区域变薄，以形成由有源层的第一区域和第二区域限定的有源层中的阶梯表面，在活性层上沉积限定平面的平坦化层，有源层，蚀刻以在有源层的第一区域中限定纳米线和焊盘，将纳米线悬挂在BOX层上，蚀刻有源层的第二区域中的鳍形成围绕每个纳米线的部分的第一栅极堆叠形成覆盖所述翅片的一部分的第二栅极堆叠，以及生长外延材料，其中所述外延材料限定所述纳米线FET的源极和漏极区域以及所述finFET的源极和漏极区域。

26. 发明申请

US20130105897A1 Nanowire FET and FINFET Hybrid Technology 失效
标题翻译：纳米线FET和FINFET混合技术
公开(公告)号：US20130105897A1
公开(公告)日：2013-05-02
申请号：US13286311
申请日：2011-11-01
申请人： Sarunya Bangsaruntip , Josephine B. Chang , Leland Chang , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Josephine B. Chang , Leland Chang , Jeffrey W. Sleight
IPC分类号： H01L27/12 , H01L21/8238
CPC分类号： H01L27/1211 , B82Y10/00 , B82Y40/00 , H01L21/3247 , H01L21/845 , H01L29/0673 , H01L29/42392 , H01L29/66469 , H01L29/78696
摘要： Hybrid nanowire FET and FinFET devices and methods for fabrication thereof are provided. In one aspect, a method for fabricating a CMOS circuit having a nanowire FET and a finFET includes the following steps. A wafer is provided having an active layer over a BOX. A first region of the active layer is thinned. An organic planarizing layer is deposited on the active layer. Nanowires and pads are etched in the first region of the active layer using a first hardmask. The nanowires are suspended over the BOX. Fins are etched in the second region of the active layer using a second hardmask. A first gate stack is formed that surrounds at least a portion of each of the nanowires. A second gate stack is formed covering at least a portion of each of the fins. An epitaxial material is grown on exposed portions of the nanowires, pads and fins.
摘要翻译：提供了混合纳米线FET和FinFET器件及其制造方法。一方面，制造具有纳米线FET和finFET的CMOS电路的方法包括以下步骤。提供了在BOX上具有活性层的晶片。有源层的第一区域变薄。有机平面化层沉积在有源层上。使用第一硬掩模在有源层的第一区域中蚀刻纳米线和焊盘。纳米线悬挂在BOX上。使用第二硬掩模在活性层的第二区域中蚀刻金箔。形成围绕每个纳米线的至少一部分的第一栅极堆叠。形成第二栅极堆叠，覆盖每个散热片的至少一部分。在纳米线，焊盘和鳍片的暴露部分上生长外延材料。

27. 发明授权

US08426917B2 Body-tied asymmetric P-type field effect transistor 有权
标题翻译：体系不对称P型场效应晶体管
公开(公告)号：US08426917B2
公开(公告)日：2013-04-23
申请号：US12683606
申请日：2010-01-07
申请人： Jeffrey W. Sleight , Chung-Hsun Lin , Josephine B. Chang , Leland Chang
发明人： Jeffrey W. Sleight , Chung-Hsun Lin , Josephine B. Chang , Leland Chang
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/78612 , H01L21/26586 , H01L29/1083 , H01L29/42384 , H01L29/66772
摘要： In one exemplary embodiment of the invention, an asymmetric P-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric P-type field effect transistor is operable to act as a symmetric P-type field effect transistor.
摘要翻译：在本发明的一个示例性实施例中，非对称P型场效应晶体管包括：源极区，经由沟道耦合到漏极区; 覆盖所述通道的至少一部分的栅极结构; 至少部分地设置在所述通道中的卤素植入物，其中所述晕轮植入物设置成比所述漏极区域更靠近所述源极区域; 以及耦合到该通道的机身连接。在另一示例性实施例中，非对称P型场效应晶体管可用作对称P型场效应晶体管。

28. 发明授权

US08349670B2 Selective floating body SRAM cell 有权
标题翻译：选择性浮体SRAM单元
公开(公告)号：US08349670B2
公开(公告)日：2013-01-08
申请号：US13045756
申请日：2011-03-11
申请人： Josephine B. Chang , Leland Chang , Steven J. Koester , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Steven J. Koester , Jeffrey W. Sleight
IPC分类号： H01L21/00
CPC分类号： H01L27/088 , H01L21/845 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L27/1207 , H01L27/1211 , H01L29/7841
摘要： A memory cell has N≧6 transistors, in which two are access transistors, at least one pair [say (N−2)/2] are pull-up transistors, and at least another pair [say (N−2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed.
摘要翻译：存储单元具有N≥6个晶体管，其中两个是存取晶体管，至少一对[例如（N-2）/ 2]是上拉晶体管，并且至少另一对[例如（N-2）/ 2 ]是下拉晶体管。上拉和下拉晶体管都耦合在两个存取晶体管之间。每个存取晶体管和上拉晶体管是相同类型的，p型或n型。每个下拉晶体管是另一种类型的p型或n型。存取晶体管是浮体装置。下拉晶体管是非浮体器件。上拉晶体管可以是浮动或非浮动体器件。还详细描述了制造存储器单元的各种具体实施方式和方法。

29. 发明申请

US20110065244A1 ASYMMETRIC FINFET DEVICE WITH IMPROVED PARASITIC RESISTANCE AND CAPACITANCE 有权
标题翻译：具有改进的抗电弧和电容的非对称FINFET器件
公开(公告)号：US20110065244A1
公开(公告)日：2011-03-17
申请号：US12559996
申请日：2009-09-15
申请人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L21/26513 , H01L29/66795
摘要： A method for forming a fin field effect transistor (finFET) device includes, forming a fin structure in a substrate, forming a gate stack structure perpendicular to the fin structure, and implanting ions in the substrate at an angle (θ) to form a source region and a drain region in the substrate, wherein the angle (θ) is oblique relative to the source region.
摘要翻译：一种用于形成鳍状场效应晶体管（finFET）器件的方法包括：在衬底中形成翅片结构，形成垂直于翅片结构的栅极堆叠结构，并以一定角度（...）将离子注入到衬底中以形成源极区域和漏极区域，其中角度（θ）相对于源极区域是倾斜的。

30. 发明授权

US08822278B2 Asymmetric FET formed through use of variable pitch gate for use as logic device and test structure 有权
标题翻译：通过使用可变间距门形成的非对称FET用作逻辑器件和测试结构
公开(公告)号：US08822278B2
公开(公告)日：2014-09-02
申请号：US13434128
申请日：2012-03-29
申请人： Josephine B. Chang , Chung-Hsun Lin , Isaac Lauer , Jeffrey W. Sleight
发明人： Josephine B. Chang , Chung-Hsun Lin , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L27/12
CPC分类号： H01L27/088 , H01L21/823437 , H01L22/34 , H01L27/0207 , H01L27/1203
摘要： Asymmetric FET devices and methods for fabrication thereof that employ a variable pitch gate are provided. In one aspect, a method for fabricating a FET device includes the following steps. A wafer is provided. A plurality of active areas is formed in the wafer using STI. A plurality of gate stacks is formed on the wafer, wherein the gate stacks have an irregular gate-to-gate spacing such that for at least a given one of the active areas a gate-to-gate spacing on a source side of the given active area is greater than a gate-to-gate spacing on a drain side of the given active area. Spacers are formed on opposite sides of the gate stacks. An angled implant is performed into the source side of the given active area. A FET device is also provided.
摘要翻译：提供了非对称FET器件及其制造方法，其采用可变间距栅极。一方面，一种用于制造FET器件的方法包括以下步骤。提供晶片。使用STI在晶片中形成多个有效区域。在晶片上形成多个栅极堆叠，其中栅极堆叠具有不规则的栅极至栅极间隔，使得对于至少给定的一个有源区域，给定的源极侧的栅极到栅极间隔有源面积大于给定有源区域的漏极侧上的栅极至栅极间距。隔板形成在栅极堆叠的相对侧上。在给定活动区域的源侧执行成角度的植入物。还提供了FET器件。

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