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21. 发明申请

US20130341596A1 NANOWIRE FET AND FINFET 审中-公开
标题翻译： NANOWIRE FET和FINFET
公开(公告)号：US20130341596A1
公开(公告)日：2013-12-26
申请号：US13548554
申请日：2012-07-13
申请人： Josephine B. Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L29/775 , B82Y99/00
CPC分类号： H01L21/845 , B82Y10/00 , H01L27/1211 , H01L29/0673 , H01L29/42392 , H01L29/775 , H01L29/78696
摘要： A complimentary metal oxide semiconductor (CMOS) device includes a wafer having a buried oxide (BOX) layer having a first region with a first thickness and a second region with a second thickness, the first thickness is less than the second thickness, a nanowire field effect transistor (FET) arranged on the BOX layer in the first region, the nanowire FET, and a finFET arranged on the BOX layer in the second region.
摘要翻译：互补金属氧化物半导体（CMOS）器件包括具有掩埋氧化物（BOX）层的晶片，其具有第一厚度的第一区域和具有第二厚度的第二区域，第一厚度小于第二厚度，纳米线场布置在第一区域中的BOX层上的效应晶体管（FET），纳米线FET和布置在第二区域中的BOX层上的finFET。

22. 发明申请

US20130153996A1 HYBRID CMOS NANOWIRE MESH DEVICE AND PDSOI DEVICE 有权
标题翻译： HYBRID CMOS NANOWIRE MESH DEVICE和PDSOI DEVICE
公开(公告)号：US20130153996A1
公开(公告)日：2013-06-20
申请号：US13328069
申请日：2011-12-16
申请人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L27/088 , H01L21/28 , H01L29/78 , B82Y40/00 , B82Y99/00
CPC分类号： H01L27/1203 , B82Y10/00 , B82Y40/00 , H01L21/28 , H01L21/845 , H01L27/088 , H01L27/1211 , H01L29/0673 , H01L29/66439 , H01L29/66795 , H01L29/78 , H01L29/785 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a PDSOI device on the same SOI substrate. Also included is a semiconductor structure which includes the nanowire mesh device and the PDSOI device on the same SOI substrate.
摘要翻译：一种在SOI衬底上形成混合半导体结构的方法。该方法包括在同一SOI衬底上形成纳米线网状器件和PDSOI器件的集成工艺流程。还包括在同一SOI衬底上包括纳米线网状器件和PDSOI器件的半导体结构。

23. 发明授权

US08304837B2 Differentially recessed contacts for multi-gate transistor of SRAM cell 有权
标题翻译： SRAM单元的多栅极晶体管的差分凹陷触点
公开(公告)号：US08304837B2
公开(公告)日：2012-11-06
申请号：US12816825
申请日：2010-06-16
申请人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L21/70
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11
摘要： A complementary metal-oxide-semiconductor static random access memory cell that includes a plurality of P-channel multi-gate transistors and a plurality of N-channel multi-gate transistors. Each transistor includes a gate electrode and source and drain regions separated by the at least one gate electrode. The SRAM cell further includes a plurality of contacts formed within the source and drain regions of at least one transistor. A plurality of contacts of at least one transistor are recessed a predetermined recess amount, wherein a resistance of the at least one transistor is varied based upon the predetermined recess amount.
摘要翻译：具有多个P沟道多栅极晶体管和多个N沟道多栅极晶体管的互补金属氧化物半导体静态随机存取存储单元。每个晶体管包括栅电极和由至少一个栅极电极隔开的源极和漏极区域。 SRAM单元还包括形成在至少一个晶体管的源区和漏区内的多个触点。至少一个晶体管的多个触点凹入预定的凹陷量，其中至少一个晶体管的电阻基于预定的凹陷量而变化。

24. 发明申请

US20110163379A1 Body-Tied Asymmetric P-Type Field Effect Transistor 有权
标题翻译：体态非对称P型场效应晶体管
公开(公告)号：US20110163379A1
公开(公告)日：2011-07-07
申请号：US12683606
申请日：2010-01-07
申请人： Jeffrey W. Sleight , Chung-Hsun Lin , Josephine B. Chang , Leland Chang
发明人： Jeffrey W. Sleight , Chung-Hsun Lin , Josephine B. Chang , Leland Chang
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/78612 , H01L21/26586 , H01L29/1083 , H01L29/42384 , H01L29/66772
摘要： In one exemplary embodiment of the invention, an asymmetric P-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric P-type field effect transistor is operable to act as a symmetric P-type field effect transistor.
摘要翻译：在本发明的一个示例性实施例中，非对称P型场效应晶体管包括：源极区，经由沟道耦合到漏极区; 覆盖所述通道的至少一部分的栅极结构; 至少部分地设置在所述通道中的卤素植入物，其中所述晕轮植入物设置成比所述漏极区域更靠近所述源极区域; 以及耦合到该通道的机身连接。在另一示例性实施例中，非对称P型场效应晶体管可用作对称P型场效应晶体管。

25. 发明授权

US07948307B2 Dual dielectric tri-gate field effect transistor 有权
标题翻译：双介质三栅场效应晶体管
公开(公告)号：US07948307B2
公开(公告)日：2011-05-24
申请号：US12561880
申请日：2009-09-17
申请人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L25/00
CPC分类号： H01L29/66795 , H01L21/84 , H01L27/1203 , H01L29/785 , H01L2924/0002 , H01L2924/00
摘要： A dual dielectric tri-gate field effect transistor, a method of fabricating a dual dielectric tri-gate field effect transistor, and a method of operating a dual dielectric tri-gate effect transistor are disclosed. In one embodiment, the dual dielectric tri-gate transistor comprises a substrate, an insulating layer on the substrate, and at least one semiconductor fin. A first dielectric having a first dielectric constant extends over sidewalls of the fin, and a metal layer extends over the first dielectric, and a second dielectric having a second dielectric constant is on a top surface of the fin. A gate electrode extends over the fin and the first and second dielectrics. The gate electrode and the first dielectric layer form first and second gates having a threshold voltage Vt1, and the gate electrode and the second dielectric layer form a third gate having a threshold voltage Vt2 different than Vt1.
摘要翻译：公开了双电介质三栅场效应晶体管，制造双电介质三栅场效应晶体管的方法，以及操作双电介质三栅效应晶体管的方法。在一个实施例中，双电介质三栅晶体管包括衬底，衬底上的绝缘层和至少一个半导体鳍片。具有第一介电常数的第一电介质在翅片的侧壁上延伸，并且金属层在第一电介质上延伸，并且具有第二介电常数的第二电介质位于散热片的顶表面上。栅电极在鳍片和第一和第二电介质上延伸。栅电极和第一电介质层形成具有阈值电压Vt1的第一栅极和第二栅极，栅电极和第二电介质层形成具有不同于Vt1的阈值电压Vt2的第三栅极。

26. 发明授权

US08709888B2 Hybrid CMOS nanowire mesh device and PDSOI device 有权
标题翻译：混合CMOS纳米线网格装置和PDSOI装置
公开(公告)号：US08709888B2
公开(公告)日：2014-04-29
申请号：US13328069
申请日：2011-12-16
申请人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L29/72
CPC分类号： H01L27/1203 , B82Y10/00 , B82Y40/00 , H01L21/28 , H01L21/845 , H01L27/088 , H01L27/1211 , H01L29/0673 , H01L29/66439 , H01L29/66795 , H01L29/78 , H01L29/785 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a PDSOI device on the same SOI substrate. Also included is a semiconductor structure which includes the nanowire mesh device and the PDSOI device on the same SOI substrate.
摘要翻译：一种在SOI衬底上形成混合半导体结构的方法。该方法包括在同一SOI衬底上形成纳米线网状器件和PDSOI器件的集成工艺流程。还包括在同一SOI衬底上包括纳米线网状器件和PDSOI器件的半导体结构。

27. 发明申请

US20140065802A1 TECHNIQUES FOR METAL GATE WORKFUNCTION ENGINEERING TO ENABLE MULTIPLE THRESHOLD VOLTAGE FINFET DEVICES 有权
标题翻译：金属门工作功能的技术应用于启用多个阈值电压FinFET器件
公开(公告)号：US20140065802A1
公开(公告)日：2014-03-06
申请号：US13596687
申请日：2012-08-28
申请人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L21/20
CPC分类号： H01L27/1211 , H01L21/845
摘要： Techniques are provided for gate work function engineering in FIN FET devices using a work function setting material an amount of which is provided proportional to fin pitch. In one aspect, a method of fabricating a FIN FET device includes the following steps. A SOI wafer having a SOI layer over a BOX is provided. An oxide layer is formed over the SOI layer. A plurality of fins is patterned in the SOI layer and the oxide layer. An interfacial oxide is formed on the fins. A conformal gate dielectric layer, a conformal gate metal layer and a conformal work function setting material layer are deposited on the fins. A volume of the conformal gate metal layer and a volume of the conformal work function setting material layer deposited over the fins is proportional to a pitch of the fins. A FIN FET device is also provided.
摘要翻译：在Fin FET器件中提供栅极功能工程的技术，其功能设定材料的数量与翅片间距成正比。一方面，制造FIN FET器件的方法包括以下步骤。提供了在BOX上具有SOI层的SOI晶片。在SOI层上形成氧化物层。在SOI层和氧化物层中图案化多个翅片。翅片上形成界面氧化物。共形栅介电层，共形栅极金属层和共形功函数设定材料层沉积在散热片上。共形栅极金属层的体积和沉积在鳍片上的共形功函数设定材料层的体积与翅片的间距成正比。还提供了一种FIN FET器件。

28. 发明申请

US20140061796A1 TECHNIQUES FOR METAL GATE WORKFUNCTION ENGINEERING TO ENABLE MULTIPLE THRESHOLD VOLTAGE FINFET DEVICES 有权
标题翻译：金属门工作功能的技术应用于启用多个阈值电压FinFET器件
公开(公告)号：US20140061796A1
公开(公告)日：2014-03-06
申请号：US13611257
申请日：2012-09-12
申请人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L27/12
CPC分类号： H01L27/1211 , H01L21/845
摘要： Techniques are provided for gate work function engineering in FIN FET devices using a work function setting material an amount of which is provided proportional to fin pitch. In one aspect, a FIN FET device is provided. The FIN FET device includes a SOI wafer having an oxide layer and a SOI layer over a BOX, and a plurality of fins patterned in the oxide layer and the SOI layer; an interfacial oxide on the fins; and at least one gate stack on the interfacial oxide, the gate stack having (i) a conformal gate dielectric layer present, (ii) a conformal gate metal layer, and (iii) a conformal work function setting material layer. A volume of the conformal gate metal layer and a volume of the conformal work function setting material layer present in the gate stack is proportional to a pitch of the fins.
摘要翻译：在Fin FET器件中提供栅极功能工程的技术，其功能设定材料的数量与翅片间距成正比。在一个方面，提供一种FIN FET器件。 FIN FET器件包括在BOX上具有氧化物层和SOI层的SOI晶片和在氧化物层和SOI层中图案化的多个鳍状物; 翅片上的界面氧化物; 和界面氧化物上的至少一个栅极堆叠，所述栅极堆叠具有（i）存在共形栅极电介质层，（ii）共形栅极金属层，和（iii）共形功函数设定材料层。存在于栅极堆叠中的共形栅极金属层的体积和共形功函数设定材料层的体积与散热片的间距成正比。

29. 发明授权

US08659084B1 Techniques for gate workfunction engineering to reduce short channel effects in planar CMOS devices 有权
标题翻译：门功能工程技术可减少平面CMOS器件中的短沟道效应
公开(公告)号：US08659084B1
公开(公告)日：2014-02-25
申请号：US13617283
申请日：2012-09-14
申请人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L27/092
CPC分类号： H01L29/66545 , H01L21/823842 , H01L21/82385 , H01L21/84 , H01L27/1203
摘要： In one aspect, a CMOS device is provided. The CMOS device includes a SOI wafer having a SOI layer over a BOX; one or more active areas formed in the SOI layer in which one or more FET devices are formed, each of the FET devices having an interfacial oxide on the SOI layer and a gate stack on the interfacial oxide layer, the gate stack having (i) a conformal gate dielectric layer present on a top and sides of the gate stack, (ii) a conformal gate metal layer lining the gate dielectric layer, and (iii) a conformal workfunction setting metal layer lining the conformal gate metal layer. A volume of the conformal gate metal layer and/or a volume of the conformal workfunction setting metal layer present in the gate stack are/is proportional to a length of the gate stack.
摘要翻译：在一个方面，提供一种CMOS器件。 CMOS器件包括在BOX上具有SOI层的SOI晶片; 形成在其中形成有一个或多个FET器件的SOI层中的一个或多个有源区，每个FET器件在SOI层上具有界面氧化物，在界面氧化物层上具有栅极堆叠，所述栅极堆叠具有（i）存在于栅极堆叠的顶部和侧面上的共形栅极电介质层，（ii）衬在栅极介电层的共形栅极金属层，以及（iii）在保形栅极金属层之上的共形功函数设定金属层。存在于栅极堆叠中的共形栅极金属层的体积和/或共形功函数设定金属层的体积与栅极堆叠的长度成比例。

30. 发明授权

US08557648B2 Recessed source and drain regions for FinFETs 有权
公开(公告)号：US08557648B2
公开(公告)日：2013-10-15
申请号：US13348188
申请日：2012-01-11
申请人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/785
摘要： Semiconductor devices and methods that include forming a fin field effect transistor by defining a fin hardmask on a semiconductor layer, forming a dummy structure over the fin hardmask to establish a planar area on the semiconductor layer, removing a portion of the fin hardmask that extends beyond the dummy structure, etching a semiconductor layer adjacent to the dummy structure to produce recessed source and drain regions, removing the dummy structure, etching the semiconductor layer in the planar area to produce fins, and forming a gate stack over the fins.

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