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21. 发明授权

US08084325B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08084325B2
公开(公告)日：2011-12-27
申请号：US12165129
申请日：2008-06-30
申请人： Myung-Ok Kim
发明人： Myung-Ok Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/76897 , H01L21/823475 , H01L29/4236 , H01L29/66621
摘要： A semiconductor device can prevent exposure of an inner wall of a recess pattern caused by misalignment between masks. A gate electrode is formed inside the recess pattern so that only a gate hard mask layer is exposed above a substrate surface. Since the gate electrode is not exposed above the substrate, it is possible to prevent SAC failure and decrease an aspect ratio of a gate pattern to increase an open margin of a contact hole. Thus, a semiconductor device having a recess channel gate structure which exhibits a superior refresh property is fabricated.
摘要翻译：半导体器件可以防止由掩模之间的未对准引起的凹部图案的内壁的暴露。在凹槽图案内部形成栅电极，使得仅在栅极表面露出栅极硬掩模层。由于栅极没有暴露在基板上方，因此可以防止SAC故障并且减小栅极图案的纵横比以增加接触孔的开口边缘。因此，制造具有优异刷新特性的具有凹槽通道栅极结构的半导体器件。

22. 发明申请

US20100248467A1 METHOD FOR FABRICATING NONVOLATILE MEMORY DEVICE 审中-公开
标题翻译：用于制造非易失性存储器件的方法
公开(公告)号：US20100248467A1
公开(公告)日：2010-09-30
申请号：US12493706
申请日：2009-06-29
申请人： Tae-Hyoung Kim , Myung-Ok Kim
发明人： Tae-Hyoung Kim , Myung-Ok Kim
IPC分类号： H01L21/28
CPC分类号： H01L29/66825 , H01L29/40114
摘要： Disclosed is a method for fabricating a nonvolatile memory device having a stacked gate structure in which a floating gate, a charge blocking layer, and a control gate are sequentially stacked. The method includes forming a first conductive layer for floating gate over a substrate; forming a charge blocking layer and a second conductive layer for control gate over a resulting structure including the first conductive layer; forming an etch mask pattern over the second conductive layer; performing a primary etch process on the second conductive layer until the charge blocking layer is exposed; forming a passivation layer on a sidewall of the second conductive layer exposed by the primary etch process; and performing a secondary etch process on the charge blocking layer and the first conductive layer.
摘要翻译：公开了一种制造具有层叠栅极结构的非易失性存储器件的方法，其中浮栅，电荷阻挡层和控制栅依次层叠。该方法包括在衬底上形成浮栅的第一导电层; 在包括所述第一导电层的所得结构上形成电荷阻挡层和用于控制栅极的第二导电层; 在所述第二导电层上形成蚀刻掩模图案; 在所述第二导电层上执行初始蚀刻工艺，直到所述电荷阻挡层暴露; 在由第一蚀刻工艺暴露的第二导电层的侧壁上形成钝化层; 以及对所述电荷阻挡层和所述第一导电层执行二次蚀刻工艺。

23. 发明授权

US07749912B2 Method for fabricating bulb-shaped recess pattern 失效
标题翻译：制造灯泡形凹槽图案的方法
公开(公告)号：US07749912B2
公开(公告)日：2010-07-06
申请号：US11748617
申请日：2007-05-15
申请人： Myung-Ok Kim , Tae-Hyoung Kim
发明人： Myung-Ok Kim , Tae-Hyoung Kim
IPC分类号： H01L21/302
CPC分类号： H01L21/3086 , H01L21/3065 , H01L21/31116 , H01L21/31122 , H01L29/4236 , H01L29/66621
摘要： A method for fabricating a bulb-shaped recess pattern includes: forming an etch barrier layer over a substrate; forming a hard mask pattern in which a first polymer is attached to sidewalls of the hard mask pattern over the etch barrier layer; sequentially etching the etch barrier layer and the substrate to form a recess pattern in which a second polymer is attached to sidewalls of the recess pattern; removing the first and second polymers and the hard mask pattern; forming a plurality of spacers exposing a bottom portion of the recess pattern; and etching the exposed bottom portion of the recess pattern to form a ball pattern.
摘要翻译：一种用于制造球形凹槽图案的方法包括：在衬底上形成蚀刻阻挡层; 形成硬掩模图案，其中第一聚合物附着在蚀刻阻挡层上的硬掩模图案的侧壁上; 依次蚀刻蚀刻阻挡层和基底以形成其中第二聚合物附着到凹槽图案的侧壁上的凹陷图案; 去除第一和第二聚合物和硬掩模图案; 形成暴露所述凹部图形的底部的多个间隔件; 并且蚀刻凹陷图案的暴露的底部部分以形成球形图案。

24. 发明申请

US20100120218A1 METHOD FOR FABRICATING PARTIAL SOI SUBSTRATE 失效
标题翻译：制造部分SOI衬底的方法
公开(公告)号：US20100120218A1
公开(公告)日：2010-05-13
申请号：US12492724
申请日：2009-06-26
申请人： Myung-Ok Kim
发明人： Myung-Ok Kim
IPC分类号： H01L21/762 , H01L21/36
CPC分类号： H01L21/76283 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/02647 , H01L21/76224 , H01L21/84 , H01L27/10844
摘要： A method for fabricating a partial silicon-on-insulator (SOI) substrate is disclosed. The method for fabricating a partial silicon-on-insulator (SOI) substrate includes forming an insulation pattern over a first silicon layer, forming a second silicon layer over the substrate structure including the insulation pattern, etching the second silicon layer to form trenches, and forming device isolation regions filling the trenches.
摘要翻译：公开了一种用于制造部分绝缘体上硅（SOI）衬底的方法。部分绝缘上绝缘体（SOI）衬底的制造方法包括在第一硅层上形成绝缘图案，在包括绝缘图案的衬底结构之上形成第二硅层，蚀刻第二硅层以形成沟槽，以及形成装置隔离区填充沟槽。

25. 发明申请

US20070111467A1 Method for forming trench using hard mask with high selectivity and isolation method for semiconductor device using the same 审中-公开
标题翻译：使用硬掩模形成沟槽的方法，使用该半导体器件具有高选择性和隔离方法
公开(公告)号：US20070111467A1
公开(公告)日：2007-05-17
申请号：US11403065
申请日：2006-04-11
申请人： Myung-Ok Kim
发明人： Myung-Ok Kim
IPC分类号： H01L21/762 , H01L21/467
CPC分类号： H01L21/76224 , H01L21/3065 , H01L21/3081 , H01L21/31116 , H01L21/31122 , H01L21/31138
摘要： Provided are a method for forming a trench using a hard mask with high selectivity and an isolation method for a semiconductor device using the same. The method includes: forming a first hard mask over a substrate, the first hard mask including an oxide layer and a nitride layer; forming a second hard mask with high selectivity over the first hard mask; forming an etch barrier layer and an anti-reflective coating layer over the second hard mask; forming a photosensitive pattern over the anti-reflective coating layer; etching the anti-reflective coating layer, the etch barrier layer and the second hard mask using the photosensitive pattern as an etch barrier; etching the first hard mask and the substrate using the second hard mask as an etch barrier to form a trench; and removing the second hard mask.
摘要翻译：提供一种使用具有高选择性的硬掩模形成沟槽的方法以及使用该沟槽的半导体器件的隔离方法。该方法包括：在衬底上形成第一硬掩模，第一硬掩模包括氧化物层和氮化物层; 在第一硬掩模上形成具有高选择性的第二硬掩模; 在所述第二硬掩模上形成蚀刻阻挡层和抗反射涂层; 在所述抗反射涂层上形成感光图案; 使用感光图案作为蚀刻阻挡层蚀刻抗反射涂层，蚀刻阻挡层和第二硬掩模; 使用第二硬掩模蚀刻第一硬掩模和基板作为蚀刻阻挡层以形成沟槽; 并移除第二硬掩模。

26. 发明申请

US20060284228A1 Semiconductor device and method for fabricating the same 失效
公开(公告)号：US20060284228A1
公开(公告)日：2006-12-21
申请号：US11360142
申请日：2006-02-22
申请人： Sung-Kwon Lee , Myung-Ok Kim
发明人： Sung-Kwon Lee , Myung-Ok Kim
IPC分类号： H01L29/94
CPC分类号： H01L29/94 , H01L28/91
摘要： A method for fabricating a three dimensional type capacitor is provided. The method includes forming a first insulation layer including first contact layers over a substrate, forming a second insulation layer over the first insulation layer, forming second contact layers by using a material having an etch selectivity different from the first contact layers such that the second contact layers are connected with the first contact layers within the second insulation layer, forming an etch stop layer over the second insulation layer and the second contact layers, forming a third insulation layer over the etch stop layer, etching the third insulation layer and the etch stop layer to form first contact holes exposing the second contact layers, etching the exposed second contact layers to form second contact holes exposing the first contact holes, and forming bottom electrodes over the inner surface of the second contact holes.

27. 发明申请

US20060246730A1 Method for fabricating transistor of semiconductor device 有权
标题翻译：制造半导体器件晶体管的方法
公开(公告)号：US20060246730A1
公开(公告)日：2006-11-02
申请号：US11321591
申请日：2005-12-30
申请人： Myung-Ok Kim , Tae-Woo Jung , Sung-Kwon Lee , Sea-Ug Jang
发明人： Myung-Ok Kim , Tae-Woo Jung , Sung-Kwon Lee , Sea-Ug Jang
IPC分类号： H01L21/311
CPC分类号： H01L21/31116 , H01L29/66621
摘要： A method for fabricating a transistor of a semiconductor device is provided. The method includes: forming device isolation layers in a substrate including a bottom structure, thereby defining an active region; etching the active region to a predetermined depth to form a plurality of recess structures each of which has a flat bottom portion with a critical dimension (CD) larger than that of a top portion; and sequentially forming a gate oxide layer and a metal layer on the recess structures; and patterning the gate oxide layer and the metal layer to form a plurality of gate structures.
摘要翻译：提供一种制造半导体器件的晶体管的方法。该方法包括：在包括底部结构的衬底中形成器件隔离层，从而限定有源区; 将活性区域蚀刻到预定深度以形成多个凹部结构，每个凹部结构具有平坦的底部，其临界尺寸（CD）大于顶部部分的临界尺寸; 并且在所述凹部结构上依次形成栅极氧化物层和金属层; 以及图案化栅极氧化物层和金属层以形成多个栅极结构。

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