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21. 发明授权

US06544886B2 Process for isolating an exposed conducting surface 有权
公开(公告)号：US06544886B2
公开(公告)日：2003-04-08
申请号：US09574731
申请日：2000-05-18
申请人： Jiong-Ping Lu , Qi-Zhong Hong , Duane E. Carter , Yung Liu
发明人： Jiong-Ping Lu , Qi-Zhong Hong , Duane E. Carter , Yung Liu
IPC分类号： H01L214763
CPC分类号： H01L21/02244 , H01L21/02178 , H01L21/02252 , H01L21/02255 , H01L21/28562 , H01L21/31683 , H01L21/76831 , H01L21/76834 , H01L21/76888
摘要： A method of isolating an exposed conductive surface. An aluminum layer (130) is selectively formed over the exposed conductive (106) surface (e.g., Cu) but not over the surrounding dielectric (110) surface using a thermal CVD process. The aluminum layer (130) is then oxidized to form a thin isolating aluminum-oxide (108) over only the conductive surface. The isolating aluminum-oxide provides a barrier for the Cu while taking up minimal space and reducing the effective dielectric constant.

22. 发明授权

US06451646B1 High-k dielectric materials and processes for manufacturing them 有权
标题翻译：高k电介质材料及其制造方法
公开(公告)号：US06451646B1
公开(公告)日：2002-09-17
申请号：US09651475
申请日：2000-08-30
申请人： Jiong-Ping Lu , Ming-Jang Hwang
发明人： Jiong-Ping Lu , Ming-Jang Hwang
IPC分类号： H01L218242
CPC分类号： C23C16/34 , C23C16/56 , H01L21/31604 , H01L21/31637 , H01L21/31683 , H01L27/1085 , H01L28/40 , H01L28/57
摘要： High dielectric films of mixed transition metal oxides of titanium and tungsten, or titanium and tantalum, are formed by sequential chemical vapor deposition (CVD) of the respective nitrides and annealing in the presence of oxygen to densify and oxidize the nitrides. The resulting film is useful as a capacitative cell and resists oxygen diffusion to the underlying material, has high capacitance and low current leakage.
摘要翻译：通过相应氮化物的顺序化学气相沉积（CVD）形成钛和钨或钛和钽的混合过渡金属氧化物的高介电膜，并在氧的存在下退火以致密化和氧化氮化物。所得到的膜可用作电容性电池并且抵抗向下层材料的氧扩散，具有高电容和低电流泄漏。

23. 发明授权

US06245672B1 Method of forming diffusion barriers for copper metallization in integrated cirucits 有权
标题翻译：在集成的铁芯中形成铜金属化的扩散阻挡层的方法
公开(公告)号：US06245672B1
公开(公告)日：2001-06-12
申请号：US09177412
申请日：1998-10-23
申请人： Qi-Zhong Hong , Wei-Yung Hsu , Jiong-Ping Lu , Robert H. Havemann
发明人： Qi-Zhong Hong , Wei-Yung Hsu , Jiong-Ping Lu , Robert H. Havemann
IPC分类号： H01L214763
CPC分类号： H01L21/76856 , H01L21/76843 , H01L21/76855
摘要： An integrated circuit structure including copper metallization (20, 32, 42), and a method of fabricating the same are disclosed. The structure includes a doped region (7) of a silicon substrate (9), which is typically clad with a metal silicide film (12) formed by way of direct react silicidation. At contact locations (CT) at which the copper metallization (20, 32, 42) is to make contact to the doped region (7), a chemically-densified barrier layer (16, 30, 38) provides a diffusion barrier to the overlying copper metallization (20, 32, 42). The chemically-densified barrier layer (16, 30, 38) is formed by an anneal of the structure to react impurities (14, 28, 36) with the underlying refractory-metal-based film (12, 34); the impurities are introduced by way of wet chemistry, plasma bombardment, or from the ambient in which the structure is annealed.
摘要翻译：公开了一种包括铜金属化（20,32,42）的集成电路结构及其制造方法。该结构包括硅衬底（9）的掺杂区域（7），其通常用通过直接反应硅化形成的金属硅化物膜（12）包覆。在铜金属化层（20,32,42）将与掺杂区域（7）接触的接触位置（CT）处，化学致密化的势垒层（16,30,38）为覆盖层铜金属化（20,32,42）。化学致密化的阻挡层（16,30,38）通过该结构的退火形成，以使杂质（14,28,36）与下面的耐熔金属基膜（12,34）反应; 杂质通过湿化学，等离子体轰击或结构退火的环境引入。

24. 发明授权

US06218732B1 Copper bond pad process 有权
标题翻译：铜焊垫工艺
公开(公告)号：US06218732B1
公开(公告)日：2001-04-17
申请号：US09354510
申请日：1999-07-15
申请人： Stephen W. Russell , Jiong-Ping Lu
发明人： Stephen W. Russell , Jiong-Ping Lu
IPC分类号： H01L2348
CPC分类号： H01L24/02 , H01L24/45 , H01L2224/04042 , H01L2224/45124 , H01L2224/45144 , H01L2224/85375 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01084 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2224/48
摘要： An integrated circuit utilizing copper wiring has copper bond pads which are covered with a passivation layer to prevent unwanted reactions of the copper with metals which are bonded to it. The passivation layer can be an intermetallic of copper and titanium or a stacked layer of CuTix/TiN. Various nitrides can also be used, such as tungsten nitride, tantalum nitride, titanium silicon nitride, tungsten silicon nitride, and tantalum silicon nitride.
摘要翻译：使用铜布线的集成电路具有铜焊盘，其被钝化层覆盖以防止铜与被粘合的金属的不期望的反应。钝化层可以是铜和钛的金属间化合物或CuTix / TiN的堆叠层。还可以使用氮化物，氮化钨，氮化钽，氮化硅，氮化钨，氮化钽等氮化物。

25. 发明授权

US08546259B2 Nickel silicide formation for semiconductor components 有权
标题翻译：半导体元件的硅化镍形成
公开(公告)号：US08546259B2
公开(公告)日：2013-10-01
申请号：US11861421
申请日：2007-09-26
申请人： Juanita DeLoach , Jiong-Ping Lu , Haowen Bu
发明人： Juanita DeLoach , Jiong-Ping Lu , Haowen Bu
IPC分类号： H01L21/44
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/28052 , H01L21/28518 , H01L29/7833
摘要： Semiconductor components are often fabricated that include a nickel silicide layer, e.g., as part of a gate electrode in a transistor component, which may be formed by forming a layer of nickel on a silicon-containing area of the semiconductor substrate, followed by thermally annealing the semiconductor substrate to produce a nickel silicide. However, nickel may tend to diffuse into silicon during the thermal anneal, and may form crystals that undesirably increase the sheet resistance in the transistor. Carbon may be placed with the nickel to serve as a diffusion suppressant and/or to prevent nickel crystal formation during thermal annealing. Methods are disclosed for utilizing this technique, as well as semiconductor components formed in accordance with this technique.
摘要翻译：通常制造半导体部件，其包括硅化镍层，例如，作为晶体管部件中的栅电极的一部分，其可以通过在半导体衬底的含硅区域上形成镍层，然后进行热退火半导体衬底以产生硅化镍。然而，镍可能在热退火期间扩散到硅中，并且可能形成不期望地增加晶体管中的薄层电阻的晶体。碳可以与镍一起放置以用作扩散抑制剂和/或防止在热退火期间形成镍晶体。公开了利用该技术的方法以及根据该技术形成的半导体部件。

26. 发明申请

US20080265420A1 METHOD OF FORMING A FULLY SILICIDED SEMICONDUCTOR DEVICE WITH INDEPENDENT GATE AND SOURCE/DRAIN DOPING AND RELATED DEVICE 有权
标题翻译：形成具有独立栅极和源/漏极掺杂的完全硅化半导体器件的方法及相关器件
公开(公告)号：US20080265420A1
公开(公告)日：2008-10-30
申请号：US11741540
申请日：2007-04-27
申请人： Shaofeng Yu , Freidoon Mehrad , Jiong-Ping Lu
发明人： Shaofeng Yu , Freidoon Mehrad , Jiong-Ping Lu
IPC分类号： H01L21/3205 , H01L23/48
CPC分类号： H01L21/28097 , H01L29/66507 , H01L29/66545
摘要： A method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate (the gate stack comprising a polysilicon layer and a blocking layer), and performing an ion implantation into an active region of the substrate adjacent to the gate stack (the blocking layer substantially blocks the ion implantation from the polysilicon layer).
摘要翻译：一种形成具有独立栅极和源极/漏极掺杂及相关器件的完全硅化半导体器件的方法。示例性实施例中的至少一些是包括在衬底上形成栅极堆叠的方法（包括多晶硅层和阻挡层的栅极堆叠），以及执行离子注入到与栅极堆叠相邻的衬底的有源区域中阻挡层基本上阻挡从多晶硅层的离子注入）。

27. 发明授权

US07348265B2 Semiconductor device having a silicided gate electrode and method of manufacture therefor 失效
标题翻译：具有硅化栅电极的半导体器件及其制造方法
公开(公告)号：US07348265B2
公开(公告)日：2008-03-25
申请号：US10790606
申请日：2004-03-01
申请人： Jiong-Ping Lu
发明人： Jiong-Ping Lu
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/28052 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device (100), among other possible elements, includes a gate oxide (140) located over a substrate (110), and a silicided gate electrode (150) located over the gate oxide (140), wherein the silicided gate electrode (150) includes a first metal and a second metal.
摘要翻译：本发明提供一种半导体器件及其制造方法以及包括半导体器件的集成电路。半导体器件（100）以及其他可能的元件中包括位于衬底（110）上方的栅极氧化物（140）和位于栅极氧化物（140）上方的硅化栅电极（150），其中硅化栅电极 150）包括第一金属和第二金属。

28. 发明申请

US20080064175A1 Low Stress Sacrificial Cap Layer 有权
标题翻译：低应力牺牲帽层
公开(公告)号：US20080064175A1
公开(公告)日：2008-03-13
申请号：US11940433
申请日：2007-11-15
申请人： Jiong-Ping Lu , Periannan Chidambaram , Srinivasan Chakravarthi
发明人： Jiong-Ping Lu , Periannan Chidambaram , Srinivasan Chakravarthi
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/3185 , H01L21/324 , H01L29/6656 , H01L29/6659
摘要： A low stress sacrificial cap layer 120 having a silicon oxide liner film 130, a low stress silicon film 140, and a silicon nitride film. Alternatively, a low stress sacrificial cap layer 410 having a silicon oxide liner film 130 and a graded silicon nitride film 420. Also, methods 300, 500 for fabricating a transistor 20, 400 having a low stress sacrificial cap layer 120, 410.
摘要翻译：具有氧化硅衬垫膜130，低应力硅膜140和氮化硅膜的低应力牺牲帽层120。或者，具有氧化硅衬垫膜130和梯度氮化硅膜420的低应力牺牲帽层410。而且，用于制造具有低应力牺牲帽层120,410的晶体管20,400的方法300,500。

29. 发明授权

US07253124B2 Process for defect reduction in electrochemical plating 有权
标题翻译：电化学电镀中缺陷减少的工艺
公开(公告)号：US07253124B2
公开(公告)日：2007-08-07
申请号：US09971210
申请日：2001-10-04
申请人： Jiong-Ping Lu , Patricia B. Smith
发明人： Jiong-Ping Lu , Patricia B. Smith
IPC分类号： H01L21/26
CPC分类号： H01L21/76864 , H01L21/02068 , H01L21/321 , H01L21/76838 , H01L21/76843 , H01L21/76873
摘要： A pre-ECD surface treatment. After forming the barrier material (110) and seed layer (112), the surface of the seed layer (112) is treated with an H2 plasma to remove surface contamination (122), reduce any CuOx (123), and improve wettability. The ECD copper film (124) is then formed over the seed layer (112).
摘要翻译：前ECD表面处理。在形成阻挡材料（110）和种子层（112）之后，种子层（112）的表面用H 2 H 2等离子体处理以除去表面污染物（122），减少任何CuO （123），并提高润湿性。然后在种子层（112）上形成ECD铜膜（124）。

30. 发明申请

US20070063294A1 Semiconductor Device Having a Fully Silicided Gate Electrode and Method of Manufacture Therefor 审中-公开
标题翻译：具有全硅酸盐栅电极的半导体器件及其制造方法
公开(公告)号：US20070063294A1
公开(公告)日：2007-03-22
申请号：US11556834
申请日：2006-11-06
申请人： Haowen Bu , Jiong-Ping Lu , Shaofeng Yu , Ping Jiang , Clint Montgomery
发明人： Haowen Bu , Jiong-Ping Lu , Shaofeng Yu , Ping Jiang , Clint Montgomery
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00 , H01L27/108 , H01L31/119
CPC分类号： H01L29/66507 , H01L21/28097 , H01L21/823835 , H01L21/823864 , H01L29/4975 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a silicided gate electrode (150) located over a substrate (110), the silicided gate electrode (150) having gate sidewall spacers (160) located on sidewalls thereof. The semiconductor device (100) further includes source/drain regions (170) located in the substrate (110) proximate the silicided gate electrode (150), and silicided source/drain regions (180) located in the source/drain regions (170) and at least partially under the gate sidewall spacers (160).
摘要翻译：本发明提供一种半导体器件及其制造方法以及集成电路的制造方法。除了其它可能的元件之外，半导体器件（100）包括位于衬底（110）上方的硅化栅电极（150），硅化栅电极（150）具有位于其侧壁上的栅极侧壁间隔物（160）。半导体器件（100）还包括位于靠近硅化物栅电极（150）的衬底（110）中的源/漏区（170）和位于源/漏区（170）中的硅化源/漏区（180）并且至少部分地在栅极侧壁间隔件（160）下方。

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