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21. 发明授权

US08737132B2 Charge cycling by equalizing the source and bit line levels between pulses during no-verify write operations for NAND flash memory 有权
标题翻译：通过在NAND闪存的非验证写入操作期间均衡脉冲之间的源和位线电平来进行充电循环
公开(公告)号：US08737132B2
公开(公告)日：2014-05-27
申请号：US13570826
申请日：2012-08-09
申请人： Hao Thai Nguyen , Juan Carlos Lee , Seungpil Lee , Jongmin Park , Man Lung Mui
发明人： Hao Thai Nguyen , Juan Carlos Lee , Seungpil Lee , Jongmin Park , Man Lung Mui
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/3454 , G11C2211/5621
摘要： In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. In some cases a non-volatile memory is programmed by an alternating set of pulses, but, for at least some pulses without any intervening verify operations. After a one pulse, but before biasing the memory for the next pulse without an intervening very, the source and bit line levels can be left to float.
摘要翻译：在非易失性存储器件中，写入通常由交替的脉冲和验证操作组成。在脉冲结束时，器件必须被正确偏置才能进行准确的校验，之后器件被重新偏置用于下一个脉冲。在一些情况下，非易失性存储器通过交替的脉冲组编程，但对于至少一些没有任何中间验证操作的脉冲。在一个脉冲之后，但是在将存储器偏置在下一个脉冲之前，不会中断，源和位线电平可以保持浮动。

22. 发明申请

US20130258772A1 Non-Volatile Memory and Method Having a Memory Array with a High-Speed, Short Bit-Line Portion 有权
标题翻译：具有高速，短位线部分的存储器阵列的非易失性存储器和方法
公开(公告)号：US20130258772A1
公开(公告)日：2013-10-03
申请号：US13431670
申请日：2012-03-27
申请人： Seungpil Lee , Jongmin Park
发明人： Seungpil Lee , Jongmin Park
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C7/18 , G11C11/5621 , G11C16/0425 , G11C16/0433 , G11C2211/5641
摘要： A non-volatile memory array is partitioned along the column direction into first and second portions. The first portion has SLC memory cells and the second portion has MLC memory cells. The first portion acts as a fast cache memory for the second portion. The read/write operations of the first portion are further enhanced by coupling to a set of read/write circuits immediately adjacent to the first portion, while the column of each bit line is switchably cut off at the junction between the first and second portions. In this way, the RC constant of the cut off bit line is at a minimum, which translates to faster precharge of the bit line via the read/write circuits. When the second portion is operating, its access to the set of read/write circuits is accomplished by not cutting off each bit line at the junction between the first and second portions.
摘要翻译：沿着列方向将非易失性存储器阵列分割成第一和第二部分。第一部分具有SLC存储单元，第二部分具有MLC存储单元。第一部分用作第二部分的快速缓存。通过耦合到与第一部分相邻的一组读/写电路，第一部分的读/写操作进一步增强，同时每个位线的列在第一和第二部分之间的连接处可切换地切断。以这种方式，截止位线的RC常数处于最小值，这通过读/写电路转换为更快的位线预充电。当第二部分工作时，其通过不切断第一和第二部分之间的连接处的每个位线来实现对该组读/写电路的访问。

23. 发明申请

US20130223155A1 TEMPERATURE BASED COMPENSATION DURING VERIFY OPERATIONS FOR NON-VOLATILE STORAGE 有权
标题翻译：在非易失性存储的验证操作期间基于温度的补偿
公开(公告)号：US20130223155A1
公开(公告)日：2013-08-29
申请号：US13403934
申请日：2012-02-23
申请人： Ken Oowada , Yingda Dong , Gerrit Jan Hemink , Man Lung Mui , Hao Nguyen , Seungpil Lee , Jong Park , Fanglin Zhang
发明人： Ken Oowada , Yingda Dong , Gerrit Jan Hemink , Man Lung Mui , Hao Nguyen , Seungpil Lee , Jong Park , Fanglin Zhang
IPC分类号： G11C16/10
CPC分类号： G11C16/06 , G11C7/04 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/34 , G11C16/3454 , G11C16/3459 , G11C16/3481 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.
摘要翻译：执行编程和读取过程的非易失性存储系统。编程过程包括粗/精编程和验证操作。通过测试两个不同的阈值电压电平来验证编程，同时通过测试存储器单元的电流水平并基于当前温度调整测试的电流水平，将相同的电压电平施加到存储器单元的控制栅极，使得两个有效的测试阈值电压水平在温度变化上保持恒定。

24. 发明申请

US20110261625A1 Low Noise Sense Amplifier Array and Method for Nonvolatile Memory 有权
标题翻译：低噪声检测放大器阵列和非易失性存储器的方法
公开(公告)号：US20110261625A1
公开(公告)日：2011-10-27
申请号：US13178690
申请日：2011-07-08
申请人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee
发明人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee
IPC分类号： G11C16/26
CPC分类号： G11C7/02 , G11C7/065 , G11C7/08 , G11C7/12 , G11C11/5642 , G11C16/26
摘要： In sensing a page of nonvolatile memory cells with a corresponding group of sense modules in parallel, as each high current cell is identified, it is locked out from further sensing while others in the page continued to be sensed. The sense module involved in the locked out is then in a lockout mode and becomes inactive. A noise source from the sense module becomes significant when in the lockout mode. The noise is liable to interfere with the sensing of neighboring cells by coupling through its bit line to neighboring ones. The noise can also couple through the common source line of the page to affect the accuracy of ongoing sensing of the cells in the page. Improved sense modules and method isolate the noise from the lockout sense module from affecting the other sense modules still active in sensing memory cell in the page.
摘要翻译：在感测具有对应的一组感测模块的非易失性存储器单元的页面中，当识别出每个高电流单元时，它被锁定以进一步感测，而页面中的其他单元继续被感测。被锁定的感测模块处于锁定模式并变为非活动状态。当处于锁定模式时，来自感测模块的噪声源变得显着。通过将其位线耦合到邻近单元，噪声容易干扰相邻单元的感测。噪声也可以通过页面的公共源行耦合，以影响页面中单元格的持续感测的准确性。改进的感测模块和方法将噪声与锁定感测模块隔离，以影响在页面中感测存储器单元中仍然有效的其他感测模块。

25. 发明申请

US20100008148A1 Low Noise Sense Amplifier Array and Method for Nonvolatile Memory 有权
标题翻译：低噪声检测放大器阵列和非易失性存储器的方法
公开(公告)号：US20100008148A1
公开(公告)日：2010-01-14
申请号：US12563918
申请日：2009-09-21
申请人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee
发明人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee
IPC分类号： G11C16/26 , G11C7/00 , G11C16/06
CPC分类号： G11C7/02 , G11C7/065 , G11C7/08 , G11C7/12 , G11C11/5642 , G11C16/26
摘要： In sensing a page of nonvolatile memory cells with a corresponding group of sense modules in parallel, as each high current cell is identified, it is locked out from further sensing while others in the page continued to be sensed. The sense module involved in the locked out is then in a lockout mode and becomes inactive. A noise source from the sense module becomes significant when in the lockout mode. The noise is liable to interfere with the sensing of neighboring cells by coupling through its bit line to neighboring ones. The noise can also couple through the common source line of the page to affect the accuracy of ongoing sensing of the cells in the page. Improved sense modules and method isolate the noise from the lockout sense module from affecting the other sense modules still active in sensing memory cell in the page.
摘要翻译：在感测具有对应的一组感测模块的非易失性存储器单元的页面中，当识别出每个高电流单元时，它被锁定以进一步检测，而页面中的其他单元继续被感测。被锁定的感测模块处于锁定模式并变为非活动状态。当处于锁定模式时，来自感测模块的噪声源变得显着。通过将其位线耦合到邻近单元，噪声容易干扰相邻单元的感测。噪声也可以通过页面的公共源行耦合，以影响页面中单元格的持续感测的准确性。改进的感测模块和方法将噪声与锁定感测模块隔离，以影响在页面中感测存储器单元中仍然有效的其他感测模块。

26. 发明授权

US07606076B2 Sensing in non-volatile storage using pulldown to regulated source voltage to remove system noise 有权
标题翻译：在非易失性存储器中使用下拉调节源电压来消除系统噪声
公开(公告)号：US07606076B2
公开(公告)日：2009-10-20
申请号：US12099439
申请日：2008-04-08
申请人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee , Chi-Ming Wang
发明人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee , Chi-Ming Wang
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/24 , G11C11/5621 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3427 , G11C16/3454
摘要： A pull down circuit pulls a bit line voltage to a regulated source voltage in a non-volatile storage device during a sense operation such as a verify operation which occurs during programming. The storage device may include NAND strings which have associated bit lines and sense components, and a common source line. When a selected storage element of a NAND string has been programmed to its intended state, the bit line is locked out during subsequent verify operations which occur for other NAND strings which are not yet locked out. The pull down device is coupled to each bit line and to the common source line, whose voltage is regulated at a positive DC level, to prevent coupling of system power bus (VSS) noise from the locked out bit lines to the not yet locked out bit lines.
摘要翻译：下拉电路在诸如在编程期间发生的验证操作的感测操作期间将位线电压拉到非易失性存储设备中的稳压源电压。存储设备可以包括具有相关联的位线和感测组件的NAND串，以及公共源线。当NAND串的所选择的存储元件已被编程到其预期状态时，在对尚未被锁定的其它NAND串发生的后续验证操作期间，位线被锁定。下拉装置耦合到每个位线和公共源极线，其电压被调节在正的直流电平，以防止将系统电源总线（VSS）噪声从锁定的位线耦合到尚未锁定位线。

27. 发明授权

US07532516B2 Non-volatile storage with current sensing of negative threshold voltages 有权
标题翻译：具有电流检测负阈值电压的非易失性存储器
公开(公告)号：US07532516B2
公开(公告)日：2009-05-12
申请号：US11771987
申请日：2007-06-29
申请人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
发明人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C2211/5621 , G11C2211/5623 , G11C2211/5634 , G11C2211/565
摘要： A non-volatile storage device in which current sensing is performed for a non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.
摘要翻译：一种非易失性存储装置，其中对具有负阈值电压的非易失性存储元件执行电流检测。控制栅极读取电压被施加到非易失性存储元件的选定字线，并且源极和p阱电压分别施加到与非易失性存储元件相关联的源极和p阱。源极和p阱电压超过控制栅极读取电压，从而可以使用正极控制栅极读取电压。即使用于感测负阈值电压，也不需要负电荷泵来施加负字线电压。通过感测与在非易失性存储元件的NAND串中流动的固定电流相关联的电压降来确定非易失性存储元件的编程条件。

28. 发明申请

US20090080265A1 MULTIPLE BIT LINE VOLTAGES BASED ON DISTANCE 有权
标题翻译：基于距离的多位线路电压
公开(公告)号：US20090080265A1
公开(公告)日：2009-03-26
申请号：US11861571
申请日：2007-09-26
申请人： Nima Mokhlesi , Dengtao Zhao , Man Mui , Hao Nguyen , Seungpil Lee , Deepak Chandra Sekar , Tapan Samaddar
发明人： Nima Mokhlesi , Dengtao Zhao , Man Mui , Hao Nguyen , Seungpil Lee , Deepak Chandra Sekar , Tapan Samaddar
IPC分类号： G11C16/24 , G11C7/12 , G11C16/26
CPC分类号： G11C16/0483 , G11C7/12 , G11C11/5642 , G11C16/24 , G11C16/26 , G11C2211/5634
摘要： An array of non-volatile storage elements includes a first group of non-volatile storage elements connected to a selected word line, a second group of non-volatile storage elements connected to the selected word line, a first group of bit lines in communication with the first group of non-volatile storage elements, a second group of bit lines in communication with the second group of non-volatile storage elements, a first set of sense modules located at a first location and connected to the first group of bit lines, and a second set of sense modules located at a second location and connected to the second group of bit lines. The first set of sense modules applies a first bit line voltage based on the bit line distance between the first set of sense modules and the first group of non-volatile storage elements. The second set of sense modules applies a second bit line voltage based on the bit line distance between the second set of sense modules and the second group of non-volatile storage elements.
摘要翻译：非易失性存储元件的阵列包括连接到所选字线的第一组非易失性存储元件，连接到所选择的字线的第二组非易失性存储元件，与所选字线连接的第一组位线第一组非易失性存储元件，与第二组非易失性存储元件通信的第二组位线，位于第一位置并连接到第一组位线的第一组感测模块，以及位于第二位置并连接到第二组位线的第二组感测模块。第一组感测模块基于第一组感测模块和第一组非易失性存储元件之间的位线距离来施加第一位线电压。第二组感测模块基于第二组感测模块和第二组非易失性存储元件之间的位线距离来施加第二位线电压。

29. 发明授权

US07489554B2 Method for current sensing with biasing of source and P-well in non-volatile storage 有权
标题翻译：用于在非易失性存储器中源和P阱偏置的电流感测方法
公开(公告)号：US07489554B2
公开(公告)日：2009-02-10
申请号：US11771992
申请日：2007-06-29
申请人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu
发明人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C2211/5621 , G11C2211/5623 , G11C2211/5634 , G11C2211/565
摘要： Current sensing is performed in a non-volatile storage device for a non-volatile storage element. A voltage is applied to a selected word line of the first non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages are regulated at respective positive DC levels to avoid a ground bounce, or voltage fluctuation, which would occur if the source voltage at least was regulated at a ground voltage. A programming condition of the non-volatile storage element is determined by sensing a current in a NAND string of the non-volatile storage element. The sensing can occur quickly since there is no delay in waiting for the ground bounce to settle.
摘要翻译：在用于非易失性存储元件的非易失性存储设备中执行电流检测。对第一非易失性存储元件的选定字线施加电压，并且将源极和p阱电压分别施加到与非易失性存储元件相关联的源极和p阱。源极和p阱电压在相应的正直流电平下被调节，以避免地电压或电压波动，如果源电压至少在接地电压下被调节，则会发生接地反弹或电压波动。通过感测非易失性存储元件的NAND串中的电流来确定非易失性存储元件的编程条件。感觉可以快速发生，因为等待地面反弹稳定没有延迟。

30. 发明申请

US20080247241A1 SENSING IN NON-VOLATILE STORAGE USING PULLDOWN TO REGULATED SOURCE VOLTAGE TO REMOVE SYSTEM NOISE 有权
标题翻译：使用推挽方式将非挥发性储存感知到调节源电压以移除系统噪声
公开(公告)号：US20080247241A1
公开(公告)日：2008-10-09
申请号：US12099439
申请日：2008-04-08
申请人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee , Chi-Ming Wang
发明人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee , Chi-Ming Wang
IPC分类号： G11C16/06
CPC分类号： G11C16/24 , G11C11/5621 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3427 , G11C16/3454
摘要： A pull down circuit pulls a bit line voltage to a regulated source voltage in a non-volatile storage device during a sense operation such as a verify operation which occurs during programming. The storage device may include NAND strings which have associated bit lines and sense components, and a common source line. When a selected storage element of a NAND string has been programmed to its intended state, the bit line is locked out during subsequent verify operations which occur for other NAND strings which are not yet locked out. The pull down device is coupled to each bit line and to the common source line, whose voltage is regulated at a positive DC level, to prevent coupling of system power bus (VSS) noise from the locked out bit lines to the not yet locked out bit lines.
摘要翻译：下拉电路在诸如在编程期间发生的验证操作的感测操作期间将位线电压拉到非易失性存储设备中的稳压源电压。存储设备可以包括具有相关联的位线和感测组件的NAND串，以及公共源线。当NAND串的所选择的存储元件已被编程到其预期状态时，在对尚未被锁定的其它NAND串发生的后续验证操作期间，位线被锁定。下拉装置耦合到每个位线和公共源极线，其电压被调节为正的直流电平，以防止系统电源总线（V SS SS）噪声与被锁定的位线到尚未锁定的位线。

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