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21. 发明授权

US08397030B2 Efficient region coherence protocol for clustered shared-memory multiprocessor systems 有权
标题翻译：用于集群共享内存多处理器系统的高效区域一致性协议
公开(公告)号：US08397030B2
公开(公告)日：2013-03-12
申请号：US12144759
申请日：2008-06-24
申请人： Jason F. Cantin , Steven R. Kunkel
发明人： Jason F. Cantin , Steven R. Kunkel
IPC分类号： G06F12/08
CPC分类号： G06F12/0833 , G06F12/0822
摘要： A system and method of a region coherence protocol for use in Region Coherence Arrays (RCAs) deployed in clustered shared-memory multiprocessor systems which optimize cache-to-cache transfers by allowing broadcast memory requests to be provided to only a portion of a clustered shared-memory multiprocessor system. Interconnect hierarchy levels can be devised for logical groups of processors, processors on the same chip, processors on chips aggregated into a multichip module, multichip modules on the same printed circuit board, and for processors on other printed circuit boards or in other cabinets. The present region coherence protocol includes, for example, one bit per level of interconnect hierarchy, such that the one bit has a value of “1” to indicate that there may be processors caching copies of lines from the region at that level of the interconnect hierarchy, and the one bit has a value of “0” to indicate that there are no cached copies of any lines from the region at that respective level of the interconnect hierarchy.
摘要翻译：区域一致性协议的系统和方法，用于部署在群集共享存储器多处理器系统中的区域相干阵列（RCA），其通过允许广播存储器请求仅提供给集群共享的一部分来优化高速缓存到高速缓存传输内存多处理器系统。可以为逻辑组处理器，同一芯片上的处理器，集成到多芯片模块中的芯片上的处理器，同一印刷电路板上的多芯片模块以及其他印刷电路板或其他机柜中的处理器设计互连层级。当前区域相干协议包括例如每层次的互连层级中的一位，使得一位具有值1以指示可以存在处理器从互连层级的该级别的区域缓存行的副本，并且一位的值为0，表示在互连层次结构的相应级别的区域中没有任何行的缓存副本。

22. 发明授权

US08229867B2 Bit-selection for string-based genetic algorithms 失效
标题翻译：基于字符串的遗传算法的位选择
公开(公告)号：US08229867B2
公开(公告)日：2012-07-24
申请号：US12277680
申请日：2008-11-25
申请人： Jason F. Cantin , Donald R. DeSota
发明人： Jason F. Cantin , Donald R. DeSota
IPC分类号： G06F17/30
CPC分类号： G06N3/126
摘要： Selecting bits in a string-based genetic algorithm is provided. A type of genetic operation to perform is determined. Responsive to a determination to perform a crossover operation, an input comprising a pair of strings is received. The strings in the pair of strings are compared to identify a set of non-matching points. A set of points from the set of non-matching points is randomly selected, forming a set of randomly selected non-matching points. A new string for the pair of strings is generated using the set of randomly selected non-matching points.
摘要翻译：提供了基于字符串的遗传算法中的位选择。确定一种要执行的遗传操作。响应于执行交叉操作的确定，接收包括一对字符串的输入。将一对字符串中的字符串进行比较以识别一组非匹配点。随机选择来自该组非匹配点的一组点，形成一组随机选择的非匹配点。使用随机选择的非匹配点集合生成一对字符串的新字符串。

23. 发明申请

US20120130929A1 CONTROLLING QUARANTINING AND BIASING IN CATACLYSMS FOR OPTIMIZATION SIMULATIONS 失效
标题翻译：控制优化模拟中的分类和偏差
公开(公告)号：US20120130929A1
公开(公告)日：2012-05-24
申请号：US12954296
申请日：2010-11-24
申请人： Jason F. Cantin
发明人： Jason F. Cantin
IPC分类号： G06N3/12
CPC分类号： G06N99/005 , G06N3/086 , G06N3/126 , G06N7/00
摘要： Some embodiments are directed to generating a first probability value that represents a percentage of times that first bit values for a given bit position of a first plurality of candidate solutions equate to a pre-defined number, where the first plurality of candidate solutions has converged on a sub-optimal solution during a simulation of an optimization problem using an optimization algorithm. Some embodiments are further directed to generating a second probability value that is inversely biased from the first probability value; and generating a second plurality of candidate solutions with the second probability value, where the second plurality of candidate solutions are inversely biased from the first bit values for the given bit position.
摘要翻译：一些实施例涉及生成表示第一多个候选解的给定比特位置的第一比特值等于预定义数量的时间百分比的第一概率值，其中第一多个候选解已经收敛在使用优化算法的优化问题的仿真期间的次优解。一些实施例进一步涉及生成从第一概率值反向偏置的第二概率值; 以及生成具有所述第二概率值的第二多个候选解，其中所述第二多个候选解与所述给定位位置的所述第一位值相反地偏置。

24. 发明授权

US08140766B2 Enhanced coherency tracking with implementation of region victim hash for region coherence arrays 有权
标题翻译：增强了一致性跟踪，实现区域相干阵列的区域受害者散列
公开(公告)号：US08140766B2
公开(公告)日：2012-03-20
申请号：US12177176
申请日：2008-07-22
申请人： Robert H. Bell, Jr. , Jason F. Cantin
发明人： Robert H. Bell, Jr. , Jason F. Cantin
IPC分类号： G06F12/00
CPC分类号： G06F12/082 , G06F12/12 , G06F2212/171
摘要： A method and system for precisely tracking lines evicted from a region coherence array (RCA) without requiring eviction of the lines from a processor's cache hierarchy. The RCA is a set-associative array which contains region entries consisting of a region address tag, a set of bits for the region coherence state, and a line-count for tracking the number of region lines cached by the processor. Tracking of the RCA is facilitated by a non-tagged hash table of counts represented by a Region Victim Hash (RVH). When a region is evicted from the RCA, and lines from the evicted region still reside in the processor's caches (i.e., the region's line-count is non-zero), the RCA line-count is added to the corresponding RVH count. The RVH count is decremented by the value of the region line count following a subsequent processor cache eviction/invalidation of the region previously evicted from the RCA.
摘要翻译：一种用于精确跟踪从区域相干阵列（RCA）中逐出的线而不需要从处理器的高速缓存层次结构中排除线路的方法和系统。 RCA是一个集合关联数组，其中包含由区域地址标签，区域相干状态的一组位组成的区域条目，以及用于跟踪由处理器缓存的区域行数的行计数。通过由区域受害者哈希（RVH）表示的计数的非标记哈希表来促进RCA的跟踪。当区域从RCA中逐出时，并且来自被驱逐区域的线路仍然驻留在处理器的高速缓存中（即，该区域的行计数不为零）时，将RCA线路计数添加到相应的RVH计数。 RVH计数在随后的处理器缓存驱逐/无效以前从RCA中逐出的区域之后减少区域行计数的值。

25. 发明申请

US20100191921A1 REGION COHERENCE ARRAY FOR A MULT-PROCESSOR SYSTEM HAVING SUBREGIONS AND SUBREGION PREFETCHING 有权
标题翻译：用于具有子空间和子帧预处理的模块处理器系统的区域相干阵列
公开(公告)号：US20100191921A1
公开(公告)日：2010-07-29
申请号：US12359665
申请日：2009-01-26
申请人： Jason F. Cantin
发明人： Jason F. Cantin
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0815 , G06F12/0822 , G06F2212/507
摘要： A Region Coherence Array (RCA) having subregions and subregion prefetching for shared-memory multiprocessor systems having a single-level, or a multi-level interconnect hierarchy architecture.
摘要翻译：具有子区域和区域预取的区域相干阵列（RCA），用于具有单级或多级互连层次结构的共享存储器多处理器系统。

26. 发明申请

US20100131439A1 BIT-SELECTION FOR STRING-BASED GENETIC ALGORITHMS 失效
标题翻译：基于STRING的遗传算法的选择
公开(公告)号：US20100131439A1
公开(公告)日：2010-05-27
申请号：US12277680
申请日：2008-11-25
申请人： Jason F. Cantin , Donald R. DeSota
发明人： Jason F. Cantin , Donald R. DeSota
IPC分类号： G06N3/12
CPC分类号： G06N3/126
摘要： Selecting bits in a string-based genetic algorithm is provided. A type of genetic operation to perform is determined. Responsive to a determination to perform a crossover operation, an input comprising a pair of strings is received. The strings in the pair of strings are compared to identify a set of non-matching points. A set of points from the set of non-matching points is randomly selected, forming a set of randomly selected non-matching points. A new string for the pair of strings is generated using the set of randomly selected non-matching points.
摘要翻译：提供了基于字符串的遗传算法中的位选择。确定一种要执行的遗传操作。响应于执行交叉操作的确定，接收包括一对字符串的输入。将一对字符串中的字符串进行比较以识别一组非匹配点。随机选择来自该组非匹配点的一组点，形成一组随机选择的非匹配点。使用随机选择的非匹配点集合生成一对字符串的新字符串。

27. 发明申请

US20100005242A1 Efficient Processing of Data Requests With The Aid Of A Region Cache 有权
标题翻译：利用区域缓存的数据请求进行高效处理
公开(公告)号：US20100005242A1
公开(公告)日：2010-01-07
申请号：US12168209
申请日：2008-07-07
申请人： Jason F. Cantin
发明人： Jason F. Cantin
IPC分类号： G06F12/08
CPC分类号： G06F12/082 , G06F12/0893 , G06F2212/1016 , G06F2212/1028 , G06F2212/601 , Y02D10/13
摘要： A method and system for configuring a cache memory system in order to efficiently process processor requests. A group of cache elements, which include a Region Cache, a Region Coherence Array, and a lowest level cache, is configured based on a tradeoff of latency and power consumption requirements. A selected cache configuration differs from other feasible configurations in the order in which cache elements are accessed relative to each other. The Region Cache is employed in a number of configurations to reduce the power consumption, latency, and bandwidth requirements of the Region Coherence Array. The Region Cache is accessed by processor requests before (or in parallel with) the larger Region Coherence Array, providing the region coherence state and power efficiently to requests that hit in the Region Cache.
摘要翻译：一种用于配置高速缓冲存储器系统以便有效地处理处理器请求的方法和系统。基于等待时间和功耗要求的折中来配置一组缓存元素，其中包括区域缓存，区域连贯性阵列和最低级缓存。所选择的高速缓存配置与其他可行配置的不同之处在于缓存元素相对于彼此被访问的顺序。区域缓存用于多种配置，以减少区域相干阵列的功耗，延迟和带宽要求。区域缓存在较大的区域相干阵列之前（或并行地）处理器请求访问，为区域缓存中的命中提供区域相干状态和功率。

28. 发明授权

US07389388B2 Data processing system and method for efficient communication utilizing an in coherency state 有权
标题翻译：用于在一致性状态下有效通信的数据处理系统和方法
公开(公告)号：US07389388B2
公开(公告)日：2008-06-17
申请号：US11055305
申请日：2005-02-10
申请人： Jason F. Cantin , James S. Fields, Jr. , Steven R. Kunkel , William J. Starke
发明人： Jason F. Cantin , James S. Fields, Jr. , Steven R. Kunkel , William J. Starke
IPC分类号： G06F13/00
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0813
摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory, and the second coherency domain includes a coherent second cache memory. The first cache memory within the first coherency domain of the data processing system holds a memory block in a storage location associated with an address tag and a coherency state field. The coherency state field is set to a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is likely cached only within the first coherency domain.
摘要翻译：高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元。第一相关域包括第一高速缓冲存储器，并且第二相干域包括相干第二高速缓冲存储器。数据处理系统的第一相干域内的第一高速缓冲存储器在与地址标签和一致性状态字段相关联的存储位置中保存存储器块。相关性状态字段被设置为指示地址标签有效的状态，存储位置不包含有效数据，并且该存储器块可能仅在第一相干域内被缓存。

29. 发明授权

US09201654B2 Processor and data processing method incorporating an instruction pipeline with conditional branch direction prediction for fast access to branch target instructions 有权
标题翻译：处理器和数据处理方法结合了具有条件分支方向预测的指令流水线，用于快速访问分支目标指令
公开(公告)号：US09201654B2
公开(公告)日：2015-12-01
申请号：US13171027
申请日：2011-06-28
申请人： Jason F. Cantin , Jack R. Smith , Arnold S. Tran , Kenichi Tsuchiya
发明人： Jason F. Cantin , Jack R. Smith , Arnold S. Tran , Kenichi Tsuchiya
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3848
摘要： Disclosed are a processor and a processing method incorporating an instruction pipeline with direction prediction (i.e., taken or not taken) for conditional branch instructions. In the embodiments, reading of a branch instruction history table (BHT) and a branch instruction target address cache (BTAC) for branch direction prediction occurs in parallel with the current instruction fetch in order to minimize delay in the next instruction fetch. Additionally, direction prediction is performed in the very next clock cycle based either on an initial direction prediction for the specific instruction, as stored in the BHT, or, if applicable, on a prior entry for the specific instruction in the BTAC. An override bit associated with each entry in the BTAC is the determining factor for whether or the BTAC or BHT is controlling. Override bits in the BTAC can be pre-established based on the branch instruction type in order to ensure prediction accuracy.
摘要翻译：公开了一种处理器和处理方法，其结合了用于条件分支指令的具有方向预测（即采取或未采用）的指令流水线。在实施例中，用于分支方向预测的分支指令历史表（BHT）和分支指令目标地址高速缓存（BTAC）的读取与当前指令获取并行发生，以便使下一指令提取中的延迟最小化。另外，方向预测是在下一个时钟周期内执行的，即基于存储在BHT中的特定指令的初始方向预测，或者如果适用，在BTAC中针对特定指令的先前条目。与BTAC中的每个条目相关联的覆盖位是否是BTAC或BHT正在控制的决定因素。可以基于分支指令类型预先建立BTAC中的覆盖位，以确保预测精度。

30. 发明授权

US08694732B2 Enhanced coherency tracking with implementation of region victim hash for region coherence arrays 有权
标题翻译：增强了一致性跟踪，实现区域相干阵列的区域受害者散列
公开(公告)号：US08694732B2
公开(公告)日：2014-04-08
申请号：US13398922
申请日：2012-02-17
申请人： Robert H. Bell , Jason F. Cantin
发明人： Robert H. Bell , Jason F. Cantin
IPC分类号： G06F12/00
CPC分类号： G06F12/082 , G06F12/12 , G06F2212/171
摘要： A method and system for precisely tracking lines evicted from a region coherence array (RCA) without requiring eviction of the lines from a processor's cache hierarchy. The RCA is a set-associative array which contains region entries consisting of a region address tag, a set of bits for the region coherence state, and a line-count for tracking the number of region lines cached by the processor. Tracking of the RCA is facilitated by a non-tagged hash table of counts represented by a Region Victim Hash (RVH). When a region is evicted from the RCA, and lines from the evicted region still reside in the processor's caches (i.e., the region's line-count is non-zero), the RCA line-count is added to the corresponding RVH count. The RVH count is decremented by the value of the region line count following a subsequent processor cache eviction/invalidation of the region previously evicted from the RCA.
摘要翻译：一种用于精确跟踪从区域相干阵列（RCA）中逐出的线而不需要从处理器的高速缓存层次结构中排除线路的方法和系统。 RCA是一个集合关联数组，其中包含由区域地址标签，区域相干状态的一组位组成的区域条目，以及用于跟踪由处理器缓存的区域行数的行计数。通过由区域受害者哈希（RVH）表示的计数的非标记哈希表来促进RCA的跟踪。当区域从RCA中逐出时，并且来自被驱逐区域的线路仍然驻留在处理器的高速缓存中（即，该区域的行计数不为零）时，将RCA线路计数添加到相应的RVH计数。 RVH计数在随后的处理器缓存驱逐/无效以前从RCA中逐出的区域之后减少区域行计数的值。

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