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21. 发明申请

US20090101941A1 WRAPPED GATE JUNCTION FIELD EFFECT TRANSISTOR 有权
标题翻译：封装栅极连接场效应晶体管
公开(公告)号：US20090101941A1
公开(公告)日：2009-04-23
申请号：US11875190
申请日：2007-10-19
申请人： John Ellis-Monaghan , Richard A. Phelps , Robert M. Rassel , Steven H. Voldman , Michael J. Zierak
发明人： John Ellis-Monaghan , Richard A. Phelps , Robert M. Rassel , Steven H. Voldman , Michael J. Zierak
IPC分类号： H01L29/808 , H01L21/337
CPC分类号： H01L29/808 , H01L29/1058 , H01L29/1066 , H01L29/1608 , H01L29/20 , H01L29/22 , H01L29/66901 , H01L29/66924
摘要： A wrapped gate junction field effect transistor (JFET) with at least one semiconductor channel having a first conductivity type doping is provided. Both sidewalls of each of the at least one semiconductor channel laterally abuts a side gate region having a second conductivity type doping, which is the opposite of the first conductivity doping. Further, the at least one semiconductor channel vertically abuts a top gate region and at least one bottom gate region, both having the second conductivity type doping. The gate electrode, which comprises side gate region, the top gate region, and at least one bottom gate regions, wraps around each of the at least one semiconductor channel to provide tight control of the current, i.e., a low off-current, through the at least one semiconductor channel. By employing multiple channels, the JFET may provide a high on-current.
摘要翻译：提供具有至少一个具有第一导电类型掺杂的半导体沟道的封装的栅极结场效应晶体管（JFET）。所述至少一个半导体通道中的每一个的两个侧壁横向邻接具有第二导电类型掺杂的侧栅极区域，其与第一导电掺杂相反。此外，至少一个半导体沟道垂直邻接顶部栅极区域和至少一个具有第二导电类型掺杂的底部栅极区域。包括侧栅极区域的栅极电极，顶栅极区域和至少一个底栅极区域围绕至少一个半导体通道中的每一个环绕，以提供电流的严格控制，即，低截止电流，通过所述至少一个半导体通道。通过采用多个通道，JFET可以提供高导通电流。

22. 发明申请

US20090019414A1 HIGH TOLERANCE TCR BALANCED HIGH CURRENT RESISTOR FOR RF CMOS AND RF SIGE BICMOS APPLICATIONS AND CADENCED BASED HIERARCHICAL PARAMETERIZED CELL DESIGN KIT WITH TUNABLE TCR AND ESD RESISTOR BALLASTING FEATURE 有权
标题翻译：用于RF CMOS和RF SIGE BICMOS应用的高耐压TCR平衡型高电流电阻器和基于CAD的分层式参考电池设计套件，具有TUNABLE TCR和ESD电阻贴片特性
公开(公告)号：US20090019414A1
公开(公告)日：2009-01-15
申请号：US12234473
申请日：2008-09-19
申请人： Ebenezer E. Eshun , Steven H. Voldman
发明人： Ebenezer E. Eshun , Steven H. Voldman
IPC分类号： G06F17/50
CPC分类号： H01C7/06 , H01L27/0288 , H01L27/0802 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A resistor device structure and method of manufacture therefore, wherein the resistor device structure invention includes a plurality of alternating conductive film and insulative film layers, at least two of the conductive film layers being electrically connected in parallel to provide for high current flow through the resistor device at high frequencies with increased temperature and mechanical stability. The alternating conductive film and insulative film layers may be of a planar or non-planar geometric spatial orientation. The alternating conductive film and insulative film layers may include lateral and vertical portions designed to enable a uniform current density flow within the structure itself through a self-ballasting effect within the physical resistor. A computer aided design tool with graphical and schematic features is provided to enable generation of hierarchical parameterized cells for a resistor element with the ability to provide customization, personalization and tunability of TCR, TCR matching, and high current and ESD robustness.
摘要翻译：因此，电阻器件结构及其制造方法，其中电阻器件结构发明包括多个交替导电膜和绝缘膜层，至少两个导电膜层并联电连接以提供通过电阻器的高电流器件在高频下具有升高的温度和机械稳定性。交替导电膜和绝缘膜层可以是平面或非平面的几何空间取向。交替导电膜和绝缘膜层可以包括横向和垂直部分，其被设计成能够通过物理电阻器内的自镇流效应在结构本身内实现均匀的电流密度流动。提供了具有图形和原理图功能的计算机辅助设计工具，以便能够为电阻元件生成分层参数化单元，具有提供TCR，TCR匹配以及高电流和ESD鲁棒性的定制，个性化和可调性的能力。

23. 发明授权

US07439145B2 Tunable semiconductor diodes 失效
标题翻译：可调谐半导体二极管
公开(公告)号：US07439145B2
公开(公告)日：2008-10-21
申请号：US11469582
申请日：2006-09-01
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： H01L21/8222
CPC分类号： H01L29/66136 , H01L27/0255 , H01L29/8611 , H01L29/8618 , H01L2924/0002 , H01L2924/00
摘要： A diode structure fabrication method. In a P− substrate, an N+ layer is implanted. The N+ layer has an opening whose size affects the breakdown voltage of the diode structure. Upon the N+ layer, an N− layer is formed. Then, a P+ region is formed to serve as an anode of the diode structure. An N+ region can be formed on the surface of the substrate to serve as a cathode of the diode structure. By changing the size of the opening in the N+ layer during fabrication, the breakdown voltage of the diode structure can be changed (tuned) to a desired value.
摘要翻译：二极管结构制造方法。在P-衬底中，植入N +层。 N +层的开口尺寸影响二极管结构的击穿电压。在N +层上形成N-层。然后，形成P +区域作为二极管结构的阳极。可以在衬底的表面上形成N +区以用作二极管结构的阴极。通过在制造期间改变N +层中的开口的尺寸，可以将二极管结构的击穿电压改变（调谐）至期望的值。

24. 发明申请

US20080251846A1 METHOD AND STRUCTURE FOR LOW CAPACITANCE ESD ROBUST DIODES 有权
标题翻译：低电容静电二极管的方法和结构
公开(公告)号：US20080251846A1
公开(公告)日：2008-10-16
申请号：US12118875
申请日：2008-05-12
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： H01L23/62
CPC分类号： H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： A diode having a capacitance below 0.1 pF and a breakdown voltage of at least 500V. The diode has an anode of a first conductivity type and a cathode of a second conductivity type disposed below the anode. At least one of the cathode and anode have multiple, vertically abutting diffusion regions. The cathode and anode are disposed between and bounded by adjacent isolation regions.
摘要翻译：具有低于0.1pF的电容和至少500V的击穿电压的二极管。二极管具有第一导电类型的阳极和布置在阳极下方的第二导电类型的阴极。阴极和阳极中的至少一个具有多个垂直邻接的扩散区域。阴极和阳极设置在相邻隔离区之间并由其限定。

25. 发明申请

US20080237789A1 INTEGRATED CIRCUIT STUCTURE INCORPORATING AN INDUCTOR, AN ASSOCIATED DESIGN METHOD AND AN ASSOCIATED DESIGN SYSTEM 失效
标题翻译：一体化电路结合电感器，相关设计方法和相关设计系统
公开(公告)号：US20080237789A1
公开(公告)日：2008-10-02
申请号：US11692948
申请日：2007-03-29
申请人： Zhong-Xiang He , Robert M. Rassel , Steven H. Voldman
发明人： Zhong-Xiang He , Robert M. Rassel , Steven H. Voldman
IPC分类号： H01L29/00 , G06F17/50
CPC分类号： G06F17/5063 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Disclosed are embodiments of a circuit (e.g., an electrostatic discharge (ESD) circuit), a design methodology and a design system. In the circuit, an ESD device is wired to a first metal level (e.g., M1). An inductor is formed in a second metal level (e.g., M5) above the first metal level and is aligned over and electrically connected in parallel to the ESD device by a single vertical via stack. The inductor is configured to nullify, for a given application frequency, the capacitance value of the ESD device. The quality factor of the inductor is optimized by providing, on a third metal level (e.g., M3) between the second metal level and the first metal level, a shield to minimize inductive coupling. An opening in the shield allows the via stack to pass through, trading off Q factor reduction for size-scaling and ESD robustness improvements.
摘要翻译：公开了电路（例如，静电放电（ESD）电路）的实施例，设计方法和设计系统。在电路中，ESD器件被连接到第一金属电平（例如，M 1）。电感器形成在第一金属级上方的第二金属级（例如，M 5）中，并且通过单个垂直通孔叠层对准并与ESD器件电连接。对于给定的应用频率，电感器被配置为使ESD器件的电容值无效。通过在第二金属层与第一金属层之间的第三金属层（例如M 3）上设置用于最小化电感耦合的屏蔽来优化电感器的品质因数。屏蔽开口允许通孔堆叠通过，减小尺寸缩放和ESD稳健性改进的Q因子。

26. 发明授权

US07384854B2 Method of forming low capacitance ESD robust diodes 有权
标题翻译：形成低电容ESD鲁棒二极管的方法
公开(公告)号：US07384854B2
公开(公告)日：2008-06-10
申请号：US09683985
申请日：2002-03-08
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： H01L21/20 , H01L29/00
CPC分类号： H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a diode having a capacitance below 0.1 pF and a breakdown voltage of at least 500V. The method including forming an anode of a first conductivity type and a cathode of a second conductivity type disposed below the anode. At least one of the cathode and anode have multiple, vertically abutting diffusion regions. Forming isolation regions such that the cathode and anode are disposed between and bounded by adjacent isolation regions.
摘要翻译：一种形成具有低于0.1pF的电容和至少500V的击穿电压的二极管的方法。该方法包括形成第一导电类型的阳极和布置在阳极下方的第二导电类型的阴极。阴极和阳极中的至少一个具有多个垂直邻接的扩散区域。形成隔离区域，使得阴极和阳极设置在相邻隔离区域之间并由其限定。

27. 发明申请

US20080087978A1 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20080087978A1
公开(公告)日：2008-04-17
申请号：US11548310
申请日：2006-10-11
申请人： Douglas D. Coolbaugh , Xuefeng Liu , Robert M. Rassel , David C. Sheridan , Steven H. Voldman
发明人： Douglas D. Coolbaugh , Xuefeng Liu , Robert M. Rassel , David C. Sheridan , Steven H. Voldman
IPC分类号： H01L29/93 , H01L21/20
CPC分类号： H01L29/0821 , H01L21/743 , H01L21/8249 , H01L27/0251 , H01L29/66242 , H01L29/737 , H01L29/78
摘要： A structure and method comprises a deep sub-collector located in a first epitaxial layer and a doped region located in a second epitaxial layer, which is above the first epitaxial layer. The device further comprises a reach-through structure penetrating from a surface of the device through the first and second epitaxial layers to the deep sub-collector, and a trench isolation structure penetrating from a surface of the device and surrounding the doped region.
摘要翻译：一种结构和方法包括位于第一外延层中的深子集电极和位于第一外延层之上的第二外延层中的掺杂区。该器件还包括从器件的表面穿过第一和第二外延层到达深子集电极的通孔结构，以及从器件的表面穿透且围绕掺杂区域的沟槽隔离结构。

28. 发明授权

US07348657B2 Electrostatic discharge protection networks for triple well semiconductor devices 有权
标题翻译：三阱半导体器件的静电放电保护网络
公开(公告)号：US07348657B2
公开(公告)日：2008-03-25
申请号：US11425491
申请日：2006-06-21
申请人： James P. Pequignot , Jeffrey H. Sloan , Douglas W. Stout , Steven H. Voldman
发明人： James P. Pequignot , Jeffrey H. Sloan , Douglas W. Stout , Steven H. Voldman
IPC分类号： H01L29/06
CPC分类号： H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection network that uses triple well semiconductor devices either singularly or in a series configuration. The semiconductor devices are preferably in diode junction type configuration.
摘要翻译：一种使用三重阱半导体器件的静电放电保护网络，其单体或串联配置。半导体器件优选为二极管结型。

29. 发明授权

US07348251B2 Modulated trigger device 失效
标题翻译：调制触发器
公开(公告)号：US07348251B2
公开(公告)日：2008-03-25
申请号：US11201023
申请日：2005-08-10
申请人： Steven H. Voldman , Michael J. Zierak
发明人： Steven H. Voldman , Michael J. Zierak
IPC分类号： H01L29/66
CPC分类号： H01L27/0277 , H01L29/1087 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure, a trigger device and a method of electrostatic discharge protection, the integrated circuit structure including: a substrate having a top surface defining a horizontal direction, the substrate of a first dopant type; a first horizontal layer in the substrate, the first layer of a second dopant type; and a second horizontal layer of the first dopant type, the second layer on top of the first layer and between the top surface of the substrate and the first layer, the second layer electrically modulated by the first layer.
摘要翻译：集成电路结构，触发装置和静电放电保护方法，所述集成电路结构包括：具有限定水平方向的顶表面的衬底，所述第一掺杂剂类型的衬底; 衬底中的第一水平层，第二掺杂剂型的第一层; 以及第一掺杂剂类型的第二水平层，第二层在第一层的顶部和衬底的顶表面与第一层之间，第二层由第一层电调制。

30. 发明申请

US20070287243A1 Semiconductor devices 失效
标题翻译：半导体器件
公开(公告)号：US20070287243A1
公开(公告)日：2007-12-13
申请号：US11422690
申请日：2006-06-07
申请人： Xuefeng Liu , Robert M. Rassel , Steven H. Voldman
发明人： Xuefeng Liu , Robert M. Rassel , Steven H. Voldman
IPC分类号： H01L21/8238
CPC分类号： H01L29/7436 , H01L27/0262 , H01L29/7378
摘要： A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The device further comprises a reach-through structure connecting the first and second sub-collectors and an N-well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure. The device further comprises N+ diffusion regions in contact with the N-well, a P+ diffusion region in contact with the N-well, and shallow trench isolation structures between the N+ and P+ diffusion regions.
摘要翻译：一种器件包括形成在衬底的上部中的第一子集电极和形成在第一外延层的上部中的第一外延层和第二子集电极的下部，以及第二外延层的下部。该装置还包括连接第一和第二子集电器的连通结构和形成在第二外延层的一部分中并与第二子集电器和达到通孔结构接触的N阱。该装置还包括与N阱接触的N +扩散区，与N阱接触的P +扩散区，以及N +和P +扩散区之间的浅沟槽隔离结构。

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