专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US08373486B2 Structure for a frequency adaptive level shifter circuit 有权
标题翻译：频率自适应电平转换电路的结构
公开(公告)号：US08373486B2
公开(公告)日：2013-02-12
申请号：US13431599
申请日：2012-03-27
申请人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
发明人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
IPC分类号： H03L5/00
CPC分类号： H03K4/94 , H03L9/00
摘要： The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.
摘要翻译：本发明提供了一种用于频率自适应电平移位器电路的装置和方法。频率自适应电平移位器电路包括第一反相器，耦合到第一反相器的输出的第二反相器，耦合到第二反相器的输出的电容器和耦合到电容器的输出的电阻器。频率自适应电平移位器电路还包括耦合到电阻器的输出的晶体管，其中晶体管具有连接到参考电压的栅极，耦合到电容器的输出的第三反相器和耦合到第三反相器和晶体管并输出信号。

22. 发明授权

US07538625B2 Method and enhanced phase locked loop circuits for implementing effective testing 失效
标题翻译：用于实现有效测试的方法和增强锁相环电路
公开(公告)号：US07538625B2
公开(公告)日：2009-05-26
申请号：US11679323
申请日：2007-02-27
申请人： Michael David Cesky , James David Strom
发明人： Michael David Cesky , James David Strom
IPC分类号： H03L7/00 , H03L7/06
CPC分类号： H03L7/1974 , G06F1/08
摘要： A method and enhanced phase-locked loop (PLL) circuit enable effective testing of the PLL. A phase frequency detector generates a differential signal, receiving a reference signal and a feedback signal of an output signal of the PLL circuit. A charge pump is coupled to the phase frequency detector receiving the differential signal. The charge pump applies either negative or positive charge pulses to a low-pass filter, which generates a tuning voltage input applied to a voltage controlled oscillator. A first divider is coupled to the voltage controlled oscillator receives and divides down the VCO output signal, providing the output signal of the PLL circuit. A second divider receives the output signal of the PLL circuit and provides the feedback signal to the phase frequency detector. The output signal of PLL circuit is applied to a clock distribution.
摘要翻译：一种方法和增强型锁相环（PLL）电路能够有效地测试PLL。相位频率检测器产生差分信号，接收PLL电路的输出信号的参考信号和反馈信号。电荷泵耦合到接收差分信号的相位频率检测器。电荷泵将负电荷或正电荷脉冲施加到低通滤波器，产生施加到压控振荡器的调谐电压输入。第一分频器耦合到压控振荡器接收并分频VCO输出信号，提供PLL电路的输出信号。第二分频器接收PLL电路的输出信号，并将反馈信号提供给相位频率检测器。 PLL电路的输出信号应用于时钟分配。

23. 发明申请

US20080301503A1 HIGH FREQUENCY DIVIDER STATE CORRECTION CIRCUIT 失效
标题翻译：高频分路器状态校正电路
公开(公告)号：US20080301503A1
公开(公告)日：2008-12-04
申请号：US12187517
申请日：2008-08-07
申请人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
发明人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
IPC分类号： G06F11/28
CPC分类号： H03K21/406 , G06F7/58
摘要： The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.
摘要翻译：本发明提供一种自校正状态电路。第一触发器被配置为接收时钟输入和第一数据输入，并且响应于时钟输入和第一数据输入而产生第一输出。第二触发器耦合到第一触发器并且被配置为接收时钟输入并且接收第一输出作为第二数据输入，并且响应于时钟输入和第一输出而产生第二输出。第一校正电路耦合到第二触发器并且被配置为产生校正输出。第三触发器耦合到第一校正电路并且被配置为接收时钟输入并且接收校正的输出作为第三数据输入，并且响应于时钟输入和第三数据输入而产生第三输出。

24. 发明申请

US20080204154A1 Method and Enhanced Phase Locked Loop Circuits for Implementing Effective Testing 失效
标题翻译：用于实现有效测试的方法和增强型锁相环电路
公开(公告)号：US20080204154A1
公开(公告)日：2008-08-28
申请号：US11679323
申请日：2007-02-27
申请人： Michael David Cesky , James David Strom
发明人： Michael David Cesky , James David Strom
IPC分类号： H03J7/04
CPC分类号： H03L7/1974 , G06F1/08
摘要： A method and enhanced phase-locked loop (PLL) circuit enable effective testing of the PLL. A phase frequency detector generates a differential signal, receiving a reference signal and a feedback signal of an output signal of the PLL circuit. A charge pump is coupled to the phase frequency detector receiving the differential signal. The charge pump applies either negative or positive charge pulses to a low-pass filter, which generates a tuning voltage input applied to a voltage controlled oscillator. A first divider is coupled to the voltage controlled oscillator receives and divides down the VCO output signal, providing the output signal of the PLL circuit. A second divider receives the output signal of the PLL circuit and provides the feedback signal to the phase frequency detector. The output signal of PLL circuit is applied to a clock distribution.
摘要翻译：一种方法和增强型锁相环（PLL）电路能够有效地测试PLL。相位频率检测器产生差分信号，接收PLL电路的输出信号的参考信号和反馈信号。电荷泵耦合到接收差分信号的相位频率检测器。电荷泵将负电荷或正电荷脉冲施加到低通滤波器，产生施加到压控振荡器的调谐电压输入。第一分频器耦合到压控振荡器接收并分频VCO输出信号，提供PLL电路的输出信号。第二分频器接收PLL电路的输出信号，并将反馈信号提供给相位频率检测器。 PLL电路的输出信号应用于时钟分配。

25. 发明申请

US20080116947A1 Method and Apparatus for Distributing Charge Pump Current and Voltage for PLL Circuits 审中-公开
标题翻译：用于分配PLL电路的电荷泵电流和电压的方法和装置
公开(公告)号：US20080116947A1
公开(公告)日：2008-05-22
申请号：US11561431
申请日：2006-11-20
申请人： Katherine Ellen Lobb , James David Strom
发明人： Katherine Ellen Lobb , James David Strom
IPC分类号： H03L7/08
CPC分类号： H03L7/0891 , H03L7/18
摘要： A method and apparatus for distributing charge pump current and voltage for phase-locked loop circuits includes a charge pump implemented with a plurality of charge pump stages, each providing substantially equal charge pump current. Each stage includes a respective associated buffer for receiving an incoming increment (INC) signal and an incoming decrement (DEC) signal and providing an output time delayed INC signal and an output time delayed DEC. A chain of the buffers is provided to pass the time delayed INC signals and the time delayed DEC signals to the respective charge pump stages. Each of the charge pump stages includes an enable input arranged for independently enabling each respective charge pump stage.
摘要翻译：用于分配用于锁相环电路的电荷泵电流和电压的方法和装置包括用多个电荷泵级实现的电荷泵，每个电荷泵提供基本相等的电荷泵电流。每个级包括用于接收输入增量（INC）信号和进入递减（DEC）信号并提供输出时间延迟INC信号和输出时间延迟DEC的各自相关联的缓冲器。提供缓冲器链以将时间延迟的INC信号和时间延迟的DEC信号传递到各个电荷泵级。每个电荷泵级包括使能输入，其被布置用于独立地使能各个电荷泵级。

26. 发明授权

US07061284B2 High frequency divider state correction circuit with data path correction 失效
标题翻译：具有数据路径校正的高分频器状态校正电路
公开(公告)号：US07061284B2
公开(公告)日：2006-06-13
申请号：US10850402
申请日：2004-05-20
申请人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
发明人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
IPC分类号： H03K21/00 , H03K23/00 , H03K25/08
CPC分类号： H03K21/406 , G06F7/58
摘要： The present invention provides for state correction. A first flip flop coupled to a second flip flop. A state correction circuit coupled to the output of the second flip flop. A third flip flop is coupled to the output of the state correction circuit. A fourth flip flop is coupled to the output of the third flip flop.
摘要翻译：本发明提供了状态校正。耦合到第二触发器的第一触发器。耦合到第二触发器的输出的状态校正电路。第三触发器耦合到状态校正电路的输出端。第四触发器耦合到第三触发器的输出。

27. 发明授权

US08686782B2 Structure for a frequency adaptive level shifter circuit 有权
标题翻译：频率自适应电平转换电路的结构
公开(公告)号：US08686782B2
公开(公告)日：2014-04-01
申请号：US12956343
申请日：2010-11-30
申请人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
发明人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
IPC分类号： H03L5/00
CPC分类号： H03K4/94 , H03L9/00
摘要： The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.
摘要翻译：本发明提供了一种用于频率自适应电平移位器电路的装置和方法。频率自适应电平移位器电路包括第一反相器，耦合到第一反相器的输出的第二反相器，耦合到第二反相器的输出的电容器和耦合到电容器的输出的电阻器。频率自适应电平移位器电路还包括耦合到电阻器的输出的晶体管，其中晶体管具有连接到参考电压的栅极，耦合到电容器的输出的第三反相器和耦合到第三反相器和晶体管并输出信号。

28. 发明申请

US20120187987A1 STRUCTURE FOR A FREQUENCY ADAPTIVE LEVEL SHIFTER CIRCUIT 有权
标题翻译：频率自适应电平变换电路的结构
公开(公告)号：US20120187987A1
公开(公告)日：2012-07-26
申请号：US13431599
申请日：2012-03-27
申请人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
发明人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
IPC分类号： H03L7/08 , H03L5/00
CPC分类号： H03K4/94 , H03L9/00
摘要： The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.
摘要翻译：本发明提供了一种用于频率自适应电平移位器电路的装置和方法。频率自适应电平移位器电路包括第一反相器，耦合到第一反相器的输出的第二反相器，耦合到第二反相器的输出的电容器和耦合到电容器的输出的电阻器。频率自适应电平移位器电路还包括耦合到电阻器的输出的晶体管，其中晶体管具有连接到参考电压的栅极，耦合到电容器的输出的第三反相器和耦合到第三反相器和晶体管并输出信号。

29. 发明申请

US20120133413A1 DESIGN STRUCTURE FOR A FREQUENCY ADAPTIVE LEVEL SHIFTER CIRCUIT 有权
标题翻译：一种频率自适应电平变换电路的设计结构
公开(公告)号：US20120133413A1
公开(公告)日：2012-05-31
申请号：US12956343
申请日：2010-11-30
申请人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
发明人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
IPC分类号： H03L5/00
CPC分类号： H03K4/94 , H03L9/00
摘要： The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.
摘要翻译：本发明提供了一种用于频率自适应电平移位器电路的装置和方法。频率自适应电平移位器电路包括第一反相器，耦合到第一反相器的输出的第二反相器，耦合到第二反相器的输出的电容器和耦合到电容器的输出的电阻器。频率自适应电平移位器电路还包括耦合到电阻器的输出的晶体管，其中晶体管具有连接到参考电压的栅极，耦合到电容器的输出的第三反相器和耦合到第三反相器和晶体管并输出信号。

30. 发明申请

US20080116959A1 Method and Apparatus for Distributing Charge Pump Current and Voltage for PLL Circuits 审中-公开
标题翻译：用于分配PLL电路的电荷泵电流和电压的方法和装置
公开(公告)号：US20080116959A1
公开(公告)日：2008-05-22
申请号：US11872356
申请日：2007-10-15
申请人： Katherine Ellen Hirsch , James David Strom
发明人： Katherine Ellen Hirsch , James David Strom
IPC分类号： G05F1/10
CPC分类号： H03L7/0891 , H03L7/18
摘要： A method and apparatus for distributing charge pump current and voltage for phase-locked loop circuits, and a design structure on which the subject circuit resides are provided. A charge pump implemented with a plurality of charge pump stages, each providing substantially equal charge pump current. Each stage includes a respective associated buffer for receiving an incoming increment (INC) signal and an incoming decrement (DEC) signal and providing an output time delayed INC signal and an output time delayed DEC. A chain of the buffers is provided to pass the time delayed INC signals and the time delayed DEC signals to the respective charge pump stages. Each of the charge pump stages includes an enable input arranged for independently enabling each respective charge pump stage.
摘要翻译：一种用于分配锁相环电路的电荷泵电流和电压的方法和装置，以及设置有被摄体电路的设计结构。一种电荷泵，其具有多个电荷泵级，各自提供基本上相等的电荷泵电流。每个级包括用于接收输入增量（INC）信号和进入递减（DEC）信号并提供输出时间延迟INC信号和输出时间延迟DEC的各自相关联的缓冲器。提供缓冲器链以将时间延迟的INC信号和时间延迟的DEC信号传递到各个电荷泵级。每个电荷泵级包括使能输入，其被布置用于独立地使能各个电荷泵级。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式