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21. 发明申请

US20050145894A1 Replacement gate flow facilitating high yield and incorporation of etch stop layers and/or stressed films 有权
标题翻译：替代栅极流动有利于高产率并且结合蚀刻停止层和/或应力膜
公开(公告)号：US20050145894A1
公开(公告)日：2005-07-07
申请号：US10749196
申请日：2003-12-30
申请人： Robert Chau , Justin Brask , Chris Barns , Scott Hareland
发明人： Robert Chau , Justin Brask , Chris Barns , Scott Hareland
IPC分类号： H01L21/336 , H01L21/338 , H01L21/8234 , H01L29/94 , H01L31/119
CPC分类号： H01L29/66545 , H01L29/7842
摘要： The present invention relates to the deposition of a layer above a transistor structure, causing crystalline stress within the transistor, and resulting in increased performance. The stress layer may be formed above a plurality of transistors formed on a substrate, or above a plurality of selected transistors.
摘要翻译：本发明涉及在晶体管结构之上沉积一层，引起晶体管内的晶体应力，并导致性能的提高。应力层可以形成在形成在衬底上或多个选定晶体管上方的多个晶体管的上方。

22. 发明申请

US20050026408A1 Preventing silicide formation at the gate electrode in a replacement metal gate technology 失效
标题翻译：在替代金属栅极技术中防止栅电极处的硅化物形成
公开(公告)号：US20050026408A1
公开(公告)日：2005-02-03
申请号：US10629127
申请日：2003-07-29
申请人： Chris Barns , Justin Brask , Mark Doczy
发明人： Chris Barns , Justin Brask , Mark Doczy
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/66545
摘要： A hard mask may be formed and maintained over a polysilicon gate structure in a metal gate replacement technology. The maintenance of the hard mask, such as a nitride hard mask, may protect the polysilicon gate structure 14 from the formation of silicide or etch byproducts. Either the silicide or the etch byproducts or their combination may block the ensuing polysilicon etch which is needed to remove the polysilicon gate structure and to thereafter replace it with an appropriate metal gate technology.
摘要翻译：在金属栅极替换技术中，可以在多晶硅栅极结构上形成并保持硬掩模。硬掩模（例如氮化物硬掩模）的维护可以保护多晶硅栅极结构14免受硅化物或蚀刻副产物的形成。硅化物或蚀刻副产物或它们的组合可以阻止除去多晶硅栅极结构所需的随后的多晶硅蚀刻，然后用适当的金属栅极技术代替它。

23. 发明申请

US20070077765A1 Etch stop and hard mask film property matching to enable improved replacement metal gate process 有权
标题翻译：蚀刻停止和硬掩模膜性能匹配，以改进替换金属浇口工艺
公开(公告)号：US20070077765A1
公开(公告)日：2007-04-05
申请号：US11240839
申请日：2005-09-30
申请人： Matthew Prince , Chris Barns , Justin Brask
发明人： Matthew Prince , Chris Barns , Justin Brask
IPC分类号： H01L21/311
CPC分类号： H01L21/31111 , H01L29/66545 , Y10S438/926
摘要： A method including forming a hard mask and an etch stop layer over a sacrificial material patterned as a gate electrode, wherein a material for the hard mask and a material for the etch stop layer are selected to have a similar stress property; removing the material for the hard mask and the material for the etch stop layer sufficient to expose the sacrificial material; replacing the sacrificial material with another material. A system including a computing device including a microprocessor, the microprocessor including a plurality of transistor devices, at least one of the plurality of transistor devices including a gate electrode formed on a substrate surface; a discontinuous etch stop layer conformally formed on the substrate surface and adjacent side wall surfaces of the gate electrode; and a dielectric material conformally formed over the etch stop layer.
摘要翻译：一种方法，包括在图案化为栅电极的牺牲材料上形成硬掩模和蚀刻停止层，其中用于硬掩模的材料和用于蚀刻停止层的材料被选择为具有类似的应力特性; 去除用于硬掩模的材料和足以暴露牺牲材料的用于蚀刻停止层的材料; 用另一种材料代替牺牲材料。一种包括包括微处理器的计算设备的系统，所述微处理器包括多个晶体管器件，所述多个晶体管器件中的至少一个晶体管器件包括形成在衬底表面上的栅电极; 保形地形成在栅电极的基板表面和相邻的侧壁表面上的不连续的蚀刻停止层; 以及保形地形成在蚀刻停止层上的电介质材料。

24. 发明申请

US20050211982A1 Strained silicon with reduced roughness 审中-公开
标题翻译：应变硅，粗糙度降低
公开(公告)号：US20050211982A1
公开(公告)日：2005-09-29
申请号：US10808021
申请日：2004-03-23
申请人： Ryan Lei , Mohamad Shaheen , Chris Barns , Been-Yih Jin , Justin Brask
发明人： Ryan Lei , Mohamad Shaheen , Chris Barns , Been-Yih Jin , Justin Brask
IPC分类号： H01L21/20 , H01L21/205 , H01L21/336 , H01L29/04 , H01L29/10 , H01L29/12 , H01L29/78 , H01L31/036
CPC分类号： H01L31/03921 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/0262 , H01L21/02658 , H01L29/1054 , H01L29/78 , Y02E10/50
摘要： The invention provides a strained silicon layer with a reduced roughness. Reduced cross-hatching in the strained silicon layer may allow the reduced roughness.
摘要翻译：本发明提供了具有减小的粗糙度的应变硅层。在应变硅层中减少交叉阴影可以减少粗糙度。

25. 发明授权

US07126199B2 Multilayer metal gate electrode 有权
标题翻译：多层金属栅电极
公开(公告)号：US07126199B2
公开(公告)日：2006-10-24
申请号：US10951073
申请日：2004-09-27
申请人： Mark L. Doczy , Justin K. Brask , Jack Kavalieros , Chris Barns , Matthew V. Metz , Suman Datta , Robert S. Chau
发明人： Mark L. Doczy , Justin K. Brask , Jack Kavalieros , Chris Barns , Matthew V. Metz , Suman Datta , Robert S. Chau
IPC分类号： H01L29/94
CPC分类号： H01L21/823437 , H01L21/823828
摘要： A complementary metal oxide semiconductor integrated circuit may be formed with NMOS and PMOS transistors that have high dielectric constant gate dielectric material over a semiconductor substrate. A metal barrier layer may be formed over the gate dielectric. A workfunction setting metal layer is formed over the metal barrier layer and a cap metal layer is formed over the workfunction setting metal layer.
摘要翻译：互补金属氧化物半导体集成电路可以形成有在半导体衬底上具有高介电常数栅极电介质材料的NMOS和PMOS晶体管。可以在栅极电介质上方形成金属阻挡层。在金属阻挡层上方形成功函设定金属层，在功函设定金属层上形成帽金属层。

26. 发明申请

US20060065633A1 Semiconductor substrate polishing methods and equipment 有权
公开(公告)号：US20060065633A1
公开(公告)日：2006-03-30
申请号：US10952655
申请日：2004-09-28
申请人： Paul Fischer , Chris Barns
发明人： Paul Fischer , Chris Barns
IPC分类号： C03C15/00 , H01L21/306 , C23F1/00 , B44C1/22
CPC分类号： H01L21/7684 , B24B37/042 , B24B37/046 , C25F3/02 , H01L21/32115 , H01L21/32125
摘要： According to one aspect of the present invention, a method of electrochemically polishing a semiconductor substrate may be provided. A semiconductor substrate processing fluid, having a plurality of abrasive particles therein, may be placed between the surface of the semiconductor substrate and the polish head. The polish head may be moved relative to the surface of the semiconductor substrate to cause the abrasive particles to polish the surface of the semiconductor substrate. According to a second aspect of the present invention, a method for electro-polishing a semiconductor substrate may be provided. A semiconductor substrate may be placed in an electrolytic solution. A surface of the semiconductor substrate may be contacted with at least one conductive member. A voltage may be applied across the electrolytic solution and the at least one conductive member. The at least one conductive member may be moved across the surface of the semiconductor substrate.

27. 发明申请

US20060272773A1 Semiconductor substrate polishing methods and equipment 审中-公开
标题翻译：半导体衬底抛光方法和设备
公开(公告)号：US20060272773A1
公开(公告)日：2006-12-07
申请号：US11506316
申请日：2006-08-17
申请人： Paul Fischer , Chris Barns
发明人： Paul Fischer , Chris Barns
IPC分类号： H01L21/306
CPC分类号： H01L21/7684 , B24B37/042 , B24B37/046 , C25F3/02 , H01L21/32115 , H01L21/32125
摘要： According to one aspect of the present invention, a method of electrochemically polishing a semiconductor substrate may be provided. A semiconductor substrate processing fluid, having a plurality of abrasive particles therein, may be placed between the surface of the semiconductor substrate and the polish head. The polish head may be moved relative to the surface of the semiconductor substrate to cause the abrasive particles to polish the surface of the semiconductor substrate. According to a second aspect of the present invention, a method for electro-polishing a semiconductor substrate may be provided. A semiconductor substrate may be placed in an electrolytic solution. A surface of the semiconductor substrate may be contacted with at least one conductive member. A voltage may be applied across the electrolytic solution and the at least one conductive member. The at least one conductive member may be moved across the surface of the semiconductor substrate.
摘要翻译：根据本发明的一个方面，可以提供一种电化学抛光半导体衬底的方法。可以在半导体衬底的表面和抛光头之间放置其中具有多个磨料颗粒的半导体衬底处理流体。抛光头可以相对于半导体衬底的表面移动，以使研磨颗粒抛光半导体衬底的表面。根据本发明的第二方面，可以提供一种用于电抛光半导体衬底的方法。可以将半导体衬底放置在电解液中。半导体衬底的表面可以与至少一个导电构件接触。可以在电解液和至少一个导电构件之间施加电压。至少一个导电构件可以跨过半导体衬底的表面移动。

28. 发明申请

US20060003600A1 Contact planarization for integrated circuit processing 审中-公开
标题翻译：接触平面化用于集成电路处理
公开(公告)号：US20060003600A1
公开(公告)日：2006-01-05
申请号：US10882897
申请日：2004-06-30
申请人： Chris Barns
发明人： Chris Barns
IPC分类号： H01L21/31 , H01L21/4763
CPC分类号： H01L21/31051 , H01L21/76819 , H01L21/7684
摘要： A method to form substantially planarized layers on a substrate. In an implementation, the method includes depositing a fluid material having at least one gap control bead onto a surface of the substrate, pressing a contact planarizer into the fluid material with a force sufficient to planarize at least a portion of a top surface of the fluid material, wherein the at least one gap control bead maintains a minimum thickness of the fluid material, curing the fluid material to form a substantially solid material, and separating the contact planarizer from the substantially solid material.
摘要翻译：在衬底上形成基本平坦化层的方法。在一个实施方案中，该方法包括将具有至少一个间隙控制珠的流体材料沉积到基底的表面上，以足以平坦化流体顶表面的至少一部分的力将接触平面化器压入流体材料中材料，其中所述至少一个间隙控制珠维持所述流体材料的最小厚度，固化所述流体材料以形成基本上固体的材料，以及将所述接触平面化器与所述基本上固体的材料分离。

29. 发明授权

US07294931B2 Method and apparatus for selective deposition 有权
标题翻译：用于选择性沉积的方法和装置
公开(公告)号：US07294931B2
公开(公告)日：2007-11-13
申请号：US11011324
申请日：2004-12-13
申请人： Chris Barns
发明人： Chris Barns
IPC分类号： H01L23/48
CPC分类号： H01L21/76879
摘要： A method for selectively depositing a source material on a wafer is disclosed. In one embodiment, a wafer is having at least one recessed feature is provided. A top surface of the wafer is then coated with an inhibiting material. Finally, a source material is selectively deposited in the at least one recessed feature, the source material repelled by the inhibiting material. In another embodiment, the inhibiting material is one of a wax, a surfactant or an oil.
摘要翻译：公开了一种用于在晶片上选择性地沉积源材料的方法。在一个实施例中，晶片具有至少一个凹陷特征。然后用抑制材料涂覆晶片的顶表面。最后，源材料被选择性地沉积在至少一个凹陷特征中，源材料被抑制材料排斥。在另一个实施方案中，抑制材料是蜡，表面活性剂或油之一。

30. 发明授权

US07238610B2 Method and apparatus for selective deposition 有权
公开(公告)号：US07238610B2
公开(公告)日：2007-07-03
申请号：US10404775
申请日：2003-03-31
申请人： Chris Barns
发明人： Chris Barns
IPC分类号： H01L21/4763
CPC分类号： H01L21/76879
摘要： A method for selectively depositing a source material on a wafer is disclosed. In one embodiment, a wafer is having at least one recessed feature is provided. A top surface of the wafer is then coated with an inhibiting material. Finally, a source material is selectively deposited in the at least one recessed feature, the source material repelled by the inhibiting material. In another embodiment, the inhibiting material is one of a wax, a surfactant or an oil.

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