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21. 发明授权

US09575836B2 Temporary pipeline marking for processor error workarounds 有权
标题翻译：处理器错误解决方法的临时管道标记
公开(公告)号：US09575836B2
公开(公告)日：2017-02-21
申请号：US15251316
申请日：2016-08-30
申请人： International Business Machines Corporation
发明人： Erez Barak , Steven R. Carlough , Eyal Gonen , Juergen Haess , Silvia M. Mueller
IPC分类号： G06F11/00 , G06F11/14 , G06F9/38
CPC分类号： G06F11/142 , G06F9/3867 , G06F11/0721 , G06F11/0751 , G06F11/079 , G06F11/0793 , G06F11/2028 , G06F11/3024 , G06F11/3466 , G06F2201/805 , G06F2201/82 , G06F2201/85 , G06F2201/86
摘要： Embodiments include a computer system for temporary pipeline marking for processor error workarounds, the computer system having a processor configured to perform a method. The method includes monitoring a pipeline of the processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.
摘要翻译：实施例包括用于处理器错误解决方案的临时管道标记的计算机系统，该计算机系统具有被配置为执行方法的处理器。该方法包括监视处理器的流水线，用于预定的事件，以使处理器处于由于卡住状态或重复的资源争用导致性能下降而导致错误指令执行结果的卡住状态。管道被标记为基于检测事件的解决方法操作。基于管道的标记触发清除动作。基于触发清除动作，管道的标记被清除。

22. 发明授权

US09529664B2 Using error correcting codes for parity purposes 有权
公开(公告)号：US09529664B2
公开(公告)日：2016-12-27
申请号：US14576403
申请日：2014-12-19
申请人： International Business Machines Corporation
发明人： Son T. Dao , Juergen Haess , Michael Klein , Silvia M. Mueller
IPC分类号： G06F11/10 , G06F3/06 , H03M13/13 , H03M13/35 , G06F11/07 , H04L1/00 , G11B20/18 , H03M13/09 , G11C29/42 , H04L12/939 , H03M13/19 , H03M13/11 , H03M13/15
CPC分类号： G06F11/10 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/0751 , G06F11/1012 , G06F11/1032 , G06F11/1044 , G06F11/1048 , G06F11/1076 , G11B20/1803 , G11C29/42 , H03M13/09 , H03M13/098 , H03M13/1102 , H03M13/13 , H03M13/1515 , H03M13/152 , H03M13/1575 , H03M13/19 , H03M13/35 , H04L1/0057 , H04L49/557
摘要： Software that combines parity bits with error correcting codes (ECC) such that a subset of ECC bits is also used for parity purposes, by performing the following steps: (i) providing a first set of redundant bit(s) in a data block, where the first set of redundant bit(s) is adapted to detect and/or correct errors in the data block; (ii) providing, within the first set of redundant bit(s), a first sub-set of parity bit(s), where the first sub-set of parity bit(s) is adapted to provide single bit error detection for the data block; and (iii) determining, based, at least in part, on a first set of data read requirements, whether to use the first set of redundant bit(s) and/or the first sub-set of parity bit(s) to detect and/or correct potential errors while reading data on the data block.

23. 发明授权

US09507659B2 Temporary pipeline marking for processor error workarounds 有权
标题翻译：处理器错误解决方法的临时管道标记
公开(公告)号：US09507659B2
公开(公告)日：2016-11-29
申请号：US15074219
申请日：2016-03-18
申请人： International Business Machines Corporation
发明人： Erez Barak , Steven R. Carlough , Eyal Gonen , Juergen Haess , Silvia M. Mueller
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/142 , G06F9/3867 , G06F11/0721 , G06F11/0751 , G06F11/079 , G06F11/0793 , G06F11/2028 , G06F11/3024 , G06F11/3466 , G06F2201/805 , G06F2201/82 , G06F2201/85 , G06F2201/86
摘要： Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring a pipeline of a processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.
摘要翻译：实施例包括用于处理器错误解决方案的临时管道标记的方法。该方法包括监视处理器的流水线，用于预定的事件，以使处理器处于由于卡住状态引起的错误指令执行结果或导致性能下降的重复的资源争用的停滞状态。管道被标记为基于检测事件的解决方法操作。基于管道的标记触发清除动作。基于清除动作的触发，管道的标记被清除。

24. 发明申请

US20160170829A1 NON-LOCAL ERROR DETECTION IN PROCESSOR SYSTEMS 有权
标题翻译：处理器系统中的非本地错误检测
公开(公告)号：US20160170829A1
公开(公告)日：2016-06-16
申请号：US14953459
申请日：2015-11-30
申请人： International Business Machines Corporation
发明人： Steven R. Carlough , James R. Cuffney , Michael Klein , Silvia M. Mueller
IPC分类号： G06F11/10 , G06F11/34 , G06F11/30
CPC分类号： G06F11/1004 , G06F9/3867 , G06F11/1008 , G06F11/3024 , G06F11/3409
摘要： A method for delocalizing an error checking on a data in a pipelined processor from the data checked. A first check-data is generated at a first location on a first data. A second location receives the first data and the first check-data. A second check-data is generated on the first data and the first check-data is compared with the second check-data at the second location. A second data is generated from the first data and a third check-data is generated on the second data at the second location. A third check-data is generated on the second data at the second location and the second data is transferred to a third location. The third check-data is transferred to a fourth location. A fourth check-data is generated on the second data and is transferred to the fourth location. The fourth check-data and the third check-data are compared at the fourth location.
摘要翻译：一种从流水线处理器中的数据的错误检查中离域的方法。在第一数据的第一位置生成第一检查数据。第二位置接收第一数据和第一检查数据。在第一数据上产生第二检查数据，并且将第一检查数据与第二位置处的第二检查数据进行比较。从第一数据产生第二数据，并且在第二位置处对第二数据生成第三检查数据。在第二位置处的第二数据上生成第三检查数据，并且将第二数据传送到第三位置。第三个检查数据被传送到第四个位置。在第二数据上产生第四检查数据，并将其传送到第四位置。第四个检查数据和第三个检查数据在第四个位置进行比较。

25. 发明申请

US20160085509A1 OPTIMIZED STRUCTURE FOR HEXADECIMAL AND BINARY MULTIPLIER ARRAY 有权
标题翻译：十进制和二进制多播阵列的优化结构
公开(公告)号：US20160085509A1
公开(公告)日：2016-03-24
申请号：US14578879
申请日：2014-12-22
申请人： International Business Machines Corporation
发明人： Silvia M. Mueller , Son Dao Trong
IPC分类号： G06F7/487
CPC分类号： G06F7/4876
摘要： A method for hiding implicit bit corrections in a partial product adder array in a binary and hexadecimal floating-point multiplier such that no additional adder stages are needed for the implicit bit corrections. Two leading-one correction terms are generated for the fraction in the multiplier floating-point number and two leading-one correction terms are generated for the fraction in the multiplicand floating-point number. The floating-point numbers may be single-precision or double-precision. Each leading-one correction term for the single-precision case is appended to the left of an intermediate partial product sum in the adder array that is an input to an adder so as to not to extend the bits in the input further to the left than the bits in another input to the adder. Each leading-one correction term for the double-precision case replaces an adder input that is unused when base-2 floating-point numbers are multiplied.
摘要翻译：一种用于在二进制和十六进制浮点乘法器中的部分积加法器阵列中隐藏隐式位校正的方法，使得隐式位校正不需要附加的加法器级。为乘数浮点数中的分数生成两个前导修正项，并为乘数浮点数中的分数生成两个前导一个校正项。浮点数可以是单精度或双精度。在加法器阵列中，单精度情况下的前导一校正项追加到加法器阵列的中间部分乘积和的左侧，该加法器阵列是加法器的输入，以便不将输入中的位进一步向左延伸加法器的另一个输入中的位。双精度情况下的每个前导一个校正项将替换当基本2浮点数相乘时未使用的加法器输入。

26. 发明授权

US09128759B2 Decimal multi-precision overflow and tininess detection 有权
标题翻译：十进制多精度溢出和检测
公开(公告)号：US09128759B2
公开(公告)日：2015-09-08
申请号：US13686135
申请日：2012-11-27
申请人： International Business Machines Corporation
发明人： Steven R. Carlough , Adam B. Collura , Michael K. Kroener , Silvia M. Mueller
IPC分类号： G06F7/494 , G06F7/491
CPC分类号： G06F7/4912 , G06F2207/4922
摘要： An approach is provided in which a processor includes an adder that concurrently generates one or more intermediate results and a boundary indicator based upon instructions retrieved from a memory area. The boundary indicator indicates whether a collective result generated from the intermediate results is within a boundary precision value.
摘要翻译：提供了一种方法，其中处理器包括基于从存储器区域检索的指令同时产生一个或多个中间结果的加法器和边界指示符。边界指示符指示从中间结果生成的集体结果是否在边界精度值内。

27. 发明授权

US10592208B2 Very low precision floating point representation for deep learning acceleration 有权
公开(公告)号：US10592208B2
公开(公告)日：2020-03-17
申请号：US15973511
申请日：2018-05-07
申请人： International Business Machines Corporation
发明人： Naigang Wang , Kailash Gopalakrishnan , Jungwook Choi , Silvia M. Mueller , Ankur Agrawal , Daniel Brand
IPC分类号： G06F7/483 , G06N3/08 , G06F7/499
摘要： A specialized circuit is configured for floating point computations using numbers represented by a very low precision format (VLP format). The VLP format includes less than sixteen bits and is apportion into a sign bit, exponent bits (e), and mantissa bits (p). The configured specialized circuit is operated to store an approximation of a numeric value in the VLP format, where the approximation is represented as a function of a multiple of a fraction, where the fraction is an inverse of a number of discrete values that can be represented using only the mantissa bits.

28. 发明授权

US10579375B2 Method to build reconfigurable variable length comparators 有权
公开(公告)号：US10579375B2
公开(公告)日：2020-03-03
申请号：US15889315
申请日：2018-02-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Cedric Lichtenau , Silvia M. Mueller , Jens P. Seifert , Jörg-Stephan Vogt , Markus Lachenmayr , L'Emir Salim Chehab , Pavankrishna Ellore Ramesh , Sourabh Chougule
IPC分类号： G06F9/30 , G06F16/22
摘要： The present disclosure relates performing of comparisons between a first and a second vector. The memory location has a size or length of m bits. A compare block to compare two single bits is used. The compare block comprises: two input bits associated to one of the bits from the first and the second vector respectively; a greater than input bit and a lower than input bit; a cascade enable input bit to control if the greater than input bit and the lower than input bit are considered; a greater than result bit, a lower than result bit, and an equal result bit. A daisy chaining of m of the one-bit compare blocks is performed such that the result bits of one compare block represents the compare result of the previous compare blocks in the chain.

29. 发明授权

US10379811B2 Normalization of a product on a datapath 有权
公开(公告)号：US10379811B2
公开(公告)日：2019-08-13
申请号：US15815120
申请日：2017-11-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Klaus M. Kroener , Cedric Lichtenau , Silvia M. Mueller , Andreas Wagner
IPC分类号： G06F5/01 , G06F7/544 , G06F7/483
摘要： A unit operates on a sum term and a carry term separated into a high part and a low part of a product and performs a method that includes iteratively computing a carry save product and separating the carry save product into the high part and the low part: an intermediate product. The unit generates an intermediate wide result by performing a wide addition of the intermediate product to generate an unrounded sum for the high part (i.e., a fused-multiply-add high part) and the low part (i.e., a fused-multiply-add high part). The unit pre-aligns the intermediate wide result on two fixed length shifters such that the fused-multiply-add high part and the fused-multiply-add low part are pre-aligned to each fit on one shifter of the two fixed length shifters.

30. 发明申请

US20190243650A1 METHOD TO BUILD RECONFIGURABLE VARIABLE LENGTH COMPARATORS 审中-公开
公开(公告)号：US20190243650A1
公开(公告)日：2019-08-08
申请号：US15889315
申请日：2018-02-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Cedric Lichtenau , Silvia M. Mueller , Jens P. Seifert , Jörg-Stephan Vogt , Markus Lachenmayr , L'Emir Salim Chehab , Pavankrishna Ellore Ramesh , Sourabh Chougule
IPC分类号： G06F9/30 , G06F17/30
摘要： The present disclosure relates performing of comparisons between a first and a second vector. The memory location has a size or length of m bits. A compare block to compare two single bits is used. The compare block comprises: two input bits associated to one of the bits from the first and the second vector respectively; a greater than input bit and a lower than input bit; a cascade enable input bit to control if the greater than input bit and the lower than input bit are considered; a greater than result bit, a lower than result bit, and an equal result bit. A daisy chaining of m of the one-bit compare blocks is performed such that the result bits of one compare block represents the compare result of the previous compare blocks in the chain.

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