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21. 发明申请

US20230032586A1 SCALABLE ACCESS CONTROL CHECKING FOR CROSS-ADDRESS-SPACE DATA MOVEMENT 有权
公开(公告)号：US20230032586A1
公开(公告)日：2023-02-02
申请号：US17711928
申请日：2022-04-01
申请人： Intel Corporation
发明人： Narayan Ranganathan , Philip R. Lantz , Rajesh M. Sankaran , Sanjay Kumar , Saurabh Gayen , Nikhil Rao , Utkarsh Y. Kakaiya , Dhananjay A. Joshi , David Jiang , Ashok Raj
IPC分类号： G06F3/06 , G06F9/455
摘要： Methods and apparatus relating to scalable access control checking for cross-address-space data movement are described. In an embodiment, a memory stores an InterDomain Permissions Table (IDPT) having a plurality of entries. At least one entry of the IDPT provides a relationship between a target address space identifier and a plurality of requester address space identifiers. A hardware accelerator device allows access to a target address space, corresponding to the target address space identifier, by one or more of requesters, corresponding to the plurality of requester address space identifiers, respectively, based at least in part on the relationship provided by the at least one entry of the IDPT. Other embodiments are also disclosed and claimed.

22. 发明授权

US11461100B2 Process address space identifier virtualization using hardware paging hint 有权
公开(公告)号：US11461100B2
公开(公告)日：2022-10-04
申请号：US17253053
申请日：2018-12-21
申请人： Intel Corporation
发明人： Kun Tian , Sanjay Kumar , Ashok Raj , Yi Liu , Rajesh M. Sankaran , Philip R. Lantz
IPC分类号： G06F9/34 , G06F9/38 , G06F9/455 , G06F12/1009 , G06F13/42
摘要： Process address space identifier virtualization uses hardware paging hint. The processing device (100) comprising: a processing core (110); and a translation circuit coupled to the processing core, the translation circuit to: receive a workload instruction from a guest application being executed by the processing device, the workload instruction comprising an untranslated guest process address space identifier (gPASID), a workload for an input/output (I/O) target device, and an identifier of a submission register on the I/O target device (410), access a paging data structure (PDS) associated with the guest application to retrieve a page table entry corresponding to the gPASID and the identifier of the submission register (420), determine a value of an I/O hint bit of the page table entry corresponding to the gPASID and the identifier of the submission register (430), responsive to determining that the I/O hint bit is enabled, keep the untranslated gPASID in the workload instruction (440), and provide the workload instruction to a work queue of the I/O target device (450).

23. 发明申请

US20210173790A1 UNIFIED ADDRESS TRANSLATION FOR VIRTUALIZATION OF INPUT/OUTPUT DEVICES 有权
公开(公告)号：US20210173790A1
公开(公告)日：2021-06-10
申请号：US16651786
申请日：2017-12-29
申请人： Intel Corporation
发明人： Utkarsh Y. Kakaiya , Sanjay Kumar , Rajesh M. Sankaran , Philip R. Lantz , Ashok Raj , Kun Tian
IPC分类号： G06F12/1009 , G06F12/1081 , G06F12/06 , G06F9/455
摘要： Embodiments of apparatuses, methods, and systems for unified address translation for virtualization of input/output devices are described. In an embodiment, an apparatus includes first circuitry to use at least an identifier of a device to locate a context entry and second circuitry to use at least a process address space identifier (PASID) to locate a PASID-entry. The context entry is to include at least one of a page-table pointer to a page-table translation structure and a PASID. The PASID-entry is to include at least one of a first-level page-table pointer to a first-level translation structure and a second-level page-table pointer to a second-level translation structure. The PASID is to be supplied by the device. At least one of the apparatus, the context entry, and the PASID entry is to include one or more control fields to indicate whether the first-level page-table pointer or the second-level page-table pointer is to be used.

24. 发明申请

US20190303324A1 HIGHLY SCALABLE ACCELERATOR 审中-公开
公开(公告)号：US20190303324A1
公开(公告)日：2019-10-03
申请号：US15940128
申请日：2018-03-29
申请人： Intel Corporation
发明人： Philip R. Lantz , Sanjay Kumar , Rajesh M. Sankaran , Saurabh Gayen
IPC分类号： G06F13/364 , G06F13/24
摘要： Embodiments of apparatuses, methods, and systems for highly scalable accelerators are described. In an embodiment, an apparatus includes an interface to receive a plurality of work requests from a plurality of clients and a plurality of engines to perform the plurality of work requests. The work requests are to be dispatched to the plurality of engines from a plurality of work queues. The work queues are to store a work descriptor per work request. Each work descriptor is to include all information needed to perform a corresponding work request.

25. 发明申请

US20160283354A1 TECHNOLOGIES FOR APPLICATION VALIDATION IN PERSISTENT MEMORY SYSTEMS 有权
标题翻译：在不间断存储系统中应用验证的技术
公开(公告)号：US20160283354A1
公开(公告)日：2016-09-29
申请号：US14670965
申请日：2015-03-27
申请人： Intel Corporation
发明人： Philip R. Lantz , Thomas Willhalm , Kirill Instrumentov , Karthik Kumar
IPC分类号： G06F11/36
CPC分类号： G06F11/3688 , G06F11/3648
摘要： Technologies for software testing include a computing device having persistent memory that includes a platform simulator and an application or other code module to be tested. The computing device generates a checkpoint for the application at a test location using the platform simulator. The computing device executes the application from the test location to an end location and traces all writes to persistent memory using the platform simulator. The computing device generates permutations of persistent memory writes that are allowed by the hardware specification of the computing device simulated by the platform simulator. The computing device replays each permutation from the checkpoint, simulates a power failure, and then invokes a user-defined test function using the platform simulator. The computing device may test different permutations of memory writes until the application's use of persistent memory is validated. Other embodiments are described and claimed.
摘要翻译：用于软件测试的技术包括具有持久存储器的计算设备，其包括平台模拟器和要测试的应用或其他代码模块。计算设备使用平台模拟器在测试位置生成应用程序的检查点。计算设备从测试位置执行应用程序到终端位置，并使用平台模拟器跟踪对持久存储器的所有写入。计算设备产生由平台模拟器模拟的计算设备的硬件规范允许的持久存储器写入的排列。计算设备从检查点重播每个置换，模拟电源故障，然后使用平台模拟器调用用户定义的测试功能。计算设备可以测试存储器写入的不同排列，直到应用程序使用永久存储器被验证为止。描述和要求保护其他实施例。

26. 发明授权

US11734209B2 Scalable interrupt virtualization for input/output devices 有权
公开(公告)号：US11734209B2
公开(公告)日：2023-08-22
申请号：US17550977
申请日：2021-12-14
申请人： Intel Corporation
发明人： Sanjay Kumar , Rajesh M. Sankaran , Philip R. Lantz , Utkarsh Y. Kakaiya , Kun Tian
IPC分类号： G06F13/28 , G06F13/24 , G06F9/455 , G06F9/48
CPC分类号： G06F13/24 , G06F9/45558 , G06F9/4812 , G06F2009/45579
摘要： Implementations of the disclosure provide processing device comprising: an interrupt managing circuit to receive an interrupt message directed to an application container from an assignable interface (AI) of an input/output (I/O) device. The interrupt message comprises an address space identifier (ASID), an interrupt handle and a flag to distinguish the interrupt message from a direct memory access (DMA) message. Responsive to receiving the interrupt message, a data structure associated with the interrupt managing circuit is identified. An interrupt entry from the data structure is selected based on the interrupt handle. It is determined that the ASID associated with the interrupt message matches an ASID in the interrupt entry. Thereupon, an interrupt in the interrupt entry is forwarded to the application container.

27. 发明授权

US11650947B2 Highly scalable accelerator 有权
公开(公告)号：US11650947B2
公开(公告)日：2023-05-16
申请号：US17410063
申请日：2021-08-24
申请人： Intel Corporation
发明人： Philip R. Lantz , Sanjay Kumar , Rajesh M. Sankaran , Saurabh Gayen
IPC分类号： G06F13/364 , G06F13/24 , G06F9/50
CPC分类号： G06F13/364 , G06F9/5027 , G06F13/24
摘要： Embodiments of apparatuses, methods, and systems for highly scalable accelerators are described. In an embodiment, an apparatus includes an interface to receive a plurality of work requests from a plurality of clients and a plurality of engines to perform the plurality of work requests. The work requests are to be dispatched to the plurality of engines from a plurality of work queues. The work queues are to store a work descriptor per work request. Each work descriptor is to include all information needed to perform a corresponding work request.

28. 发明申请

US20230032236A1 DATA STREAMING ACCELERATOR 有权
公开(公告)号：US20230032236A1
公开(公告)日：2023-02-02
申请号：US17875198
申请日：2022-07-27
申请人： Intel Corporation
发明人： Rajesh M. Sankaran , Philip R. Lantz , Narayan Ranganathan , Saurabh Gayen , Sanjay Kumar , Nikhil Rao , Dhananjay A. Joshi , Hai Ming Khor , Utkarsh Y. Kakaiya
IPC分类号： G06F3/06
摘要： Methods and apparatus relating to data streaming accelerators are described. In an embodiment, a hardware accelerator such as a Data Streaming Accelerator (DSA) logic circuitry provides high-performance data movement and/or data transformation for data to be transferred between a processor (having one or more processor cores) and a storage device. Other embodiments are also disclosed and claimed.

29. 发明授权

US11556363B2 Techniques for virtual machine transfer and resource management 有权
公开(公告)号：US11556363B2
公开(公告)日：2023-01-17
申请号：US16479395
申请日：2017-03-31
申请人： Intel Corporation
发明人： Sanjay Kumar , Philip R. Lantz , Kun Tian , Utkarsh Y. Kakaiya , Rajesh M. Sankaran
IPC分类号： G06F9/455 , G06F9/30 , G06F12/1009
摘要： Techniques for transferring virtual machines and resource management in a virtualized computing environment are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processor, and logic for transferring a virtual machine (VM), at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one processor, the logic to generate a plurality of virtualized capability registers for a virtual device (VDEV) by virtualizing a plurality of device-specific capability registers of a physical device to be virtualized by the VM, the plurality of virtualized capability registers comprising a plurality of device-specific capabilities of the physical device, determine a version of the physical device to support via a virtual machine monitor (VMM), and expose a subset of the virtualized capability registers associated with the version to the VM. Other embodiments are described and claimed.

30. 发明申请

US20220164384A1 EFFICIENT STORAGE AND PROCESSING OF HIGH-DIMENSIONAL FEATURE VECTORS 有权
公开(公告)号：US20220164384A1
公开(公告)日：2022-05-26
申请号：US17362554
申请日：2021-06-29
申请人： Intel Corporation
发明人： Luis Carlos Maria Remis , Vishakha Gupta , Christina R. Strong , Philip R. Lantz
IPC分类号： G06F16/901 , G06F16/903 , G06K9/62 , G06F16/22 , G06F16/2455
摘要： In one embodiment, an apparatus comprises a storage device and a processor. The storage device stores a feature vector index, wherein the feature vector index comprises a sparse-array data structure representing a feature space for a set of labeled feature vectors, wherein the set of labeled feature vectors are assigned to a plurality of classes. The processor is to: receive a query corresponding to a target feature vector; access, via the storage device, a first portion of the feature vector index, wherein the first portion of the feature vector index comprises a subset of labeled feature vectors that correspond to a same portion of the feature space as the target feature vector; determine the corresponding class of the target feature vector based on the subset of labeled feature vectors; and provide a response to the query based on the corresponding class.

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