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21. 发明申请

US20150095580A1 SCALABLY MECHANISM TO IMPLEMENT AN INSTRUCTION THAT MONITORS FOR WRITES TO AN ADDRESS 审中-公开
标题翻译：规范机制，以实施向地址写入的监视器的指令
公开(公告)号：US20150095580A1
公开(公告)日：2015-04-02
申请号：US14040375
申请日：2013-09-27
申请人： Intel Corporation
发明人： Yen-Cheng Liu , Bahaa Fahim , Erik G. Hallnor , Jeffrey D. Chamberlain , Stephen R. Van Doren , Antonio Juan
IPC分类号： G06F12/08
摘要： A processor includes a cache-side address monitor unit corresponding to a first cache portion of a distributed cache that has a total number of cache-side address monitor storage locations less than a total number of logical processors of the processor. Each cache-side address monitor storage location is to store an address to be monitored. A core-side address monitor unit corresponds to a first core and has a same number of core-side address monitor storage locations as a number of logical processors of the first core. Each core-side address monitor storage location is to store an address, and a monitor state for a different corresponding logical processor of the first core. A cache-side address monitor storage overflow unit corresponds to the first cache portion, and is to enforce an address monitor storage overflow policy when no unused cache-side address monitor storage location is available to store an address to be monitored.
摘要翻译：处理器包括对应于分布式高速缓存的第一高速缓存部分的高速缓存器侧地址监视器单元，其具有小于处理器的逻辑处理器总数的高速缓存器侧地址监视器存储位置的总数。每个缓存侧地址监视器存储位置是存储要监视的地址。核心侧地址监视器单元对应于第一核心，并且具有与第一核心的多个逻辑处理器相同数量的核心侧地址监视器存储位置。每个核心侧地址监视器存储位置用于存储第一核心的不同对应逻辑处理器的地址和监视状态。高速缓存侧地址监视器存储溢出单元对应于第一高速缓存部分，并且当没有未使用的高速缓存侧地址监视器存储位置可用于存储要监视的地址时，强制执行地址监视器存储溢出策略。

22. 发明申请

US20220114122A1 HIGH PERFORMANCE INTERCONNECT 有权
公开(公告)号：US20220114122A1
公开(公告)日：2022-04-14
申请号：US17556853
申请日：2021-12-20
申请人： Intel Corporation
发明人： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC分类号： G06F13/22 , H04L49/15 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F13/42 , G06F8/71 , G06F8/77 , G06F9/30 , G06F12/0806 , G06F9/46 , G06F13/40 , G06F9/445 , G06F1/3287 , G06F11/10 , H04L9/06 , G06F12/0808
摘要： A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

23. 发明授权

US11269793B2 High performance interconnect 有权
公开(公告)号：US11269793B2
公开(公告)日：2022-03-08
申请号：US16937499
申请日：2020-07-23
申请人： Intel Corporation
发明人： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC分类号： G06F13/22 , H04L49/15 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F13/42 , G06F8/71 , G06F8/77 , G06F9/30 , G06F12/0806 , G06F9/46 , G06F13/40 , G06F9/445 , G06F1/3287 , G06F11/10 , H04L9/06 , G06F12/0808 , H04L45/74 , G06F8/73 , H04L12/46
摘要： A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

24. 发明授权

US10339060B2 Optimized caching agent with integrated directory cache 有权
公开(公告)号：US10339060B2
公开(公告)日：2019-07-02
申请号：US15396174
申请日：2016-12-30
申请人： Intel Corporation
发明人： Bahaa Fahim , Ashok Jagannathan , Jeffrey D. Chamberlain , Samuel D. Strom
IPC分类号： G06F12/0817 , G06F12/0831
摘要： System, method, and processor for enabling early deallocation of tracker entries which track memory accesses are described herein. One embodiment of a method includes: maintaining an RSF corresponding to a first processing unit of a plurality of processing units to track cache lines, wherein a cache line is tracked by the RSF if the cache line is stored in both a memory and one or more other processing unit, the memory is coupled to and shared by the plurality of processing units; receiving a request to access a target cache line from a processing core of the first processing unit; allocating a tracker entry corresponding to the request, the tracker entry used to track a status of the request; performing a lookup in the RSF for the target cache line; and deallocating the tracker entry responsive to a detection that the target cache line is not tracked the RSF.

25. 发明申请

US20190004921A1 METHOD AND SYSTEM FOR CACHE AGENT TRACE AND CAPTURE 审中-公开
公开(公告)号：US20190004921A1
公开(公告)日：2019-01-03
申请号：US15639294
申请日：2017-06-30
申请人： Intel Corporation
发明人： Bahaa Fahim , Swadesh Choudhary
IPC分类号： G06F11/34 , G06F11/14 , G06F11/30
CPC分类号： G06F11/3485 , G06F11/079 , G06F11/1446 , G06F11/3037 , G06F11/3461 , G06F11/349 , G06F11/3636 , G06F2201/84 , G06F2201/86 , G06F2201/885
摘要： In one embodiment, a processor comprises a fabric interconnect to couple a first cache agent to at least one of a memory controller or an input/output (I/O) controller; and a first cache agent comprising a cache controller coupled to a cache; and a trace and capture engine to periodically capture a snapshot of state information associated with the first cache agent; trace events to occur at the first cache agent in between captured snapshots; and send the captured snapshots and traced events via the fabric interconnect to the memory controller or I/O controller for storage at a system memory or storage device.

26. 发明申请

US20180189180A1 OPTIMIZED CACHING AGENT WITH INTEGRATED DIRECTORY CACHE 审中-公开
公开(公告)号：US20180189180A1
公开(公告)日：2018-07-05
申请号：US15396174
申请日：2016-12-30
申请人： Intel Corporation
发明人： Bahaa Fahim , Ashok Jagannathan , Jeffrey D. Chamberlain , Samuel D. Strom
IPC分类号： G06F12/0815
CPC分类号： G06F12/0833 , G06F12/0824 , G06F2212/1024 , G06F2212/1041
摘要： System, method, and processor for enabling early deallocation of tracker entries which track memory accesses are described herein. One embodiment of a method includes: maintaining an RSF corresponding to a first processing unit of a plurality of processing units to track cache lines, wherein a cache line is tracked by the RSF if the cache line is stored in both a memory and one or more other processing unit, the memory is coupled to and shared by the plurality of processing units; receiving a request to access a target cache line from a processing core of the first processing unit; allocating a tracker entry corresponding to the request, the tracker entry used to track a status of the request; performing a lookup in the RSF for the target cache line; and deallocating the tracker entry responsive to a detection that the target cache line is not tracked the RSF.

27. 发明授权

US09959939B2 Granular cache repair 有权
公开(公告)号：US09959939B2
公开(公告)日：2018-05-01
申请号：US14581686
申请日：2014-12-23
申请人： Intel Corporation
发明人： Bahaa Fahim , Min Huang , Zhiguo Wang
IPC分类号： G06F12/06 , G11C29/00 , G06F11/08 , G06F12/0895 , G06F11/00 , G11C15/04 , G06F11/10 , G06F11/16
CPC分类号： G11C29/78 , G06F11/00 , G06F11/08 , G06F11/10 , G06F11/1004 , G06F11/1064 , G06F11/1666 , G06F12/0638 , G06F12/0895 , G11C15/04
摘要： Systems and methods for granular cache repair. An example processing system comprises a processing core communicatively coupled to a cache via a cache controller and a cache repair memory communicatively coupled to the cache controller. The cache controller is configured, responsive to receiving a read request referencing a physical address, to: retrieve cache data from a cache location identified by the physical address, retrieve, in parallel with retrieving the cache data, cache repair data from the cache repair memory, the cache repair data associated with the cache location, the cache repair data comprising at least one of: a bit repair value, a column repair value, and a raw repair value, and output the cache data multiplexed with the cache repair data.

28. 发明申请

US20170109315A1 HIGH PERFORMANCE INTERCONNECT 审中-公开
公开(公告)号：US20170109315A1
公开(公告)日：2017-04-20
申请号：US15393153
申请日：2016-12-28
申请人： Intel Corporation
发明人： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert H. Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC分类号： G06F13/42 , H04L9/06 , G06F11/10 , G06F13/40
CPC分类号： G06F13/22 , G06F1/3287 , G06F8/71 , G06F8/73 , G06F8/77 , G06F9/30145 , G06F9/44505 , G06F9/466 , G06F11/1004 , G06F12/0806 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F13/4273 , G06F13/4282 , G06F13/4286 , G06F13/4291 , G06F2212/1016 , G06F2212/2542 , G06F2212/622 , H04L9/0662 , H04L12/4641 , H04L45/74 , H04L49/15 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/40 , Y02D10/44 , Y02D30/30
摘要： A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

29. 发明申请

US20170019350A1 SHARED MESH 审中-公开
标题翻译：共享的MESH
公开(公告)号：US20170019350A1
公开(公告)日：2017-01-19
申请号：US14800552
申请日：2015-07-15
申请人： INTEL CORPORATION
发明人： Bahaa Fahim , Yen-Cheng Liu , Chung-Chi Wang , Donald C. Soltis, JR. , Terry C. Huang , Tejpal Singh , Bongjin Jung , Nazar Syed Haider
IPC分类号： H04L12/933 , H04L12/937
CPC分类号： H04L49/103 , G06F11/1064 , G06F13/4022 , H04L49/254
摘要： A shared mesh comprises a mesh station. The mesh station is used to couple to at least a first core component and a second core component. The mesh station includes a logic unit. The mesh station is shared by at least the first core component and the second core component. A memory is coupled to the mesh station.
摘要翻译：共享网格包括网格站。网状站用于耦合到至少第一核心组件和第二核心组件。网格站包括一个逻辑单元。网状站由至少第一核心组件和第二核心组件共享。存储器耦合到网格站。

30. 发明申请

US20150081984A1 HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL 审中-公开
标题翻译：高性能互连协调协议
公开(公告)号：US20150081984A1
公开(公告)日：2015-03-19
申请号：US14554532
申请日：2014-11-26
申请人： Intel Corporation
发明人： Robert G. Blankenship , Bahaa Fahim , Robert Beers , Yen-Cheng Liu , Vedaraman Geetha , Herbert H. Hum , Jeff Willey
IPC分类号： G06F12/08
CPC分类号： G06F13/22 , G06F1/3287 , G06F8/71 , G06F8/73 , G06F8/77 , G06F9/30145 , G06F9/44505 , G06F9/466 , G06F11/1004 , G06F12/0806 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F13/4273 , G06F13/4282 , G06F13/4286 , G06F13/4291 , G06F2212/1016 , G06F2212/2542 , G06F2212/622 , H04L9/0662 , H04L12/4641 , H04L45/74 , H04L49/15 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/40 , Y02D10/44 , Y02D30/30
摘要： A request is received that is to reference a first agent and to request a particular line of memory to be cached in an exclusive state. A snoop request is sent intended for one or more other agents. A snoop response is received that is to reference a second agent, the snoop response to include a writeback to memory of a modified cache line that is to correspond to the particular line of memory. A complete is sent to be addressed to the first agent, wherein the complete is to include data of the particular line of memory based on the writeback.
摘要翻译：接收到要引用第一代理并请求特定的内存行以独占状态被缓存的请求。发送窥探请求用于一个或多个其他代理。接收到一个窥探响应，该响应是引用第二个代理，窥探响应包括对与特定的存储器行相对应的修改的高速缓存行的存储器的回写。一个完整的发送被发送到第一个代理，其中完整的是基于回写来包括特定的存储器行的数据。

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