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21. 发明申请

US20050194597A1 Transistors of semiconductor device having channel region in a channel-portion hole and methods of forming the same 有权
标题翻译：在通道部分孔中具有沟道区的半导体器件的晶体管及其形成方法
公开(公告)号：US20050194597A1
公开(公告)日：2005-09-08
申请号：US11073246
申请日：2005-03-04
申请人： Hyeoung-Won Seo , Du-Heon Song , Sang-Hyun Lee
发明人： Hyeoung-Won Seo , Du-Heon Song , Sang-Hyun Lee
IPC分类号： H01L27/108 , H01L21/00 , H01L29/12
CPC分类号： H01L27/10891 , H01L27/10823 , H01L27/1087
摘要： According to some embodiments of the invention, transistors of a semiconductor device have a channel region in a channel-portion hole. Methods include forming embodiments of the transistor having a channel-portion hole disposed in a semiconductor substrate. A channel-portion trench pad and a channel-portion layer are sequentially formed at a lower portion of the channel-portion hole. A word line insulating layer pattern and a word line pattern are sequentially stacked on the channel-portion layer and fill the channel-portion hole, disposed on the semiconductor substrate. The channel-portion layer is formed to contact the semiconductor substrate through a portion of sidewall of the channel-portion hole, and forms a channel region under the word line pattern. Punchthrough is prevented between electrode impurity regions corresponding to source and drain regions.
摘要翻译：根据本发明的一些实施例，半导体器件的晶体管在沟道部分孔中具有沟道区。方法包括形成具有设置在半导体衬底中的沟道部分孔的晶体管的实施例。通道部分沟槽焊盘和沟道部分层依次形成在沟道部分孔的下部。字线绝缘层图案和字线图案依次层叠在沟道部分层上并填充设置在半导体衬底上的沟道部分孔。沟道部分层形成为通过沟道部分孔的侧壁的一部分与半导体衬底接触，并在字线图案下形成沟道区。防止对应于源区和漏区的电极杂质区之间的穿透。

22. 发明申请

US20050133836A1 Asymmetric MOS transistor with trench-type gate 有权
标题翻译：具有沟槽型栅极的非对称MOS晶体管
公开(公告)号：US20050133836A1
公开(公告)日：2005-06-23
申请号：US11021349
申请日：2004-12-23
申请人： Hyeoung-Won Seo , Dong-Hyun Kim , Du-Heon Song , Sang-Hyun Lee
发明人： Hyeoung-Won Seo , Dong-Hyun Kim , Du-Heon Song , Sang-Hyun Lee
IPC分类号： H01L21/336 , H01L29/10 , H01L29/76 , H01L29/78
CPC分类号： H01L29/7835 , H01L29/1045 , H01L29/4236 , H01L29/66621 , H01L29/66659
摘要： a A MOS (metal oxide semiconductor) transistor with a trench-type gate is fabricated with a channel stopping region for forming an asymmetric channel region for reducing short channel effects. For example in fabricating an N-channel MOS transistor, a gate structure is formed within a trench that is within a P-well. A channel stopping region with a P-type dopant is formed to a first side of the trench to completely contain an N-type source junction therein. An N-type drain junction is formed within a LDD region to a second side of the trench, thus forming the asymmetric channel region.
摘要翻译：制造具有沟槽型栅极的MOS（金属氧化物半导体）晶体管，其具有用于形成用于减小短沟道效应的不对称沟道区的沟道停止区域。例如在制造N沟道MOS晶体管时，栅极结构形成在P阱内的沟槽内。在沟槽的第一侧形成具有P型掺杂剂的沟道停止区，以在其中完全包含N型源极结。在LDD区内形成N型漏极结至沟槽的第二侧，从而形成非对称沟道区。

23. 发明申请

US20060118885A1 Semiconductor device having resistor and method of fabricating the same 有权
标题翻译：具有电阻器的半导体器件及其制造方法
公开(公告)号：US20060118885A1
公开(公告)日：2006-06-08
申请号：US11284237
申请日：2005-11-21
申请人： Du-Heon Song
发明人： Du-Heon Song
IPC分类号： H01L29/76 , H01L29/00
CPC分类号： H01L27/0629 , H01L27/0688 , H01L27/10817 , H01L27/10894 , H01L28/20 , H01L28/91
摘要： In a semiconductor device having a resistor and a method of fabricating the same, the device includes a semiconductor substrate having a cell region and a peripheral region. A lower interlayer insulating layer is disposed on the semiconductor substrate. A buffer pad is disposed on the lower interlayer insulating layer in the cell region. A capacitor is provided to have a storage node electrode disposed on the buffer pad, a plate electrode covering the storage node electrode, and a capacitor dielectric is interposed between the storage node electrode and the plate electrode. A lower resistor is disposed on the lower interlayer insulating layer in the peripheral region. 10 An upper resistor is disposed on the lower resistor to expose both ends of the lower resistor. An inter-resistor insulating layer is interposed at least between the lower resistor and the upper resistor. An upper interlayer insulating layer is disposed on the lower interlayer insulating layer to cover the capacitor, the lower resistor, and the upper resistor. A resistor interconnection line is disposed on the upper interlayer insulating layer, to contact a resistor contact plug penetrating the upper interlayer insulating layer and is electrically connected to a first end of the lower resistor and a first end of the upper resistor.
摘要翻译：在具有电阻器的半导体器件及其制造方法中，该器件包括具有单元区域和周边区域的半导体衬底。下半层绝缘层设置在半导体衬底上。缓冲垫设置在电池区域中的下层间绝缘层上。设置电容器以具有设置在缓冲垫上的存储节点电极，覆盖存储节点电极的平板电极和电容器电介质介于存储节点电极和平板电极之间。下部电阻器设置在周边区域的下部层间绝缘层上。 10上电阻设在下电阻上，露出下电阻的两端。至少在下电阻器和上电阻器之间插入有电阻器绝缘层。上层间绝缘层设置在下层绝缘层上以覆盖电容器，下电阻器和上电阻器。电阻器互连线设置在上层间绝缘层上，以接触穿过上层间绝缘层的电阻器接触插塞，并且电连接到下电阻器的第一端和上电阻器的第一端。

24. 发明授权

US5942450A Method of fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5942450A
公开(公告)日：1999-08-24
申请号：US990148
申请日：1997-12-12
申请人： Du-Heon Song
发明人： Du-Heon Song
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/8242 , H01L27/105 , H01L27/108 , H01L21/00
CPC分类号： H01L21/8234 , H01L27/105 , H01L27/10873 , H01L27/10894
摘要： A method of fabricating a semiconductor device includes the steps of sequentially forming a gate oxide layer, a gate material layer and a cap insulating layer on a semiconductor substrate, selectively etching them to form a gate, sequentially forming a plurality of material layers on the overall surface of the semiconductor substrate including the gate, etching them back to form a gate sidewall spacer out of the plurality of material layers, and selectively removing the plurality of material layers forming the gate sidewall spacer to form gate sidewall spacers having lengths different from each other, the lengths depending on a particular region of the substrate.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在半导体衬底上依次形成栅极氧化层，栅极材料层和帽绝缘层，选择性地蚀刻它们以形成栅极，在整体上依次形成多个材料层包括栅极的半导体衬底的表面，将其回蚀刻以在多个材料层中形成栅极侧壁间隔物，并且选择性地去除形成栅极侧壁间隔物的多个材料层，以形成具有彼此长度不同的栅极侧壁间隔物长度取决于衬底的特定区域。

25. 发明授权

US5686331A Fabrication method for semiconductor device 失效
标题翻译：半导体器件制造方法
公开(公告)号：US5686331A
公开(公告)日：1997-11-11
申请号：US773086
申请日：1996-12-24
申请人： Du-Heon Song
发明人： Du-Heon Song
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L29/49 , H01L29/78 , H01L21/8232
CPC分类号： H01L29/6653 , H01L21/823443 , H01L29/4983 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： A fabrication method for a semiconductor device which is capable of preventing the shorting of the semiconductor device by performing an ion-implantation of an impurity after forming an insulating layer on a gate electrode, and forming sidewall spacers on the upper surface of the gate electrode and at the sides thereof includes: forming on a semiconductor substrate a pattern including a gate insulating film, a gate electrode on the gate insulating film and a disposable layer on the gate electrode; forming low concentration impurity regions in the substrate by performing an ion implantation, using the pattern as a mask; forming first sidewall spacers at the sides of the pattern; forming high concentration impurity regions in the substrate by performing an ion implantation, using the pattern and the sidewall spacers as a mask; stripping the disposable layer; forming second sidewall spacers at the sides of the first sidewall spacers and on both ends of the upper surface of the gate electrode; and forming a reaction layer of a metal and a silicon on the gate electrode and the high concentration impurity regions.
摘要翻译：一种半导体器件的制造方法，其能够通过在栅电极上形成绝缘层之后进行杂质的离子注入来防止半导体器件的短路，并且在栅电极的上表面上形成侧壁间隔物，以及其包括：在半导体基板上形成包括栅极绝缘膜，栅极绝缘膜上的栅电极和栅电极上的一次性层的图案; 通过使用该图案作为掩模，通过进行离子注入在基板中形成低浓度杂质区域; 在图案的侧面形成第一侧壁间隔物; 通过使用图案和侧壁间隔物作为掩模，通过进行离子注入在基板中形成高浓度杂质区域; 剥离一次性层; 在第一侧壁间隔物的侧面和栅电极的上表面的两端上形成第二侧壁间隔物; 以及在栅电极和高浓度杂质区上形成金属和硅的反应层。

26. 发明授权

US07402871B2 Semiconductor device having resistor and method of fabricating the same 有权
标题翻译：具有电阻器的半导体器件及其制造方法
公开(公告)号：US07402871B2
公开(公告)日：2008-07-22
申请号：US11284237
申请日：2005-11-21
申请人： Du-Heon Song
发明人： Du-Heon Song
IPC分类号： H01L29/76 , H01L21/20
CPC分类号： H01L27/0629 , H01L27/0688 , H01L27/10817 , H01L27/10894 , H01L28/20 , H01L28/91
摘要： In a semiconductor device having a resistor and a method of fabricating the same, the device includes a semiconductor substrate having a cell region and a peripheral region. A lower interlayer insulating layer is disposed on the semiconductor substrate. A buffer pad is disposed on the lower interlayer insulating layer in the cell region. A capacitor is provided to have a storage node electrode disposed on the buffer pad, a plate electrode covering the storage node electrode, and a capacitor dielectric is interposed between the storage node electrode and the plate electrode. A lower resistor is disposed on the lower interlayer insulating layer in the peripheral region. An upper resistor is disposed on the lower resistor to expose both ends of the lower resistor. An inter-resistor insulating layer is interposed at least between the lower resistor and the upper resistor. An upper interlayer insulating layer is disposed on the lower interlayer insulating layer to cover the capacitor, the lower resistor, and the upper resistor. A resistor interconnection line is disposed on the upper interlayer insulating layer, to contact a resistor contact plug penetrating the upper interlayer insulating layer and is electrically connected to a first end of the lower resistor and a first end of the upper resistor.
摘要翻译：在具有电阻器的半导体器件及其制造方法中，该器件包括具有单元区域和周边区域的半导体衬底。下半层绝缘层设置在半导体衬底上。缓冲垫设置在电池区域中的下层间绝缘层上。设置电容器以具有设置在缓冲垫上的存储节点电极，覆盖存储节点电极的平板电极和电容器电介质介于存储节点电极和平板电极之间。下部电阻器设置在周边区域的下部层间绝缘层上。上电阻器设置在下电阻器上以露出下电阻器的两端。至少在下电阻器和上电阻器之间插入有电阻器绝缘层。上层间绝缘层设置在下层绝缘层上以覆盖电容器，下电阻器和上电阻器。电阻器互连线设置在上层间绝缘层上，以接触穿过上层间绝缘层的电阻器接触插塞，并且电连接到下电阻器的第一端和上电阻器的第一端。

27. 发明授权

US07323746B2 Recess gate-type semiconductor device and method of manufacturing the same 失效
标题翻译：嵌入式门式半导体器件及其制造方法
公开(公告)号：US07323746B2
公开(公告)日：2008-01-29
申请号：US11228041
申请日：2005-09-14
申请人： Won-Mo Park , Jae-Choel Paik , Du-Heon Song , Dong-Hyun Kim , Chang-Sub Lee
发明人： Won-Mo Park , Jae-Choel Paik , Du-Heon Song , Dong-Hyun Kim , Chang-Sub Lee
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L29/0692 , H01L29/4236
摘要： A recess gate-type semiconductor device includes a gate electrode having a recessed portion at least partially covering a recess trench in an active region, and source/drain regions disposed in the active region that are separated by the gate electrode. The recess trench is separated from sidewalls of a device isolation region in a first direction and contacts sidewalls of the device isolation region in a second direction. The width of the recess trench of the active region in the second direction may be greater than the width of the source/drain regions in the second direction, and the recessed portion of the gate electrode may have tabs protruding in the first direction at its corners. Therefore, the semiconductor device has excellent junction leakage current and excellent refresh characteristics.
摘要翻译：凹槽型半导体器件包括具有至少部分地覆盖有源区中的凹槽的凹部的栅电极和设置在有源区中的由栅电极分离的源/漏区。所述凹槽在第一方向上与器件隔离区的侧壁分离，并沿着第二方向接触器件隔离区的侧壁。有源区在第二方向上的凹槽的宽度可以大于第二方向上的源极/漏极区的宽度，并且栅电极的凹陷部分可以具有在其角部沿第一方向突出的突出部。因此，半导体器件具有优异的结漏电流和优异的刷新特性。

28. 发明授权

US07034368B2 Semiconductor memory device and fabrication method thereof using damascene gate and epitaxial growth 失效
标题翻译：半导体存储器件及其制造方法使用镶嵌栅极和外延生长
公开(公告)号：US07034368B2
公开(公告)日：2006-04-25
申请号：US11001355
申请日：2004-11-30
申请人： Du-Heon Song
发明人： Du-Heon Song
IPC分类号： H01L31/062 , H01L29/94
CPC分类号： H01L21/76897 , H01L21/28525 , H01L21/76885 , H01L21/76895 , H01L27/10855 , H01L27/10888
摘要： A semiconductor memory device and fabrication method of same includes the processes of forming sacrifice gates on a silicon substrate with the sacrifice gates apart from each other. A first conductive layer is formed on an exposed portion of the silicon substrate between the sacrifice gates and a first inter-insulation layer is formed that exposes the first conductive layer and the sacrifice gates. The exposed sacrifice gates are removed to form openings and damascene gates are subsequently formed in the openings. Capping layers are formed on the top of the gates and a second conductive layer is formed on the exposed first conductive layer. A second inter-insulation layer is formed on the silicon substrate, and bit line contacts that expose the second conductive layer are formed by etching the second inter-insulation layer.
摘要翻译：半导体存储器件及其制造方法包括在牺牲栅彼此分开的情况下在硅衬底上形成牺牲栅的工艺。在牺牲栅之间的硅衬底的暴露部分上形成第一导电层，并且形成暴露第一导电层和牺牲栅的第一绝缘层。去除暴露的牺牲栅极以形成开口，随后在开口中形成镶嵌栅极。封盖层形成在栅极的顶部，并且在暴露的第一导电层上形成第二导电层。在硅衬底上形成第二绝缘层，通过蚀刻第二绝缘层形成露出第二导电层的位线接触。

29. 发明授权

US06844233B2 Semiconductor memory device and fabrication method thereof using damascene gate and epitaxial growth 失效
标题翻译：半导体存储器件及其制造方法使用镶嵌栅极和外延生长
公开(公告)号：US06844233B2
公开(公告)日：2005-01-18
申请号：US10456087
申请日：2003-06-06
申请人： Du-Heon Song
发明人： Du-Heon Song
IPC分类号： H01L29/423 , H01L21/285 , H01L21/3205 , H01L21/336 , H01L21/60 , H01L21/768 , H01L21/8239 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/49 , H01L29/76 , H01L29/78
CPC分类号： H01L21/76897 , H01L21/28525 , H01L21/76885 , H01L21/76895 , H01L27/10855 , H01L27/10888
摘要： A semiconductor memory device and fabrication method of same includes the processes of forming sacrifice gates on a silicon substrate with the sacrifice gates apart from each other. A first conductive layer is formed on an exposed portion of the silicon substrate between the sacrifice gates and a first inter-insulation layer is formed that exposes the first conductive layer and the sacrifice gates. The exposed sacrifice gates are removed to form openings and damascene gates are subsequently formed in the openings. Capping layers are formed on the top of the gates and a second conductive layer is formed on the exposed first conductive layer. A second inter-insulation layer is formed on the silicon substrate, and bit line contacts that expose the second conductive layer are formed by etching the second inter-insulation layer.
摘要翻译：半导体存储器件及其制造方法包括在牺牲栅彼此分开的情况下在硅衬底上形成牺牲栅的工艺。在牺牲栅之间的硅衬底的暴露部分上形成第一导电层，并且形成暴露第一导电层和牺牲栅的第一绝缘层。去除暴露的牺牲栅极以形成开口，随后在开口中形成镶嵌栅极。封盖层形成在栅极的顶部，并且在暴露的第一导电层上形成第二导电层。在硅衬底上形成第二绝缘层，通过蚀刻第二绝缘层形成露出第二导电层的位线接触。

30. 发明授权

US6090692A Fabrication method for semiconductor memory device 失效
标题翻译：半导体存储器件的制造方法
公开(公告)号：US6090692A
公开(公告)日：2000-07-18
申请号：US686676
申请日：1996-07-26
申请人： Du-Heon Song
发明人： Du-Heon Song
IPC分类号： H01L21/28 , H01L21/265 , H01L21/285 , H01L21/306 , H01L21/336 , H01L29/78 , H01L22/336 , H01L21/3205
CPC分类号： H01L21/28044 , H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/6653 , H01L29/6656
摘要： A fabrication method for a semiconductor memory device includes the steps of forming a gate pattern on a semiconductor substrate; forming first and second sidewall spacers at sides of the gate pattern; performing an ion=implantation of a high concentration impurity using the gate pattern and the first and second sidewall spacers as a mask, thereby forming an impurity diffusion region in the semiconductor substrate; performing an ion-implantation of a transition metal on the semiconductor substrate including the gate pattern and the first and second sidewall spacers, and then forming a polysilicide and a silicide by annealing; and removing the second sidewall spacers.
摘要翻译：半导体存储器件的制造方法包括以下步骤：在半导体衬底上形成栅极图案; 在栅极图案的侧面形成第一和第二侧壁间隔物; 使用栅极图案和第一和第二侧壁间隔物进行离子注入高浓度杂质作为掩模，从而在半导体衬底中形成杂质扩散区域; 在包括栅极图案和第一和第二侧壁间隔物的半导体衬底上进行过渡金属的离子注入，然后通过退火形成多硅化物和硅化物; 以及去除所述第二侧壁间隔物。

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