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21. 发明授权

US08952453B2 MOSFET formed on an SOI wafer with a back gate 有权
标题翻译：在具有背栅的SOI晶片上形成MOSFET
公开(公告)号：US08952453B2
公开(公告)日：2015-02-10
申请号：US13580053
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L27/12 , H01L21/84 , H01L29/66 , H01L29/786
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/66545 , H01L29/78648
摘要： The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET is formed on an SOI wafer, comprising: a shallow trench isolation for defining an active region in the semiconductor layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; a channel region in the semiconductor layer and sandwiched by the source region and the drain region; a back gate in the semiconductor substrate; a first dummy gate stack overlapping with a boundary between the semiconductor layer and the shallow trench isolation; and a second dummy gate stack on the shallow trench isolation, wherein the MOSFET further comprises a plurality of conductive vias which are disposed between the gate stack and the first dummy gate stack and electrically connected to the source region and the drain region respectively, and between the first dummy gate stack and the second dummy gate stack and electrically connected to the back gate. The MOSFET avoids short circuit between the back gate and the source/drain regions by the dummy gate stacks.
摘要翻译：本申请公开了一种MOSFET及其制造方法。 MOSFET形成在SOI晶片上，包括：用于限定半导体层中的有源区的浅沟槽隔离; 半导体层上的栅极堆叠; 栅极堆叠的两侧的半导体层中的源极区域和漏极区域; 半导体层中的沟道区，被源极区和漏极区夹持; 半导体衬底中的背栅; 与半导体层和浅沟槽隔离之间的边界重叠的第一虚拟栅极堆叠; 以及在浅沟槽隔离上的第二虚拟栅极堆叠，其中所述MOSFET还包括多个导电通孔，所述多个导电通孔设置在所述栅极堆叠和所述第一伪栅极堆叠之间，并分别电连接到所述源极区域和所述漏极区域之间，以及第一虚拟栅极堆叠和第二虚拟栅极堆叠并且电连接到背栅极。 MOSFET通过虚拟栅极堆叠避免了背栅极和源极/漏极区域之间的短路。

22. 发明授权

US08928089B2 Semiconductor structure and method for forming the same 有权
标题翻译：半导体结构及其形成方法
公开(公告)号：US08928089B2
公开(公告)日：2015-01-06
申请号：US13201827
申请日：2011-02-24
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/70 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： A semiconductor structure and a method for forming the same are provided. The structure comprises a semiconductor substrate (100) with an nMOSFET region (102) and a pMOSFET region (104) on it. An nMOSFET structure and a pMOSFET structure are formed in the nMOSFET region (102) and the pMOSFET region (104), respectively. The nMOSFET structure comprises a first channel region (182) formed in the nMOSFET region (102) and a first gate stack formed in the first channel region (182). The nMOSFET structure is covered with a compressive-stressed material layer (130) to apply a tensile stress to the first channel region (182). The pMOSFET structure comprises a second channel region (184) formed in the pMOSFET region (104) and a second gate stack formed in the second channel region (184). The pMOSFET structure is covered with a tensile-stressed material layer (140) to apply a compressive stress to the second channel region (184).
摘要翻译：提供半导体结构及其形成方法。该结构包括其上具有nMOSFET区域（102）和pMOSFET区域（104）的半导体衬底（100）。 nMOSFET结构和pMOSFET结构分别形成在nMOSFET区域（102）和pMOSFET区域（104）中。 nMOSFET结构包括形成在nMOSFET区域（102）中的第一沟道区（182）和形成在第一沟道区（182）中的第一栅叠层。 nMOSFET结构用压应力材料层（130）覆盖，以向第一沟道区域（182）施加拉伸应力。 pMOSFET结构包括形成在pMOSFET区域（104）中的第二沟道区（184）和形成在第二沟道区（184）中的第二栅叠层。 pMOSFET结构被拉伸应力材料层（140）覆盖，以向第二通道区域（184）施加压缩应力。

23. 发明授权

US08815698B2 Well region formation method and semiconductor base 有权
标题翻译：井区形成方法和半导体基础
公开(公告)号：US08815698B2
公开(公告)日：2014-08-26
申请号：US13381636
申请日：2011-07-26
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L27/04 , H01L21/76 , H01L21/8238 , H01L29/16 , H01L21/8234 , H01L29/66
CPC分类号： H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L29/1608 , H01L29/161 , H01L29/66651
摘要： A well region formation method and a semiconductor base in the field of semiconductor technology are provided. A method comprises: forming isolation regions in a semiconductor substrate to isolate active regions; selecting at least one of the active regions, and forming a first well region in the selected active region; forming a mask to cover the selected active region, and etching the rest of the active regions, so as to form grooves; and growing a semiconductor material by epitaxy to fill the grooves. Another method comprises: forming isolation regions in a semiconductor substrate for isolating active regions; forming well regions in the active regions; etching the active regions to form grooves, such that the grooves have a depth less than or equal to a depth of the well regions; and growing a semiconductor material by epitaxy to fill the grooves.
摘要翻译：提供了半导体技术领域中的阱区形成方法和半导体基底。一种方法包括：在半导体衬底中形成隔离区以隔离有源区; 选择所述有源区域中的至少一个，以及在所选择的有源区域中形成第一阱区域; 形成掩模以覆盖所选择的有源区，并蚀刻其余的有源区，以便形成沟槽; 并通过外延生长半导体材料以填充凹槽。另一种方法包括：在半导体衬底中形成用于隔离有源区的隔离区; 在活跃区域形成井区; 蚀刻有源区以形成凹槽，使得凹槽具有小于或等于阱区深度的深度; 并通过外延生长半导体材料以填充凹槽。

24. 发明申请

US20140197410A1 Semiconductor Structure and Method for Manufacturing the Same 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20140197410A1
公开(公告)日：2014-07-17
申请号：US13697096
申请日：2012-05-17
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/78 , H01L29/66 , H01L29/04
CPC分类号： H01L29/78 , H01L21/76283 , H01L29/04 , H01L29/66477 , H01L29/66772 , H01L29/7843 , H01L29/7848 , H01L29/78603 , H01L29/78618 , H01L29/78696
摘要： The present invention provides a method for manufacturing a semiconductor structure. The method comprises: providing an SOI substrate and forming a gate structure on said SOI substrate; etching a SOI layer and a BOX layer of the SOI substrate on both sides of the gate structure to form a trench exposing the BOX layer, said trench partially entering into the BOX layer; forming a stressed layer that fills up a part of said trench; forming a semiconductor layer covering the stressed layer in the trench. Correspondingly, the present invention also provides a semiconductor structure formed by the above method. In the semiconductor structure and the method for manufacturing the same according to the present invention, a trench is formed on an ultrathin SOI substrate, first filled with a stressed layer, and then filled with a semiconductor material to be ready for forming a source/drain region. The stressed layer provides a favorable stress to the channel of the semiconductor device, thus facilitating improving the performance of the semiconductor device.
摘要翻译：本发明提供一种半导体结构的制造方法。该方法包括：提供SOI衬底并在所述SOI衬底上形成栅极结构; 在栅极结构的两侧蚀刻SOI衬底的SOI层和BOX层，以形成露出BOX层的沟槽，所述沟槽部分地进入BOX层; 形成填充所述沟槽的一部分的应力层; 形成覆盖沟槽中的应力层的半导体层。相应地，本发明还提供了通过上述方法形成的半导体结构。在根据本发明的半导体结构及其制造方法中，在超薄SOI衬底上形成沟槽，首先填充有应力层，然后填充半导体材料以准备形成源极/漏极地区。应力层对半导体器件的通道提供有利的应力，从而有助于提高半导体器件的性能。

25. 发明授权

US08729661B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08729661B2
公开(公告)日：2014-05-20
申请号：US13379533
申请日：2011-04-25
申请人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
IPC分类号： H01L21/70
CPC分类号： H01L21/02647 , H01L21/02639 , H01L21/76229
摘要： A semiconductor structure and a method for manufacturing the same are disclosed. The method comprises: disposing a first dielectric material layer on a first semiconductor layer and defining openings in the first dielectric material layer; epitaxially growing a second semiconductor layer on the first semiconductor layer via the openings defined in the first dielectric material layer, wherein the second semiconductor layer and the first semiconductor layer comprise different materials from each other; and forming plugs of a second dielectric material in the second semiconductor layer at positions where the openings are defined in the first dielectric material layer and also at middle positions between adjacent openings. According to embodiments of the disclosure, defects occurring during the heteroepitaxial growth can be effectively suppressed.
摘要翻译：公开了一种半导体结构及其制造方法。该方法包括：在第一半导体层上设置第一介电材料层并在第一介电材料层中限定开口; 通过限定在第一介电材料层中的开口在第一半导体层上外延生长第二半导体层，其中第二半导体层和第一半导体层包括彼此不同的材料; 以及在所述第二半导体层中形成所述第一介电材料层中所述开口的位置以及在相邻开口之间的中间位置处形成第二电介质材料的插塞。根据本公开的实施例，可以有效地抑制在异质外延生长期间发生的缺陷。

26. 发明授权

US08729638B2 Method for making FINFETs and semiconductor structures formed therefrom 有权
标题翻译：制造FINFET和由其形成的半导体结构的方法
公开(公告)号：US08729638B2
公开(公告)日：2014-05-20
申请号：US13696071
申请日：2011-11-30
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7856 , H01L29/66795 , H01L29/7848 , H01L29/7851
摘要： A method for making FinFETs and semiconductor structures formed therefrom is disclosed, comprising: providing a SiGe layer on a Si semiconductor substrate and a Si layer on the SiGe layer, wherein the lattice constant of the SiGe layer matches that of the substrate; patterning the Si layer and the SiGe layer to form a Fin structure; forming a gate stack on top and both sides of the Fin structure and a spacer surrounding the gate stack; removing a portion of the Si layer which is outside the spacer with the spacer as a mask, while keeping a portion of the Si layer which is inside the spacer; removing a portion of the SiGe layer which is kept after the patterning, to form a void; forming an insulator in the void; and epitaxially growing stressed source and drain regions on both sides of the Fin structure and the insulator.
摘要翻译：公开了一种用于制造FinFET和由其形成的半导体结构的方法，包括：在Si半导体衬底上提供SiGe层和SiGe层上的Si层，其中SiGe层的晶格常数与衬底的晶格常数相匹配; 图案化Si层和SiGe层以形成Fin结构; 在Fin结构的顶部和两侧上形成栅极堆叠以及围绕栅极堆叠的间隔物; 在间隔物作为掩模的同时，除去间隔物外部的Si层的一部分，同时保持间隔物内部的Si层的一部分; 去除在图案化之后保留的SiGe层的一部分，以形成空隙; 在空隙中形成绝缘体; 并在鳍结构和绝缘体的两侧外延生长应力源极和漏极区。

27. 发明授权

US08710556B2 Semiconductor device comprising a Fin and method for manufacturing the same 有权
标题翻译：包括Fin的半导体器件及其制造方法
公开(公告)号：US08710556B2
公开(公告)日：2014-04-29
申请号：US12937652
申请日：2010-06-25
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qiagqing Liang
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qiagqing Liang
IPC分类号： H01L29/76 , H01L27/12 , H01L21/336
CPC分类号： H01L29/66636 , H01L29/66795 , H01L29/66803 , H01L29/7848 , H01L29/785
摘要： The present application discloses a semiconductor device comprising a fin of semiconductive material formed from a semiconductor layer over a semiconductor substrate and having two opposing sides perpendicular to the main surface of the semiconductor substrate; a source region and a drain region provided in the semiconductor substrate adjacent to two ends of the fin and being bridged by the fin; a channel region provided at the central portion of the fin; and a stack of gate dielectric and gate conductor provided at one side of the fin, where the gate conductor is isolated from the channel region by the gate dielectric, and wherein the stack of gate dielectric and gate conductor extends away from the one side of the fin in a direction parallel to the main surface of the semiconductor substrate, and insulated from the semiconductor substrate by an insulating layer. The semiconductor device has an improved short channel effect and a reduced parasitic capacitance and resistance, which contributes to an improved electrical property and facilitates scaling down of the transistor.
摘要翻译：本申请公开了一种半导体器件，其包括由半导体衬底上的半导体层形成并具有垂直于半导体衬底的主表面的两个相对侧的半导体材料的鳍; 源极区域和漏极区域，设置在所述半导体衬底中，邻近所述鳍片的两端并被所述鳍片桥接; 设置在所述翅片的中央部的通道区域; 以及设置在鳍的一侧的栅极电介质和栅极导体的堆叠，其中栅极导体通过栅极电介质与沟道区隔离，并且其中栅极电介质和栅极导体的堆叠远离翅片在平行于半导体衬底的主表面的方向上，并且通过绝缘层与半导体衬底绝缘。半导体器件具有改善的短沟道效应和减小的寄生电容和电阻，这有助于改善电性能并且有助于晶体管的缩小。

28. 发明授权

US08658507B2 MOSFET structure and method of fabricating the same using replacement channel layer 有权
标题翻译： MOSFET结构及其制造方法采用替代沟道层
公开(公告)号：US08658507B2
公开(公告)日：2014-02-25
申请号：US12990714
申请日：2010-06-24
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qingqing Liang
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qingqing Liang
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L29/1054 , H01L29/66583 , H01L29/66636 , H01L29/66651 , H01L29/7834 , H01L29/7848
摘要： There is provided a MOSFET structure and a method of fabricating the same. The method includes: providing a semiconductor substrate; forming a dummy gate on the semiconductor substrate; forming source/drain regions; selectively etching the dummy gate to a position where a channel is to be formed; and epitaxially growing a channel layer at the position where the channel is to be formed and forming a gate on the channel layer, wherein the channel layer comprises a material of high mobility. Thereby, the channel of the device is replaced with the material of high mobility after the source/drain region is formed, and thus it is possible to suppress the short channel effect and also to improve the device performance.
摘要翻译：提供了一种MOSFET结构及其制造方法。该方法包括：提供半导体衬底; 在半导体衬底上形成虚拟栅极; 形成源/漏区; 选择性地将伪栅极蚀刻到要形成沟道的位置; 并且在通道的位置上外延生长沟道层，并在沟道层上形成栅极，其中沟道层包括高迁移率的材料。因此，在形成源极/漏极区域之后，器件的沟道被高迁移率的材料代替，从而可以抑制短沟道效应并且还能够提高器件性能。

29. 发明授权

US08541280B2 Semiconductor structure and method for manufacturing the same 有权
公开(公告)号：US08541280B2
公开(公告)日：2013-09-24
申请号：US13380654
申请日：2011-04-18
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/28518 , H01L21/28525 , H01L21/76805 , H01L21/823425 , H01L21/823814 , H01L21/823871 , H01L23/485 , H01L29/41725 , H01L29/41783 , H01L29/517 , H01L29/518 , H01L29/66628 , H01L29/66636 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for manufacturing a semiconductor structure, comprising the steps of: depositing an interlayer dielectric layer (105) on a semiconductor substrate (101) to cover a source/drain region (102) and a gate stack on the semiconductor substrate (101); etching the interlayer dielectric layer and the source/drain region, so as to form a contact hole (110) extending into the source/drain region; conformally forming an amorphous layer (111) on an exposed part of the source/drain region; forming a metal silicide layer (113) on a surface of the amorphous layer (111); and filling the contact hole (110) with a contact metal (114). Correspondingly, the present invention further provides a semiconductor structure. The present invention etches the source/drain region so that the exposed part comprises the bottom and a sidewall, thereby expanding the contact area between the contact metal in the contact hole and the source/drain region, and reducing the contact resistance. The present invention effectively eliminates EOR defects caused by the amorphous ion implantation by forming an amorphous substance by a selective deposition.

30. 发明授权

US08441045B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08441045B2
公开(公告)日：2013-05-14
申请号：US13378206
申请日：2011-02-27
申请人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L27/085 , H01L29/84 , H01L29/80 , H01L31/112 , H01L29/04
CPC分类号： H01L29/165 , H01L21/30608 , H01L29/1054 , H01L29/1083 , H01L29/517 , H01L29/6653 , H01L29/66553 , H01L29/66583 , H01L29/6659 , H01L29/66651 , H01L29/7834 , H01L29/7849
摘要： The present application discloses a semiconductor device and a method of manufacturing the same. Wherein, the semiconductor device comprises: a semiconductor substrate; a stressor embedded in the semiconductor substrate; a channel region disposed on the stressor; a gate stack disposed on the channel region; a source/drain region disposed on two sides of the channel region and embedded in the semiconductor substrate; wherein, surfaces of the stressor comprise a top wall, a bottom wall, and side walls, the side walls comprising a first side wall and a second side wall, the first side wall connecting the top wall and the second side wall, the second side wall connecting the first side wall and the bottom wall, the angle between the first side wall and the second side wall being less than 180°, and the first sidewall and the second side wall being roughly symmetrical with respect to a plane parallel to the semiconductor substrate. Embodiments of the present invention are applicable to the stress engineering technology in the semiconductor device manufacturing.
摘要翻译：本申请公开了一种半导体器件及其制造方法。其中，所述半导体器件包括：半导体衬底; 嵌入在半导体衬底中的应力器; 设置在所述应力器上的通道区域; 设置在通道区域上的栅极堆叠; 源极/漏极区域，设置在沟道区域的两侧并且嵌入在半导体衬底中; 其中，所述应力器的表面包括顶壁，底壁和侧壁，所述侧壁包括第一侧壁和第二侧壁，所述第一侧壁连接所述顶壁和所述第二侧壁，所述第二侧连接第一侧壁和底壁的壁，第一侧壁和第二侧壁之间的角度小于180°，第一侧壁和第二侧壁相对于平行于半导体的平面大致对称基质。本发明的实施例可应用于半导体器件制造中的应力工程技术。

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