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21. 发明授权

US06670275B2 Method of rounding a topcorner of trench 有权
标题翻译：四舍五入的方法
公开(公告)号：US06670275B2
公开(公告)日：2003-12-30
申请号：US10158039
申请日：2002-05-29
申请人： Chun-Hung Lee , Shiuh-Sheng Yu , Chia-Chi Chung
发明人： Chun-Hung Lee , Shiuh-Sheng Yu , Chia-Chi Chung
IPC分类号： H01L21311
CPC分类号： H01L21/76232 , H01L21/3065 , H01L21/3083 , H01L21/31116 , H01L21/3145 , H01L21/31612 , H01L21/3185
摘要： A method for pulling back SiN to increase rounding effect in a shallow trench isolation process, includes the steps of preparing a substrate of Si and forming a SiO2 layer on the substrate, forming a Si3N4 layer on the SiO2 layer, defining Si3N4 trenches by plasma etching, etching the remaining Si3N4 with SF6/HBr gas, etching SiO2 layer to form a platform and enhance the rounding of the platform, etching the substrate to have a third shallow trench and a reinforced platform, filling the third shallow trench with oxide, planarizing the filled oxide using chemical mechanical polishing, and removing the Si3N4 layer, wherein after the removal of the Si3N4 layer, multiple cleaning processes are performed.
摘要翻译：在浅沟槽隔离工艺中拉回SiN以增加圆化效应的方法包括以下步骤：制备Si衬底并在衬底上形成SiO2层，在SiO2层上形成Si3N4层，通过等离子体蚀刻法形成Si3N4沟槽用SF6 / HBr气体蚀刻剩余的Si3N4，蚀刻SiO 2层形成平台，增强平台的四舍五入，蚀刻基板以形成第三浅沟槽和加固平台，用氧化物填充第三浅沟槽，平面化使用化学机械抛光的填充氧化物，以及除去Si 3 N 4层，其中在除去Si 3 N 4层之后，进行多次清洁处理。

22. 发明申请

US20100096683A1 Structure of semiconductor device 有权
标题翻译：半导体器件的结构
公开(公告)号：US20100096683A1
公开(公告)日：2010-04-22
申请号：US12288632
申请日：2008-10-21
申请人： Shin-Chang Tsai , Hsin-Fang Su , Chun-Hung Lee
发明人： Shin-Chang Tsai , Hsin-Fang Su , Chun-Hung Lee
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L29/4234
摘要： A structure of a semiconductor device including a substrate and a patterned layer is provided. The patterned layer being patterned to have an open area and a dense area is disposed on the substrate. The patterned layer includes, in the dense area, a first pattern adjacent to the open area and a second pattern. The first pattern has a first bottom. The second pattern has a second bottom width. The bottom of the first pattern includes a recess facing the open area, so that the first bottom width is close to the second bottom width.
摘要翻译：提供了包括基板和图案化层的半导体器件的结构。被图案化以具有开放区域和致密区域的图案层设置在基板上。图案化层在密集区域中包括与开放区域相邻的第一图案和第二图案。第一个模式有第一个底部。第二图案具有第二底部宽度。第一图案的底部包括面向开口区域的凹部，使得第一底部宽度接近第二底部宽度。

23. 发明申请

US20080286884A1 METHOD FOR IN-SITU REPAIRING PLASMA DAMAGE AND METHOD FOR FABRICATING TRANSISTOR DEVICE 审中-公开
标题翻译：用于现场修复等离子体损伤的方法和制造晶体管器件的方法
公开(公告)号：US20080286884A1
公开(公告)日：2008-11-20
申请号：US11750732
申请日：2007-05-18
申请人： Hsin-Fang Su , Shih-Chang Tsai , Chun-Hung Lee
发明人： Hsin-Fang Su , Shih-Chang Tsai , Chun-Hung Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/0206 , H01L21/3065 , H01L29/6659 , H01L29/66636 , H01L29/7834
摘要： A method for in-situ repairing plasma damage, suitable for a substrate, is provided. A component is formed on the substrate. The formation steps of the component include a main etching process containing plasma. The method involves performing a soft plasma etching process in the apparatus of the main etching process containing plasma to remove a portion of the substrate. The soft plasma etching process is less than 30% of the power used in the main etching process.
摘要翻译：提供了一种用于原位修复等离子体损伤的方法，适用于基底。在基板上形成部件。组分的形成步骤包括含有等离子体的主蚀刻工艺。该方法包括在包含等离子体的主蚀刻工艺的装置中执行软等离子体蚀刻工艺以去除衬底的一部分。软等离子体蚀刻工艺小于主蚀刻工艺中使用的功率的30％。

24. 发明授权

US07331809B2 Computer system with fixing module for riser card thereof 有权
标题翻译：具有用于其转接卡的固定模块的计算机系统
公开(公告)号：US07331809B2
公开(公告)日：2008-02-19
申请号：US11384283
申请日：2006-03-21
申请人： Chun-Hung Lee , Shih-Tsung Chen
发明人： Chun-Hung Lee , Shih-Tsung Chen
IPC分类号： H01R13/73
CPC分类号： H01R12/7011
摘要： A computer system with a fixing module for riser card thereof is provided. By allowing the bottom side of the supporting pillar and the bottom parts of the two opposite sides of the supporting pillar engaging with each other, the riser card is supported by stress from all directions around it. Therefore, enough supporting strength is efficiently provided within a limited space and the riser card is prevented from being bended and having deformation because of the heavy weight.
摘要翻译：提供一种具有用于其转接卡的固定模块的计算机系统。通过允许支撑柱的底侧和支撑柱的两个相对侧的底部彼此接合，提升卡由围绕其的各个方向的应力支撑。因此，在有限的空间内有效地提供足够的支撑强度，并且由于重量较重，防止了转接卡片弯曲并变形。

25. 发明申请

US20070224870A1 COMPUTER SYSTEM WITH FIXING MODULE FOR RISER CARD THEREOF 有权
标题翻译：具有固定模块的计算机系统
公开(公告)号：US20070224870A1
公开(公告)日：2007-09-27
申请号：US11384283
申请日：2006-03-21
申请人： Chun-Hung Lee , Shih-Tsung Chen
发明人： Chun-Hung Lee , Shih-Tsung Chen
IPC分类号： H01R13/62
CPC分类号： H01R12/7011
摘要： A computer system with a fixing module for riser card thereof is provided. By allowing the bottom side of the supporting pillar and the bottom parts of the two opposite sides of the supporting pillar engaging with each other, the riser card is supported by stress from all directions around it. Therefore, enough supporting strength is efficiently provided within a limited space and the riser card is prevented from being bended and having deformation because of the heavy weight.
摘要翻译：提供一种具有用于其转接卡的固定模块的计算机系统。通过允许支撑柱的底侧和支撑柱的两个相对侧的底部彼此接合，提升卡由围绕其的各个方向的应力支撑。因此，在有限的空间内有效地提供足够的支撑强度，并且由于重量较重，防止了转接卡片弯曲并变形。

26. 发明申请

US20060109638A1 Fastening mechanism for interface card 审中-公开
标题翻译：接口卡紧固机制
公开(公告)号：US20060109638A1
公开(公告)日：2006-05-25
申请号：US11271830
申请日：2005-11-14
申请人： Chun-Hung Lee
发明人： Chun-Hung Lee
IPC分类号： H05K7/14 , H05K7/18
CPC分类号： G06F1/185 , G06F1/184 , G06F1/186 , H05K7/1405
摘要： A fastening mechanism for an interface card is provided. After a tail of a connection plate of the interface card is aligned with a positioning member of the chassis, a latch member pivoted directly/indirectly on the chassis may be swiveled to press the tail of the connection plate toward the positioning member. When a chassis panel of the chassis is installed, the chassis panel can press and secure the latch member. Hence the connection plate can be fastened securely on the chassis without using screws.
摘要翻译：提供了一种用于接口卡的紧固机构。在接口卡的连接板的尾部与底盘的定位构件对准之后，可以将直接/间接地枢转在底盘上的闩锁构件旋转以将连接板的尾部朝向定位构件按压。当安装机箱的机箱面板时，机箱面板可以按压并固定闩锁构件。因此，连接板可以牢固地固定在机架上，而不用螺丝。

27. 发明授权

US06551899B1 Methods of fabricating memory cells for nonvolatile memory devices 有权
标题翻译：制造非易失性存储器件存储单元的方法
公开(公告)号：US06551899B1
公开(公告)日：2003-04-22
申请号：US10172066
申请日：2002-06-14
申请人： Hsu-Sheng Yu , Chun-Hung Lee
发明人： Hsu-Sheng Yu , Chun-Hung Lee
IPC分类号： H01L2176
CPC分类号： H01L27/11517 , H01L27/115
摘要： A method for fabricating nonvolatile memory devices includes forming one or more polyislands, each having a conductive layer and a dielectric layer, on a dielectric layer of a substrate before the creation of control gates on the memory device. In particular, the polyislands may be formed by providing a substrate with a dielectric layer on a surface of the substrate, and forming one or more bar-like structures on the substrate. Each of the bar-like structures includes a conductive layer and a dielectric layer. The bar-like structures are then patterned with compositions having various etching sensitivities for the components of the bar-like structures, to thereby create one or more polyislands before the addition of a second conductive layer over the resulting structure.
摘要翻译：一种用于制造非易失性存储器件的方法包括在存储器件上形成控制栅极之前，在衬底的电介质层上形成一个或多个各自具有导电层和介电层的聚异氰酸酯。特别地，可以通过在衬底的表面上提供具有介电层的衬底并在衬底上形成一个或多个棒状结构来形成多晶体。每个棒状结构都包括导电层和电介质层。然后使用具有针对棒状结构的部件的各种蚀刻敏感性的组合物对条状结构进行构图，从而在所得结构上添加第二导电层之前产生一个或多个聚异氰酸酯。

28. 发明授权

US06350660B1 Process for forming a shallow trench isolation 有权
标题翻译：形成浅沟槽隔离的工艺
公开(公告)号：US06350660B1
公开(公告)日：2002-02-26
申请号：US09840896
申请日：2001-04-25
申请人： Shiuh-Sheng Yu , Chun-Hung Lee , Ming-Chung Liang
发明人： Shiuh-Sheng Yu , Chun-Hung Lee , Ming-Chung Liang
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： First of all, a semiconductor substrate that has a pad oxide layer thereon is provided. Then a nitride layer is formed on the pad oxide layer. Next, a photoresist layer is formed and defined on the nitride layer. Afterward, performing a residual etching process to etch the nitride layer to form an opening and a convex remainder of the nitride layer. The convex remainder of the nitride layer and the semiconductor substrate are then etched by way of using a top rounding process to form the rounding corners on the semiconductor substrate. Subsequently, performing a process for forming the trench to form a trench with the rounding corners. Finally, the follow-up processes are performed to form the shallow trench isolation.
摘要翻译：首先，提供在其上具有衬垫氧化物层的半导体衬底。然后在衬垫氧化物层上形成氮化物层。接着，在氮化物层上形成并限定光致抗蚀剂层。之后，执行残留蚀刻工艺以蚀刻氮化物层以形成氮化物层的开口和凸起的剩余部分。然后通过使用顶部圆化工艺来蚀刻氮化物层和半导体衬底的凸起的剩余部分，以在半导体衬底上形成圆角。随后，执行用于形成沟槽以形成具有圆角的沟槽的工艺。最后，进行后续处理以形成浅沟槽隔离。

29. 发明授权

US09111861B2 Method of fabricating a semiconductor structure with ion-implanted conductive layer 有权
标题翻译：用离子注入导电层制造半导体结构的方法
公开(公告)号：US09111861B2
公开(公告)日：2015-08-18
申请号：US13366669
申请日：2012-02-06
申请人： Tzu-Yen Hsieh , Ming-Ching Chang , Chia-Wei Chang , Chao-Cheng Chen , Chun-Hung Lee , Dai-Lin Wu
发明人： Tzu-Yen Hsieh , Ming-Ching Chang , Chia-Wei Chang , Chao-Cheng Chen , Chun-Hung Lee , Dai-Lin Wu
IPC分类号： H01L21/266 , H01L21/28 , H01L21/033 , H01L21/3213 , H01L21/265
CPC分类号： H01L21/3215 , H01L21/0338 , H01L21/26506 , H01L21/266 , H01L21/28026 , H01L21/28035 , H01L21/28123 , H01L21/32134 , H01L21/32139
摘要： An embodiment of the current disclosure includes a method of providing a substrate, forming a polysilicon layer over the substrate, forming a first photoresist layer on the polysislicon layer, creating a first pattern on the first photoresist layer, wherein some portions of the polysilicon layer are covered by the first photoresist layer and some portions of the polysilicon layer are not covered by the first photoresist layer, implanting ions into the portions of the polysilicon layer that are not covered by the first photoresist layer, removing the first photoresist layer from the polysilicon layer, forming a second photoresist layer on the polysilicon layer, creating a second pattern on the second photoresist layer, and implanting ions into the portions of the polysilicon layer that are not covered by the second photoresist layer, removing the second photoresist layer from the polysilicon layer, and removing portions of the polysilicon layer using an etchant.
摘要翻译：本公开的实施例包括提供衬底的方法，在衬底上形成多晶硅层，在聚苯乙烯层上形成第一光致抗蚀剂层，在第一光致抗蚀剂层上形成第一图案，其中多晶硅层的一些部分由第一光致抗蚀剂层覆盖，并且多晶硅层的一些部分不被第一光致抗蚀剂层覆盖，将离子注入到未被第一光致抗蚀剂层覆盖的多晶硅层的部分中，从多晶硅层去除第一光致抗蚀剂层在所述多晶硅层上形成第二光致抗蚀剂层，在所述第二光致抗蚀剂层上产生第二图案，以及将离子注入所述多晶硅层的未被所述第二光致抗蚀剂层覆盖的部分，从所述多晶硅层除去所述第二光致抗蚀剂层并且使用蚀刻剂去除多晶硅层的部分。

30. 发明授权

US08124537B2 Method for etching integrated circuit structure 有权
标题翻译：集成电路结构蚀刻方法
公开(公告)号：US08124537B2
公开(公告)日：2012-02-28
申请号：US12029834
申请日：2008-02-12
申请人： Chun-Hung Lee , Chia-Chi Chung , Hsin-Chih Chen , Jeff J. Xu , Neng-Kuo Chen
发明人： Chun-Hung Lee , Chia-Chi Chung , Hsin-Chih Chen , Jeff J. Xu , Neng-Kuo Chen
IPC分类号： H01L21/311 , H01L21/302 , H01L21/461 , B44C1/22 , C03C15/00 , C03C25/68 , C23F1/00
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： A method is disclosed for etching an integrated circuit structure within a trench. A layer to be etched is applied over the structure and within the trench. A CF-based polymer is deposited over the layer to be etched followed by deposition of a capping layer of SiOCl-based polymer. The CF-based polymer reduces the width of the trench to such an extent that little or no SiOCl-based polymer is deposited at the bottom of the trench. An O2 plasma etch is performed to etch through the CF-based polymer at the bottom of the trench. The O2 plasma etch has little effect on the SiOCl-based polymer, the thus the upper surfaces of the structure remain covered with polymer. Thus, these upper surfaces remain fully protected during subsequent etching of the layer to be etched.
摘要翻译：公开了一种用于蚀刻沟槽内的集成电路结构的方法。待蚀刻的层被施加在结构之上和沟槽内。将CF基聚合物沉积在待蚀刻的层上，随后沉积SiOCl基聚合物的覆盖层。基于CF的聚合物将沟槽的宽度减小到在沟槽底部沉积少量或不存在SiOCl基聚合物的程度。执行O2等离子体蚀刻以在沟槽的底部蚀刻通过CF基聚合物。 O2等离子体蚀刻对SiOCl基聚合物几乎没有影响，因此结构的上表面保持被聚合物覆盖。因此，在随后蚀刻待蚀刻的层期间，这些上表面保持完全保护。

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