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21. 发明申请

US20110154000A1 Adaptive optimized compare-exchange operation 有权
标题翻译：自适应优化比较交换操作
公开(公告)号：US20110154000A1
公开(公告)日：2011-06-23
申请号：US12653800
申请日：2009-12-18
申请人： Joshua B. Fryman , Andrew Thomas Forsyth , Edward Grochowski
发明人： Joshua B. Fryman , Andrew Thomas Forsyth , Edward Grochowski
IPC分类号： G06F9/30 , G06F12/08
CPC分类号： G06F9/3004 , G06F9/30087
摘要： A technique to perform a fast compare-exchange operation is disclosed. More specifically, a machine-readable medium, processor, and system are described that implement a fast compare-exchange operation as well as a cache line mark operation that enables the fast compare-exchange operation.
摘要翻译：公开了一种执行快速比较交换操作的技术。更具体地，描述了实现快速比较交换操作以及启用快速比较交换操作的高速缓存行标记操作的机器可读介质，处理器和系统。

22. 发明授权

US07395304B2 Method and apparatus for performing single-cycle addition or subtraction and comparison in redundant form arithmetic 有权
标题翻译：用于在冗余形式算术中执行单周期加法或减法和比较的方法和装置
公开(公告)号：US07395304B2
公开(公告)日：2008-07-01
申请号：US10890848
申请日：2004-07-13
申请人： Bharat Bhushan , Vinod Sharma , Edward Grochowski , John Crawford
发明人： Bharat Bhushan , Vinod Sharma , Edward Grochowski , John Crawford
IPC分类号： G06F7/04
CPC分类号： G06F7/5095 , G06F7/02 , G06F7/4824
摘要： A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in a redundant form to also subtract numbers received in redundant form, including numbers received from a bypass circuit. A non-propagative comparator circuit is then used to compare a given value with a result from the arithmetic circuit to determine if the result is equal to the given value. All of the operations described above can be accomplished without propagating carry signals throughout the circuitry.The method includes generating a complemented redundant form of at least one number supplied to the arithmetic circuit in redundant form. It also includes providing adjustment input to the arithmetic circuit to augment a result produced through the arithmetic circuit. This adjustment causes the arithmetic circuit to generate a valid outcome in redundant form as a result of a subtraction operation if the arithmetic operation is subtraction. Then the result is compared to a given value using a non-propagative comparator to determine equality or inequality of the result to the given value.
摘要翻译：公开了一种方法和装置，其使用运算电路来添加以冗余形式表示的数字，还可以减去以冗余形式接收的数字，包括从旁路电路接收的数字。然后使用非传播比较器电路将给定值与运算电路的结果进行比较，以确定结果是否等于给定值。可以在整个电路中不传播进位信号来实现上述所有操作。该方法包括以冗余的形式生成提供给运算电路的至少一个数的补码冗余形式。它还包括向算术电路提供调整输入以增加通过运算电路产生的结果。如果算术运算是减法，则该调整使得运算电路作为减法运算的结果以冗余形式产生有效结果。然后将结果与使用非传播比较器的给定值进行比较，以确定结果与给定值的相等或不等式。

23. 发明申请

US20050102494A1 Method and apparatus for register stack implementation using micro-operations 审中-公开
标题翻译：使用微操作的寄存器堆栈实现的方法和装置
公开(公告)号：US20050102494A1
公开(公告)日：2005-05-12
申请号：US10712618
申请日：2003-11-12
申请人： Edward Grochowski , Jeffrey Rupley , Partha Kundu
发明人： Edward Grochowski , Jeffrey Rupley , Partha Kundu
IPC分类号： G06F9/00 , G06F9/318
CPC分类号： G06F9/3017
摘要： Disclosed are embodiments of an apparatus, system, and method for implementing a register stack using micro-operations. A register stack engine generates a plurality of micro-operations to implement a memory operation in support of register windowing, such as spill or fill to/from a backing store. These micro-operations are inserted into an execution pipeline along with other micro-operations not related to register stack operation.
摘要翻译：公开了用于使用微操作来实现寄存器堆栈的装置，系统和方法的实施例。寄存器堆栈引擎产生多个微操作以实现支持寄存器窗口的存储器操作，诸如从后备存储器溢出或填充到后备存储器。这些微操作与其他与寄存器堆栈操作无关的微操作被插入到执行流水线中。

24. 发明申请

US20130117531A1 METHOD, SYSTEM, AND APPARATUS FOR PAGE SIZING EXTENSION 审中-公开
公开(公告)号：US20130117531A1
公开(公告)日：2013-05-09
申请号：US13722485
申请日：2012-12-20
申请人： Edward Grochowski , Julio Gago , Roger Gramunt , Roger Espasa , Rolf Kassa
发明人： Edward Grochowski , Julio Gago , Roger Gramunt , Roger Espasa , Rolf Kassa
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F12/0864 , G06F12/1027 , G06F12/109 , G06F12/145 , G06F2212/152 , G06F2212/6032 , G06F2212/652 , G06F2212/657 , G06F2212/68
摘要： A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.

25. 发明授权

US07622961B2 Method and apparatus for late timing transition detection 有权
标题翻译：用于后期定时转换检测的方法和装置
公开(公告)号：US07622961B2
公开(公告)日：2009-11-24
申请号：US11234548
申请日：2005-09-23
申请人： Edward Grochowski , Chris Wilkerson , Shih-Lien L. Lu , Murali Annavaram
发明人： Edward Grochowski , Chris Wilkerson , Shih-Lien L. Lu , Murali Annavaram
IPC分类号： H03K5/19
CPC分类号： G01R31/31922 , G01R31/31726 , H03K5/1534 , H04L7/0083 , H04L7/033
摘要： Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.
摘要翻译：两个锁存器在时钟信号的转变时存储数据信号的状态。比较逻辑比较两个锁存器的输出，并产生一个信号以指示输出是相等还是不相等。描述和要求保护使用锁存器和比较逻辑的系统。

26. 发明申请

US20070271421A1 Reducing aging effect on memory 审中-公开
标题翻译：减少老化对记忆的影响
公开(公告)号：US20070271421A1
公开(公告)日：2007-11-22
申请号：US11435701
申请日：2006-05-17
申请人： Nam Sung Kim , Shih-Lien L. Lu , Chris Wilkerson , Edward Grochowski
发明人： Nam Sung Kim , Shih-Lien L. Lu , Chris Wilkerson , Edward Grochowski
IPC分类号： G06F13/00
CPC分类号： G11C11/412
摘要： Methods and apparatus to reduce aging effect on memory are described. In one embodiment, a modified version of data is stored in a portion of a storage unit during a first time period.
摘要翻译：描述了减少老化对记忆效应的方法和装置。在一个实施例中，数据的修改版本在第一时间段期间存储在存储单元的一部分中。

27. 发明申请

US20070225959A1 Mechanism for estimating and controlling di/dt-induced power supply voltage variations 有权
公开(公告)号：US20070225959A1
公开(公告)日：2007-09-27
申请号：US11804860
申请日：2007-05-21
申请人： Edward Grochowski , David Sager , Vivek Tiwari , Ian Young , David Ayers
发明人： Edward Grochowski , David Sager , Vivek Tiwari , Ian Young , David Ayers
IPC分类号： G06F17/50
CPC分类号： G06F1/3296 , G06F1/26 , G06F1/3203 , G06F17/5036 , G06F2217/78 , Y02D10/172
摘要： A system for delivering power to a device in a specified voltage range is disclosed. The system includes a power delivery network, characterized by a response function, to deliver power to the device. A current computation unit stores values representing a sequence of current amplitudes drawn by the device on successive clock cycles, and provides them to a current to voltage computation unit. The current to voltage computation unit filters the current amplitudes according to coefficients derived from the response function to provide an estimate of the voltage seen by the device. Operation of the device is adjusted if the estimated voltage falls outside the specified range.

28. 发明申请

US20050081017A1 Method and apparatus for predication using micro-operations 有权
标题翻译：使用微操作进行预测的方法和装置
公开(公告)号：US20050081017A1
公开(公告)日：2005-04-14
申请号：US10685654
申请日：2003-10-14
申请人： Jeffrey Rupley , Edward Brekelbaum , Edward Grochowski , Bryan Black
发明人： Jeffrey Rupley , Edward Brekelbaum , Edward Grochowski , Bryan Black
IPC分类号： G06F9/30 , G06F9/312 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/30072 , G06F9/30145 , G06F9/30167 , G06F9/3017 , G06F9/3836 , G06F9/384
摘要： Disclosed are an apparatus, system, and method for implementing predicated instructions using micro-operations. A micro-code engine receives an instruction, decomposes the instruction, and generates a plurality of micro-operations to implement the instruction. Each of the decomposed micro-operations indicates a single destination register. For predicated instructions, the decomposed micro-operations include “conditional move” micro-operations to select between two potential output values. Except in the case that one of the potential output values is a constant, the decomposed micro-operations for a predicated instruction also include an append instruction that saves the incoming value of a destination register in a temporary variable. For at least one embodiment, the qualifying predicate for a predicated instruction is appended to the incoming value stored in the temporary register.
摘要翻译：公开了一种用于使用微操作来实现预定指令的装置，系统和方法。微码引擎接收指令，分解指令，并产生多个微操作来实现该指令。每个分解的微操作指示单个目的地寄存器。对于预测指令，分解的微操作包括在两个潜在输出值之间选择的“条件移动”微操作。除了在一个潜在输出值是常数的情况下，用于预测指令的分解的微操作还包括将目的地寄存器的输入值保存在临时变量中的附加指令。对于至少一个实施例，用于预测指令的限定谓词附加到存储在临时寄存器中的输入值。

29. 发明授权

US06839814B2 Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors 有权
标题翻译：用于保护高性能微处理器中的1-hot和2-hot矢量标签的电路和方法
公开(公告)号：US06839814B2
公开(公告)日：2005-01-04
申请号：US10726492
申请日：2003-12-04
申请人： Nhon Quach , John Crawford , Greg S. Mathews , Edward Grochowski , Chakravarthy Kosaraju
发明人： Nhon Quach , John Crawford , Greg S. Mathews , Edward Grochowski , Chakravarthy Kosaraju
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0891
摘要： The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory including an input conversion circuit to receive a 1-hot vector and to convert the 1-hot vector to a 2-hot vector. The tag array memory also including a memory array coupled to the input conversion circuit, the memory array to store the 2-hot vector; and an output conversion circuit coupled to the memory array, the output conversion circuit to receive the 2-hot vector and to convert the 2-hot vector back to the 1-hot vector.
摘要翻译：本发明涉及高度可靠的高性能微处理器的设计，更具体地说涉及使用高速缓存存储器保护方案（例如，1加热有效位方案和2热向量高速缓存方案）的设计。这些保护方案保护缓存中标签阵列中使用的1-hot向量，并设计为提供硬件节省，以更高的速度运行并且易于实现。根据本发明的一个实施例，一种标签阵列存储器，包括一个输入转换电路，用于接收1个热矢量，并将该1个热矢量转换为2个热矢量。标签阵列存储器还包括耦合到输入转换电路的存储器阵列，存储器阵列以存储2-热矢量; 以及耦合到存储器阵列的输出转换电路，所述输出转换电路接收所述2-热矢量并将所述2-热矢量转换回所述1-热矢量。

30. 发明授权

US06675266B2 Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors 有权
标题翻译：用于保护高性能微处理器中的1-hot和2-hot矢量标签的电路和方法
公开(公告)号：US06675266B2
公开(公告)日：2004-01-06
申请号：US09750094
申请日：2000-12-29
申请人： Nhon Quach , John Crawford , Greg S. Mathews , Edward Grochowski , Chakravarthy Kosaraju
发明人： Nhon Quach , John Crawford , Greg S. Mathews , Edward Grochowski , Chakravarthy Kosaraju
IPC分类号： G06F1200
CPC分类号： G06F12/0891
摘要： The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory circuit includes a plurality of memory bit circuits coupled together to form an n-bit memory cell, and a valid bit circuit coupled to the n-bit memory cell, the valid bit circuit being configured to be accessed simultaneously with the plurality of memory bit circuits.
摘要翻译：本发明涉及高度可靠的高性能微处理器的设计，更具体地说涉及使用高速缓存存储器保护方案（例如，1加热有效位方案和2热向量高速缓存方案）的设计。这些保护方案保护缓存中标签阵列中使用的1-hot向量，并且被设计为提供硬件节省，以更高的速度运行并且易于实现。根据本发明的实施例，标签阵列存储电路包括耦合在一起以形成n位存储单元的多个存储器位电路和耦合到n位存储单元的有效位电路，有效位电路被配置为与多个存储器位电路同时访问。

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