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21. 发明授权

US5838609A Integrated semiconductor device having negative resistance formed of MIS switching diode 失效
标题翻译：具有负电阻的集成半导体器件
公开(公告)号：US5838609A
公开(公告)日：1998-11-17
申请号：US925140
申请日：1997-09-08
申请人： Hirotada Kuriyama
发明人： Hirotada Kuriyama
IPC分类号： G11C11/41 , G11C8/16 , G11C11/38 , G11C11/39 , G11C11/56 , H01L27/10 , H01L27/11 , G11C11/00
CPC分类号： G11C11/56 , G11C11/38 , G11C11/39 , G11C8/16 , H01L27/1112 , G11C2211/5614
摘要： A memory cell of an SRAM includes an access transistor, and an MIS switching diode. The access transistor has a drain electrode connected to a bit line of a corresponding column, a source electrode connected to a storage node, and a gate electrode connected to a word line of a corresponding row. The threshold voltage of the access transistor is small than the threshold voltage of a bit line load transistor. The MIS switching diode is connected between the storage node and a second power supply potential node. The switching initiate voltage of the MIS switching diode is greater than the difference between the first potential and the threshold voltage of the bit line load transistor, and smaller than the difference between the first potential and the threshold voltage of the access transistor. Thus, data can be read/written and held accurately.
摘要翻译： SRAM的存储单元包括存取晶体管和MIS开关二极管。存取晶体管具有连接到相应列的位线的漏电极，连接到存储节点的源极和连接到相应行的字线的栅电极。存取晶体管的阈值电压小于位线负载晶体管的阈值电压。 MIS开关二极管连接在存储节点和第二电源电位节点之间。 MIS开关二极管的开关启动电压大于位线负载晶体管的第一电位和阈值电压之间的差，并且小于存取晶体管的第一电位和阈值电压之间的差。因此，可以准确地读取/写入数据。

22. 发明授权

US5550390A Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5550390A
公开(公告)日：1996-08-27
申请号：US453726
申请日：1995-05-30
申请人： Teruhiko Okada , Hirotada Kuriyama , Yoshio Kohno
发明人： Teruhiko Okada , Hirotada Kuriyama , Yoshio Kohno
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8244 , H01L29/786 , H01L29/76 , H01L27/01 , H01L31/036 , H01L31/112
CPC分类号： H01L29/66765 , H01L27/11 , H01L29/78636 , H01L29/78678
摘要： A semiconductor device includes a gate electrode, and a semiconductor layer formed on the main surface of the gate electrode with a gate oxide film therebetween. The semiconductor layer has a channel region opposing the main surface of gate electrode and source/drain regions having the channel region therebetween, and is formed so that the bent angle in the vicinity of the boundaries of the channel region and the source/drain regions is beyond 90.degree.. Thus, the semiconductor layer formed in a thin film transistor has no orthogonal bent, and, therefore the concentration of electric fields is suppressed, improving the performance of the thin film transistor.
摘要翻译：半导体器件包括栅电极和形成在栅电极的主表面上的半导体层，其间具有栅氧化膜。半导体层具有与栅电极的主表面相对的沟道区域和在其间具有沟道区域的源极/漏极区域，并且形成为使沟道区域和源极/漏极区域的边界附近的弯曲角度为超过90度。因此，形成在薄膜晶体管中的半导体层没有正交弯曲，因此抑制了电场的集中，提高了薄膜晶体管的性能。

23. 发明授权

US5517038A Semiconductor device including three-dimensionally disposed logic elements for improving degree of integration 失效
标题翻译：半导体器件包括用于提高集成度的三维布置的逻辑元件
公开(公告)号：US5517038A
公开(公告)日：1996-05-14
申请号：US348211
申请日：1994-11-28
申请人： Shigenobu Maeda , Hirotada Kuriyama
发明人： Shigenobu Maeda , Hirotada Kuriyama
IPC分类号： G11C11/412 , G11C11/418 , G11C11/419 , H01L21/8244 , H01L27/11 , H01L27/108
CPC分类号： H01L27/1108 , G11C11/412 , G11C11/418 , G11C11/419 , Y10S257/903 , Y10S257/904
摘要： Adjacent memory cells has a two-layer structure formed of first layer and second layer. The first layer is provided with driver transistors of the memory cell, access transistors of the memory cell, and driver transistors formed of the memory cell. The second layer is provided with load transistors of the memory cell, load transistors and of the memory cell, and access transistors of the memory cell. The transistors formed in the first layer are of an NMOS type, and the transistors formed in the second layer are of a PMOS type.
摘要翻译：相邻的存储单元具有由第一层和第二层形成的双层结构。第一层设置有存储单元的驱动器晶体管，存储单元的存取晶体管和由存储单元形成的驱动晶体管。第二层设置有存储单元，负载晶体管和存储单元的负载晶体管，以及存储单元的存取晶体管。形成在第一层中的晶体管是NMOS型，并且在第二层中形成的晶体管是PMOS型的。

24. 发明授权

US5341327A Static random access type semiconductor memory device 失效
标题翻译：静态随机存取型半导体存储器件
公开(公告)号：US5341327A
公开(公告)日：1994-08-23
申请号：US859566
申请日：1992-03-27
申请人： Hirotada Kuriyama
发明人： Hirotada Kuriyama
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/78 , H01L29/786 , G11C11/00
CPC分类号： H01L27/1108
摘要： An object of the present invention is to miniaturize a structure of a memory cell in an SRAM. The memory cell in the SRAM includes a pair of access transistors, a pair of driver transistors and a pair of load transistors. The six transistors are thin film transistors. A plurality of thin film transistors are provided on a surface of a silicon substrate, forming a plurality of layers with an interlayer insulating layer interposed therebetween.
摘要翻译：本发明的目的是使SRAM中的存储单元的结构小型化。 SRAM中的存储单元包括一对存取晶体管，一对驱动晶体管和一对负载晶体管。六个晶体管是薄膜晶体管。在硅衬底的表面上设置多个薄膜晶体管，形成多个层，其间夹有层间绝缘层。

25. 发明授权

US06563165B2 Non-volatile semiconductor memory device and method for producing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US06563165B2
公开(公告)日：2003-05-13
申请号：US09199264
申请日：1998-11-25
申请人： Kiyohiko Sakakibara , Hirotada Kuriyama
发明人： Kiyohiko Sakakibara , Hirotada Kuriyama
IPC分类号： A01L29788
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11521 , H01L27/11531 , H01L29/42324
摘要： A non-volatile semiconductor memory device comprising: a semiconductor substrate, memory cells, a region of memory cell array in which said memory cells are arranged in a matrix-like form, a region of peripheral circuit, a connecting region for connecting said region of memory cell array to said region of peripheral circuit, and conductive layers provided closest to said substrate with intervals between each other, wherein said intervals of said conductive layers are substantially equal to each other in said region of memory cell array and said connecting region, whereby when insulating films are formed and planarized after forming said conductive layers, it is possible to restrict producing of seams in the insulating films at stripped portions of the conductive layers.
摘要翻译：一种非易失性半导体存储器件，包括：半导体衬底，存储单元，其中所述存储单元以矩阵状形式布置的存储单元阵列的区域，外围电路的区域，用于连接所述区域的连接区域存储单元阵列到所述外围电路的所述区域，以及最靠近所述衬底设置的导电层，所述导体层之间具有间隔，其中所述导电层的所述间隔在所述存储单元阵列区域和所述连接区域中基本相等，由此当在形成所述导电层之后形成绝缘膜并进行平坦化时，可以限制导电层的剥离部分的绝缘膜中的接缝的产生。

26. 发明授权

US06420751B1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06420751B1
公开(公告)日：2002-07-16
申请号：US09640880
申请日：2000-08-18
申请人： Shigenobu Maeda , Yasuo Yamaguchi , Hirotada Kuriyama , Shigeto Maegawa
发明人： Shigenobu Maeda , Yasuo Yamaguchi , Hirotada Kuriyama , Shigeto Maegawa
IPC分类号： H01L2976
CPC分类号： H01L27/092 , H01L27/10823 , H01L27/10841 , H01L27/1104 , H01L27/1203 , H01L29/66666 , H01L29/7827
摘要： A field effect transistor occupying a small area and a semiconductor device using the same can be obtained. A gate electrode is provided on a substrate on which a source region is provided with a first interlayer insulating film interposed therebetween. The gate electrode is covered with a second interlayer insulating film. A contact hole for exposing a part of the surface of the source region is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A sidewall surface of the contact hole is covered with a gate insulating film. A first semiconductor layer of a first conductivity type is provided on the surface of the source region in contact therewith up to the lower surface of the gate electrode. A channel semiconductor layer is provided on the surface of the first semiconductor layer up to the upper surface of the gate electrode. A second semiconductor layer of a first conductivity type serving as a drain region is provided on the channel semiconductor layer.
摘要翻译：可以获得占据小面积的场效应晶体管和使用其的半导体器件。栅电极设置在基板上，源极区域之间插入有第一层间绝缘膜。栅电极被第二层间绝缘膜覆盖。提供用于暴露源区域的一部分表面的接触孔，以穿透第一层间绝缘膜，栅电极和第二层间绝缘膜。接触孔的侧壁表面被栅极绝缘膜覆盖。第一导电类型的第一半导体层设置在与其接触的源极区域的表面上，直到栅电极的下表面。沟道半导体层设置在第一半导体层的表面上直到栅电极的上表面。在沟道半导体层上设置有用作漏极区的第一导电类型的第二半导体层。

27. 发明授权

US6127209A Semiconductor device and method of manufacturing the same 失效
公开(公告)号：US6127209A
公开(公告)日：2000-10-03
申请号：US295363
申请日：1999-04-21
申请人： Shigenobu Maeda , Yasuo Yamaguchi , Hirotada Kuriyama , Shigeto Maegawa
发明人： Shigenobu Maeda , Yasuo Yamaguchi , Hirotada Kuriyama , Shigeto Maegawa
IPC分类号： H01L21/768 , H01L21/8242 , H01L27/092 , H01L27/10 , H01L27/108 , H01L27/11 , H01L27/12 , H01L29/78 , H01L21/00 , H01L21/8232
CPC分类号： H01L27/092 , H01L27/10823 , H01L27/10841 , H01L27/1104 , H01L27/1203 , H01L29/66666 , H01L29/7827
摘要： A field effect transistor occupying a small area and a semiconductor device using the same can be obtained. A gate electrode is provided on a substrate on which a source region is provided with a first interlayer insulating film interposed therebetween. The gate electrode is covered with a second interlayer insulating film. A contact hole for exposing a part of the surface of the source region is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A sidewall surface of the contact hole is covered with a gate insulating film. A first semiconductor layer of a first conductivity type is provided on the surface of the source region in contact therewith up to the lower surface of the gate electrode. A channel semiconductor layer is provided on the surface of the first semiconductor layer up to the upper surface of the gate electrode. A second semiconductor layer of a first conductivity type serving as a drain region is provided on the channel semiconductor layer.

28. 发明授权

US6030548A SRAM memory device having reduced size 失效
标题翻译：具有减小尺寸的SRAM存储器件
公开(公告)号：US6030548A
公开(公告)日：2000-02-29
申请号：US978002
申请日：1997-11-25
申请人： Hirotada Kuriyama
发明人： Hirotada Kuriyama
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L27/1104 , Y10S257/903
摘要： A semiconductor memory device is provided that can have the memory cell size reduced and electrical imbalance eliminated. This semiconductor memory device has gate electrodes of a driver transistor and a load transistor formed of a first polysilicon layer, and a word line also serving as a gate electrode of an access transistor formed of a different layer of a second polysilicon layer. Therefore, the gate electrodes of the driver transistor and the load transistor can be overlapped with each other in a planar manner with the word line, resulting in reduction in the planar area of the memory cell. In a cell current path, a contact portion other than a bit line contact and a GND contact is not provided. Therefore, electrical imbalance in memory cells is prevented.
摘要翻译：提供了可以使存储单元尺寸减小并消除电不平衡的半导体存储器件。该半导体存储器件具有驱动晶体管的栅电极和由第一多晶硅层形成的负载晶体管，以及还用作由第二多晶硅层的不同层形成的存取晶体管的栅电极的字线。因此，驱动晶体管和负载晶体管的栅电极可以与字线平面地彼此重叠，导致存储单元的平面面积减小。在电池电流路径中，不提供除位线触点和GND触点之外的接触部分。因此，防止了存储器单元中的电不平衡。

29. 发明授权

US5994719A SRAM semiconductor device 失效
标题翻译： SRAM半导体器件
公开(公告)号：US5994719A
公开(公告)日：1999-11-30
申请号：US116245
申请日：1998-07-16
申请人： Hirotada Kuriyama , Masahiro Ishida , Yoshiyuki Ishigaki
发明人： Hirotada Kuriyama , Masahiro Ishida , Yoshiyuki Ishigaki
IPC分类号： H01L27/11 , H01L21/8244 , H01L29/76
CPC分类号： H01L27/1108 , H01L27/11 , Y10S257/903
摘要： The present invention provides an improved static random access memory which can be manufactured into values as designed by photolithography. Second direct contract for connecting active region and ground line for first and second memory cells is provided at a boundary between the first memory cell and second memory cell. Second direct contact is divided into a plurality of portions.
摘要翻译：本发明提供一种改进的静态随机存取存储器，其可以被制造成通过光刻设计的值。在第一存储单元和第二存储单元之间的边界处提供用于连接用于第一和第二存储单元的有源区和接地线的第二直接合同。第二直接接触被分成多个部分。

30. 发明授权

US5818080A Semiconductor memory device including a memory cell region of six transistors 失效
标题翻译：半导体存储器件包括六个晶体管的存储单元区域
公开(公告)号：US5818080A
公开(公告)日：1998-10-06
申请号：US601554
申请日：1996-02-14
申请人： Hirotada Kuriyama
发明人： Hirotada Kuriyama
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/788
CPC分类号： H01L27/1104 , Y10S257/903
摘要： A semiconductor memory device is provided that can have the memory cell size reduced and electrical imbalance eliminated. This semiconductor memory device has gate electrodes of a driver transistor and a load transistor formed of a first polysilicon layer, and a word line also serving as a gate electrode of an access transistor formed of a different layer of a second polysilicon layer. Therefore, the gate electrodes of the driver transistor and the load transistor can be overlapped with each other in a planar manner with the word line, resulting in reduction in the planar area of the memory cell. In a cell current path, a contact portion other than a bit line contact and a GND contact is not provided. Therefore, electrical imbalance in memory cells is prevented.
摘要翻译：提供了可以使存储单元尺寸减小并消除电不平衡的半导体存储器件。该半导体存储器件具有驱动晶体管的栅电极和由第一多晶硅层形成的负载晶体管，以及还用作由第二多晶硅层的不同层形成的存取晶体管的栅电极的字线。因此，驱动晶体管和负载晶体管的栅电极可以与字线平面地彼此重叠，导致存储单元的平面面积减小。在电池电流路径中，不提供除位线触点和GND触点之外的接触部分。因此，防止了存储器单元中的电不平衡。

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