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21. 发明授权

US5272676A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5272676A
公开(公告)日：1993-12-21
申请号：US789018
申请日：1991-11-06
申请人： Shoji Kubono , Hiroshi Sato
发明人： Shoji Kubono , Hiroshi Sato
IPC分类号： G11C5/14 , G11C11/406 , G11C7/00
CPC分类号： G11C11/40626 , G11C11/406 , G11C11/40615 , G11C5/145
摘要： The self-refresh operation of one round of a RAM using dynamic memory cells is accomplished on the basis of the periodic pulses which are formed by an oscillating circuit substantially having no temperature dependency, and the self-refresh period is controlled by a timer circuit using a time constant circuit corresponding to the temperature dependency of the data storage in the memory cells. The operating voltage or boosted output voltage is monitored to switch the circuit operation for generating a plurality kinds of boosted voltages rising sequentially two and three times so that the boosted voltage may be a desired voltage. A control voltage to be fed to the gate of a MOSFET connected between the substrate and the earth potential of the circuit is generated by a dummy substrate voltage generator having a leakage current path varying to follow the fluctuations in a supply voltage.
摘要翻译：基于由基本上没有温度依赖性的振荡电路形成的周期性脉冲来实现使用动态存储单元的一轮RAM的自刷新操作，并且自刷新周期由定时器电路使用对应于存储器单元中的数据存储器的温度依赖性的时间常数电路。监视工作电压或升压输出电压以切换电路操作，以产生依次升高两次和三次的多种升压电压，使得升压电压可以是期望的电压。通过具有随着电源电压的波动而变化的漏电流路径的虚拟衬底电压发生器产生要馈送到连接在衬底和电路的接地电位之间的MOSFET的栅极的控制电压。

22. 发明授权

US06567319B2 Nonvolatile semiconductor memory with controlled supply of boosted voltage 有权
标题翻译：非易失性半导体存储器，具有受控供电的升压电压
公开(公告)号：US06567319B2
公开(公告)日：2003-05-20
申请号：US10171768
申请日：2002-06-17
申请人： Hiroshi Sato , Satoshi Noda , Kiichi Manita , Shoji Kubono , Koji Shigematsu
发明人： Hiroshi Sato , Satoshi Noda , Kiichi Manita , Shoji Kubono , Koji Shigematsu
IPC分类号： G11C1604
CPC分类号： G11C5/145 , G11C16/12 , G11C16/30
摘要： A semiconductor memory is designed to avoid a situation that the program cannot escape from a writing operation, and the writing operation can be promptly finished according to the level of an external source voltage. This semiconductor memory has a voltage detecting circuit for detecting whether a boosted voltage has reached a predetermined potential and a timer capable of counting predetermined time. A control circuit applies the boosted voltage to a selected memory cell when the voltage detecting circuit detects that the boosted voltage has reached the predetermined potential or when it is detected that the predetermined time has elapsed since the start of the boosting operation.
摘要翻译：半导体存储器被设计为避免程序不能从写入操作中逃逸的情况，并且可以根据外部源电压的电平迅速完成写入操作。该半导体存储器具有用于检测升压电压是否达到预定电位的电压检测电路和能够计数预定时间的定时器。当电压检测电路检测到升压电压已经达到预定电位时，或当从升压操作开始经过预定时间时，控制电路将升压电压施加到所选存储单元。

23. 发明授权

US06473321B2 Semiconductor integrated circuit and nonvolatile semiconductor memory 失效
标题翻译：半导体集成电路和非易失性半导体存储器
公开(公告)号：US06473321B2
公开(公告)日：2002-10-29
申请号：US09883237
申请日：2001-06-19
申请人： Jiro Kishimoto , Hiroshi Sato , Satoshi Noda , Tatsuya Ishii , Shoji Kubono , Takashi Ogino
发明人： Jiro Kishimoto , Hiroshi Sato , Satoshi Noda , Tatsuya Ishii , Shoji Kubono , Takashi Ogino
IPC分类号： H02M318
CPC分类号： H02M3/073 , G11C16/30 , H02M2003/075
摘要： For a semiconductor integrated circuit having an internal booster circuit such as a flash memory, voltage booster circuits capable of generating a boosted voltage 10 times or more as high as a relatively low source voltage is to be realized. Charge pumps for carrying out first stage voltage boosting on the basis of a source voltage are configured of parallel capacity type units, and charge pumps for carrying out second stage voltage boosting on the basis of the boosted voltage generated by the first charge pumps are configured of serial capacity type units.
摘要翻译：对于具有诸如闪速存储器的内部升压电路的半导体集成电路，可以实现能够产生相当低的源电压的10倍或更高的升压电压的升压电路。基于源电压进行第一级升压的充电泵由并联容量型单元构成，并且基于由第一电荷泵产生的升压电压进行第二级升压的电荷泵由串口容量型号。

24. 发明授权

US06930924B2 Nonvolatile memory and method of programming the same memory 有权
标题翻译：非易失性存储器和编程相同存储器的方法
公开(公告)号：US06930924B2
公开(公告)日：2005-08-16
申请号：US10404101
申请日：2003-04-02
申请人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
发明人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/12
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/12
摘要： There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases. In the non-volatile memory of the invention comprising the AND type memory array in which a plurality of memory cells are connected in parallel between the local bit lines and local drain lines, the local drain lines are precharged by supplying thereto a comparatively higher voltage from the common drain line side (opposite side of the main bit lines), the main bit lines are selectively precharged by applying thereto the voltage of 0V or a comparatively small voltage depending on the write data and thereafter a drain current is applied only to the selected memory cells to which data is written by applying the write voltage to the word lines in order to implant the hot electrons to the floating gate.
摘要翻译：提供了一种编程非易失性存储器的方法，其可以解决现有闪存的数据写入系统的问题，即位线的负载电容变大，位线达到预定电位所需的时间变为因此，数据写入操作所需的时间变得更长，并且由于存储器阵列的存储器电容越多，存储器阵列的长度越长，位线的数量越多，位线的数量越多，因此功耗也变大。在本发明的非易失性存储器中，包括其中多个存储器单元并联连接在局部位线和局部漏极线之间的AND型存储器阵列，通过向局部漏极线提供相对较高的电压来预充电，公共漏极线侧（主位线的相对侧），主位线通过向其施加0V的电压或根据写入数据的相对较小的电压来选择性地预充电，此后，漏极电流仅施加到所选择的通过将写入电压施加到字线来写入数据的存储器单元，以便将热电子注入浮动栅极。

25. 发明申请

US20050047212A1 Nonvolatile semiconductor storage unit 有权
标题翻译：非易失性半导体存储单元
公开(公告)号：US20050047212A1
公开(公告)日：2005-03-03
申请号：US10501391
申请日：2002-02-28
申请人： Michitaro Kanamitsu , Yoshinori Takase , Shoji Kubono
发明人： Michitaro Kanamitsu , Yoshinori Takase , Shoji Kubono
IPC分类号： G11C16/26 , G11C11/34
CPC分类号： G11C16/26
摘要： A nonvolatile semiconductor storage unit can prevent erratic sense operations in a sense latch circuit by adopting a single-end sensing system capable of reducing an area (decreasing the number of elements). There is provided a flash memory chip using the single-end sensing system and an NMOS gate sensing system together. In the single-end sensing system, the sense latch circuit is connected to one end of a global bit line to detect data on the global bit line corresponding to a threshold voltage for a memory cell. The NMOS gate sensing system uses an NMOSFET to receive data on the global bit line at a gate and drive a node for the sense latch circuit. The NMOSFET senses a sense voltage. The sense latch circuit is activated with a sufficient signal quantity ensured. An output voltage from a threshold voltage applying power supply precharges the global bit line. In this manner, it is possible to always keep a constant difference between a precharge voltage and a threshold voltage for the NMOSFET.
摘要翻译：非易失性半导体存储单元可以通过采用能够减小面积（减少元件数量）的单端感测系统来防止感测锁存电路中的错误检测操作。提供了使用单端感测系统和NMOS栅极感测系统的闪存芯片。在单端感测系统中，感测锁存电路连接到全局位线的一端以检测对应于存储器单元的阈值电压的全局位线上的数据。 NMOS栅极感测系统使用NMOSFET在栅极处的全局位线上接收数据，并驱动用于感测锁存电路的节点。 NMOSFET感测感测电压。感测锁存电路在确保足够的信号量的情况下被激活。来自施加电源的阈值电压的输出电压预充电全局位线。以这种方式，可以始终保持NMOSFET的预充电电压和阈值电压之间的恒定差。

26. 发明授权

US06233174B1 Non volatile semiconductor, memory 有权
标题翻译：非易失性半导体，存储器
公开(公告)号：US06233174B1
公开(公告)日：2001-05-15
申请号：US09539633
申请日：2000-03-30
申请人： Tetsuya Tsujikawa , Atsushi Nozoe , Michitaro Kanamitsu , Shoji Kubono , Eiji Yamamoto , Ken Matsubara
发明人： Tetsuya Tsujikawa , Atsushi Nozoe , Michitaro Kanamitsu , Shoji Kubono , Eiji Yamamoto , Ken Matsubara
IPC分类号： G11C1134
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/3463 , G11C2211/5642
摘要： A nonvolatile semiconductor memory device having a plurality of memory cells. Each cell stores data and has a threshold voltage corresponding to the data. A controller controls a partial erase operation in response to a command. This operation includes selecting memory cells in two groups, storing the data in a data latch, writing erase data indicating an erase state, erasing data of selected cells and programming the data stored in the data latch to selected memory cells and programming the erased data to selected memory cells.
摘要翻译：一种具有多个存储单元的非易失性半导体存储器件。每个单元存储数据并具有对应于数据的阈值电压。控制器响应命令控制部分擦除操作。该操作包括选择两组中的存储单元，将数据存储在数据锁存器中，写入指示擦除状态的擦除数据，擦除所选单元的数据，并将存储在数据锁存器中的数据编程到所选择的存储单元，并将擦除的数据编程为选定的存储单元。

27. 发明授权

US06567315B2 Nonvolatile memory and method of programming the same memory 有权
公开(公告)号：US06567315B2
公开(公告)日：2003-05-20
申请号：US10012549
申请日：2001-12-12
申请人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
发明人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
IPC分类号： G11C1604
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/12
摘要： There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases. In the non-volatile memory of the invention comprising the AND type memory array in which a plurality of memory cells are connected in parallel between the local bit lines and local drain lines, the local drain lines are precharged by supplying thereto a comparatively higher voltage from the common drain line side (opposite side of the main bit lines), the main bit lines are selectively precharged by applying thereto the voltage of 0V or a comparatively small voltage depending on the write data and thereafter a drain current is applied only to the selected memory cells to which data is written by applying the write voltage to the word lines in order to implant the hot electrons to the floating gate.

28. 发明授权

US07072225B2 Nonvolatile memory and method of programming the same memory 失效
公开(公告)号：US07072225B2
公开(公告)日：2006-07-04
申请号：US11168331
申请日：2005-06-29
申请人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
发明人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
IPC分类号： G11C16/04
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/12
摘要： There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases. In the non-volatile memory of the invention comprising the AND type memory array in which a plurality of memory cells are connected in parallel between the local bit lines and local drain lines, the local drain lines are precharged by supplying thereto a comparatively higher voltage from the common drain line side (opposite side of the main bit lines), the main bit lines are selectively precharged by applying thereto the voltage of 0V or a comparatively small voltage depending on the write data and thereafter a drain current is applied only to the selected memory cells to which data is written by applying the write voltage to the word lines in order to implant the hot electrons to the floating gate.

29. 发明授权

US06999348B2 Nonvolatile semiconductor storage unit 有权
标题翻译：非易失性半导体存储单元
公开(公告)号：US06999348B2
公开(公告)日：2006-02-14
申请号：US10501391
申请日：2002-02-28
申请人： Michitaro Kanamitsu , Yoshinori Takase , Shoji Kubono
发明人： Michitaro Kanamitsu , Yoshinori Takase , Shoji Kubono
IPC分类号： G11C11/34
CPC分类号： G11C16/26
摘要： A nonvolatile semiconductor storage unit can prevent erratic sense operations in a sense latch circuit by adopting a single-end sensing system capable of reducing an area (decreasing the number of elements). There is provided a flash memory chip using the single-end sensing system and an NMOS gate sensing system together. In the single-end sensing system, the sense latch circuit is connected to one end of a global bit line to detect data on the global bit line corresponding to a threshold voltage for a memory cell. The NMOS gate sensing system uses an NMOSFET to receive data on the global bit line at a gate and drive a node for the sense latch circuit. The NMOSFET senses a sense voltage. The sense latch circuit is activated with a sufficient signal quantity ensured. An output voltage from a threshold voltage applying power supply precharges the global bit line. In this manner, it is possible to always keep a constant difference between a precharge voltage and a threshold voltage for the NMOSFET.
摘要翻译：非易失性半导体存储单元可以通过采用能够减小面积（减少元件数量）的单端感测系统来防止感测锁存电路中的错误检测操作。提供了使用单端感测系统和NMOS栅极感测系统的闪存芯片。在单端感测系统中，感测锁存电路连接到全局位线的一端以检测对应于存储器单元的阈值电压的全局位线上的数据。 NMOS栅极感测系统使用NMOSFET在栅极处的全局位线上接收数据，并驱动用于感测锁存电路的节点。 NMOSFET感测感测电压。感测锁存电路在确保足够的信号量的情况下被激活。来自施加电源的阈值电压的输出电压预充电全局位线。以这种方式，可以始终保持NMOSFET的预充电电压和阈值电压之间的恒定差。

30. 发明授权

US06333871B1 Nonvolatile semiconductor memory including a controller for providing an improved reprogram operation 有权
标题翻译：非易失性半导体存储器包括用于提供改进的重新编程操作的控制器
公开(公告)号：US06333871B1
公开(公告)日：2001-12-25
申请号：US09539634
申请日：2000-03-30
申请人： Tetsuya Tsujikawa , Atsushi Nozoe , Michitaro Kanamitsu , Shoji Kubono , Eiji Yamamoto , Ken Matsubara
发明人： Tetsuya Tsujikawa , Atsushi Nozoe , Michitaro Kanamitsu , Shoji Kubono , Eiji Yamamoto , Ken Matsubara
IPC分类号： G11C1604
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/3463 , G11C2211/5642
摘要： Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.
摘要翻译：外部提供的程序数据被锁存到数据锁存电路DLL和DLR中。在执行多个编程操作的每一次时，判定所锁存的程序数据是否对应于多级的任何阈值。与判断结果相对应的程序控制信息被锁存在读出锁存电路SL中。基于锁存的程序控制信息，以逐步的方式执行用于将具有多级的阈值电压设置到存储器单元的编程操作。即使编程操作结束，外部提供的程序数据也留在数据锁存电路中。即使由于过度编程条件而重试存储器单元的编程操作，也不再需要再次从外部设备接收程序数据。

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