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热词
    • 21. 发明授权
    • Semiconductor device in which capacitance of a MOS capacitor is complemented with the capacitance of a wiring capacitor
    • MOS电容器的电容与布线电容器的电容互补的半导体器件
    • US07557400B2
    • 2009-07-07
    • US11670605
    • 2007-02-02
    • Osamu WadaHiroaki NakanoHiroshi ItoToshimasa NamekawaAtsushi Nakayama
    • Osamu WadaHiroaki NakanoHiroshi ItoToshimasa NamekawaAtsushi Nakayama
    • H01L27/108H01L29/00
    • H01L29/94H01L23/5223H01L27/0222H01L2924/0002H02M3/073H01L2924/00
    • A semiconductor device has a MOS capacitor in which a drain region and a source region of a MOS structure are commonly connected, and a capacitance is formed between the commonly connected drain region/source region and a gate electrode of the MOS structure; and a wiring capacitor which has a first comb-shaped wiring that is formed on said MOS capacitor through an interlayer insulating film, is connected to the gate electrode of said MOS capacitor, and has projecting portions projecting like comb teeth and a second comb-shaped wiring that is formed on said MOS capacitor through the interlayer insulating film, is arranged across an inter-line insulating film from the first comb-shaped wiring, is connected to the drain region and source region, and has projecting portions projecting like comb teeth, wherein the projecting portions of the second comb-shaped wiring are arranged alternately with the projecting portions of the first comb-shaped wiring and arranged perpendicularly to a channel direction connecting the drain region and source region of said MOS capacitor.
    • 半导体器件具有其中共同连接漏极区域和MOS结构的源极区域的MOS电容器,并且在共同连接的漏极区域/源极区域和MOS结构的栅极电极之间形成电容; 以及具有通过层间绝缘膜形成在所述MOS电容器上的第一梳状布线的布线电容器连接到所述MOS电容器的栅电极,并且具有突出部分,如梳齿形状突出,第二梳状 通过层间绝缘膜在所述MOS电容器上形成的布线跨越与第一梳状布线的线间绝缘膜布置,连接到漏区和源极区,并且具有突出部分如梳齿突出, 其中,所述第二梳状布线的突出部分与所述第一梳状布线的突出部分交替布置,并且垂直于连接所述MOS电容器的漏极区域和源极区域的沟道方向布置。
    • 22. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20070181918A1
    • 2007-08-09
    • US11670605
    • 2007-02-02
    • Osamu WADAHiroaki NakanoHiroshi ItoToshimasa NamekawaAtsushi Nakayama
    • Osamu WADAHiroaki NakanoHiroshi ItoToshimasa NamekawaAtsushi Nakayama
    • H01L29/76
    • H01L29/94H01L23/5223H01L27/0222H01L2924/0002H02M3/073H01L2924/00
    • A semiconductor device has a MOS capacitor in which a drain region and a source region of a MOS structure are commonly connected, and a capacitance is formed between the commonly connected drain region/source region and a gate electrode of the MOS structure; and a wiring capacitor which has a first comb-shaped wiring that is formed on said MOS capacitor through an interlayer insulating film, is connected to the gate electrode of said MOS capacitor, and has projecting portions projecting like comb teeth and a second comb-shaped wiring that is formed on said MOS capacitor through the interlayer insulating film, is arranged across an inter-line insulating film from the first comb-shaped wiring, is connected to the drain region and source region, and has projecting portions projecting like comb teeth, wherein the projecting portions of the second comb-shaped wiring are arranged alternately with the projecting portions of the first comb-shaped wiring and arranged perpendicularly to a channel direction connecting the drain region and source region of said MOS capacitor.
    • 半导体器件具有其中共同连接漏极区域和MOS结构的源极区域的MOS电容器,并且在共同连接的漏极区域/源极区域和MOS结构的栅极电极之间形成电容; 以及具有通过层间绝缘膜形成在所述MOS电容器上的第一梳状布线的布线电容器连接到所述MOS电容器的栅电极,并且具有突出部分,如梳齿形状突出,第二梳状 通过层间绝缘膜在所述MOS电容器上形成的布线跨越与第一梳状布线的线间绝缘膜布置,连接到漏区和源极区,并且具有突出部分如梳齿突出, 其中,所述第二梳状布线的突出部分与所述第一梳状布线的突出部分交替布置,并且垂直于连接所述MOS电容器的漏极区域和源极区域的沟道方向布置。
    • 23. 发明申请
    • Nonvolatile semiconductor memory device
    • 非易失性半导体存储器件
    • US20060158923A1
    • 2006-07-20
    • US11221943
    • 2005-09-09
    • Toshimasa NamekawaHiroaki NakanoHiroshi ItoAtsushi NakayamaOsamu Wada
    • Toshimasa NamekawaHiroaki NakanoHiroshi ItoAtsushi NakayamaOsamu Wada
    • G11C11/24
    • G11C5/145G11C17/16G11C17/18
    • A nonvolatile semiconductor memory device includes a storage element which is programmed with information by breaking an insulating film by application of electrical stress to the storage element, a control switch which controls the application of electrical stress to the storage element, and a control circuit which controls conduction/nonconduction of the control switch. The device further includes a power supply circuit including a voltage generation circuit which generates a first voltage to cause the electrical stress in program operation, a sensing circuit which senses that the insulating film is broken down, and a counter circuit which controls the control circuit to interrupt the application of electrical stress to the storage element when a given period of time elapses after the sensing circuit senses that the insulating film is broken down.
    • 一种非易失性半导体存储器件,包括通过对存储元件施加电应力而破坏绝缘膜的信息来编程的存储元件,控制对存储元件施加电应力的控制开关,以及控制电路 导通/非导通控制开关。 该装置还包括电源电路,该电源电路包括产生第一电压以在编程操作中产生电应力的电压产生电路,感测绝缘膜分解的感测电路,以及控制电路控制到 在感测电路感测到绝缘膜破裂之后经过给定的时间段时,中断对存储元件的电应力的施加。
    • 25. 发明授权
    • Dynamic semiconductor memory device
    • 动态半导体存储器件
    • US5629887A
    • 1997-05-13
    • US429638
    • 1995-04-27
    • Hiroaki NakanoDaisaburo TakashimaTohru Ozaki
    • Hiroaki NakanoDaisaburo TakashimaTohru Ozaki
    • G11C11/4097H01L23/522H01L27/108G11C5/02G11C5/06
    • G11C11/4097H01L23/5222H01L27/10805H01L2924/0002
    • A dynamic semiconductor memory device according to the present invention, comprises a plurality of first bit lines, a plurality of second bit lines which are partially laminated above the first bit lines and, together with the first bit lines, form bit-line pairs to build a folded bit-line structure, a plurality of word lines arranged so as to cross the first bit lines and the second bit lines, and at least one memory cell array in which a plurality of memory cells connected to the first bit lines and the second bit lines are arranged in a matrix, wherein the memory cell array includes a plurality of first areas in which a plurality of memory cells are arranged, and a plurality of second memory areas which are arranged so as to alternate with the first areas and contain no memory cell, and the second memory areas include areas where the first bit lines of the specified number of the bit-line pairs are connected to the second bit lines and the second bit lines are connected to the first bit lines.
    • 根据本发明的动态半导体存储器件包括多个第一位线,多个第二位线,其部分地层叠在第一位线上方,并与第一位线一起形成位线对以构建 折叠的位线结构,布置成跨越第一位线和第二位线的多个字线,以及至少一个存储单元阵列,其中多个存储单元连接到第一位线和第二位线 位线布置成矩阵,其中存储单元阵列包括多个第一区域,其中布置有多个存储单元;以及多个第二存储区域,其布置成与第一区域交替并且不包含 存储单元,并且第二存储器区域包括指定数量的位线对的第一位线连接到第二位线的区域,并且第二位线连接到第一位线 位线。