专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07911871B2 Semiconductor memory device operational processing device and storage system 有权
标题翻译：半导体存储器件操作处理装置和存储系统
公开(公告)号：US07911871B2
公开(公告)日：2011-03-22
申请号：US12461743
申请日：2009-08-24
申请人： Hideto Hidaka
发明人： Hideto Hidaka
IPC分类号： G11C8/00
CPC分类号： G11C11/005
摘要： A thin film magnetic memory includes a size-variable Read Only Memory (ROM) region and a size-variable Random Access Memory (RAM) coupled to different ports for parallel access to the ports, respectively. A memory system allowing fast and efficient data transfer can be achieved.
摘要翻译：薄膜磁存储器包括大小可变只读存储器（ROM）区域和耦合到不同端口的大小可变随机存取存储器（RAM），用于并行地访问端口。可以实现快速高效的数据传输的存储器系统。

22. 发明授权

US07741869B2 Low power consumption MIS semiconductor device 有权
标题翻译：低功耗MIS半导体器件
公开(公告)号：US07741869B2
公开(公告)日：2010-06-22
申请号：US12010427
申请日：2008-01-24
申请人： Hideto Hidaka
发明人： Hideto Hidaka
IPC分类号： H03K19/096 , H03K17/16 , H03K19/003
CPC分类号： G11C5/147 , H01L27/0922 , H03K19/0016
摘要： A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized.
摘要翻译：逻辑门由具有薄栅绝缘膜的绝缘栅场效应晶体管（MIS晶体管）构成。提供到逻辑门的操作电源线设置有具有用于切换供电和停止操作电源电压的厚栅极绝缘膜的MIS晶体管。使电源开关晶体管的栅极的电压以大于输入的幅度和输出信号的幅度变化为逻辑门。可以减小由薄栅绝缘膜的MIS晶体管构成的半导体器件中的电流消耗，并且其电源电压可以稳定。

23. 发明授权

US07652912B2 Nonvolatile semiconductor memory device performing data writing in a toggle manner 失效
标题翻译：非易失性半导体存储器件以切换方式执行数据写入
公开(公告)号：US07652912B2
公开(公告)日：2010-01-26
申请号：US11520563
申请日：2006-09-14
申请人： Tomoya Kawagoe , Jun Otani , Hideto Hidaka
发明人： Tomoya Kawagoe , Jun Otani , Hideto Hidaka
IPC分类号： G11C11/00
CPC分类号： G11C11/15
摘要： A nonvolatile semiconductor memory device includes a free layer having first and second magnetic layers magnetized oppositely to each other, and also having a first nonmagnetic layer formed between the first and second magnetic layers, a first fixed layer having a fixed magnetization direction, a second nonmagnetic layer formed between the second magnetic layer and the first fixed layer, a first drive circuit passing a write current through a first write current line in a data write operation, and thereby generating a data write magnetic field acting on magnetization of the free layer, and a second drive circuit passing a spin injection current between the first magnetic layer and the first fixed layer in a data write operation, and thereby exerting a force in the same direction as or in the direction opposite to the magnetization direction of the first fixed layer on the magnetization of the free layer.
摘要翻译：非易失性半导体存储器件包括具有彼此相对磁化的第一和第二磁性层的自由层，并且还具有形成在第一和第二磁性层之间的第一非磁性层，具有固定的磁化方向的第一固定层，第二非磁性层形成在第二磁性层和第一固定层之间的第一驱动电路，在数据写入操作中使写入电流通过第一写入电流线的第一驱动电路，从而产生作用于自由层的磁化的数据写入磁场;以及第二驱动电路在数据写入操作中在第一磁性层和第一固定层之间通过自旋注入电流，从而在与第一固定层的磁化方向相反的方向上施加力或者在与第一固定层的磁化方向相反的方向上施加力自由层的磁化。

24. 发明申请

US20090262575A1 THIN FILM MAGNETIC MEMORY DEVICE CAPABLE OF CONDUCTING STABLE DATA READ AND WRITE OPERATIONS 失效
标题翻译：能够进行稳定数据读取和写入操作的薄膜磁性存储器件
公开(公告)号：US20090262575A1
公开(公告)日：2009-10-22
申请号：US12494725
申请日：2009-06-30
申请人： Hideto Hidaka
发明人： Hideto Hidaka
IPC分类号： G11C11/14 , G11C7/02
CPC分类号： H01L27/228 , G11C7/14 , G11C11/16 , G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , H01L27/224
摘要： A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic layers in a tunnel junction region. In the free magnetic layer, a region corresponding to an easy axis region having characteristics desirable as a memory cell is used as the tunnel junction region. A hard axis region having characteristics undesirable as a memory cell is not used as a portion of the tunnel magnetic resistive element.
摘要翻译：形成磁存储单元的隧道磁阻元件包括具有固定方向的固定磁场的固定磁性层，由施加的磁场磁化的自由磁性层和作为绝缘膜的隧道势垒，所述绝缘膜设置在固定和隧道结区域中的自由磁性层。在自由磁性层中，使用对应于具有作为存储单元的特性的容易轴区域的区域作为隧道结区域。具有作为存储单元的不期望的特性的硬轴区域不被用作隧道磁阻元件的一部分。

25. 发明授权

US07567454B2 Thin film magnetic memory device capable of conducting stable data read and write operations 有权
公开(公告)号：US07567454B2
公开(公告)日：2009-07-28
申请号：US12081153
申请日：2008-04-11
申请人： Hideto Hidaka
发明人： Hideto Hidaka
IPC分类号： G11C11/15 , G11C11/00 , G11C7/02 , G11C11/14
CPC分类号： H01L27/228 , G11C7/14 , G11C11/16 , G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , H01L27/224
摘要： A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic layers in a tunnel junction region. In the free magnetic layer, a region corresponding to an easy axis region having characteristics desirable as a memory cell is used as the tunnel junction region. A hard axis region having characteristics undesirable as a memory cell is not used as a portion of the tunnel magnetic resistive element.

26. 发明申请

US20080225582A1 Thin film magnetic memory device capable of conducting stable data read and write operations 有权
标题翻译：能够进行稳定数据读写操作的薄膜磁存储器件
公开(公告)号：US20080225582A1
公开(公告)日：2008-09-18
申请号：US12081153
申请日：2008-04-11
申请人： Hideto Hidaka
发明人： Hideto Hidaka
IPC分类号： G11C11/14
CPC分类号： H01L27/228 , G11C7/14 , G11C11/16 , G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , H01L27/224
摘要： A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic layers in a tunnel junction region. In the free magnetic layer, a region corresponding to an easy axis region having characteristics desirable as a memory cell is used as the tunnel junction region. A hard axis region having characteristics undesirable as a memory cell is not used as a portion of the tunnel magnetic resistive element.
摘要翻译：形成磁存储单元的隧道磁阻元件包括具有固定方向的固定磁场的固定磁性层，由施加的磁场磁化的自由磁性层和作为绝缘膜的隧道势垒，所述绝缘膜设置在固定和隧道结区域中的自由磁性层。在自由磁性层中，使用对应于具有作为存储单元的特性的容易轴区域的区域作为隧道结区域。具有作为存储单元的不期望的特性的硬轴区域不被用作隧道磁阻元件的一部分。

27. 发明授权

US07394685B2 Nonvolatile memory device with write error suppressed in reading data 有权
标题翻译：在读取数据时抑制写入错误的非易失性存储器件
公开(公告)号：US07394685B2
公开(公告)日：2008-07-01
申请号：US11582983
申请日：2006-10-19
申请人： Tsukasa Ooishi , Hideto Hidaka
发明人： Tsukasa Ooishi , Hideto Hidaka
IPC分类号： G11C11/14
CPC分类号： G11C11/16
摘要： A data write current from a pinned layer to a free layer is larger than a data write current from the free layer to the pinned layer. A data read current is smaller in value than the data write current. In the case where a difference in data read current between a high-resistance state and a low-resistance state is relatively small, a sense amplifier is connected so that the data read current flows from the pinned layer to the free layer, namely from a source line to a bit line.
摘要翻译：从固定层到自由层的数据写入电流大于从自由层到被钉扎层的数据写入电流。数据读取电流的值比数据写入电流小。在高电阻状态和低电阻状态之间的数据读取电流的差异相对较小的情况下，连接读出放大器，使得数据读取电流从固定层流向自由层，即从源线到位线。

28. 发明授权

US07256644B2 Semiconductor circuit device having hierarchical power supply structure 有权
标题翻译：具有分层电源结构的半导体电路装置
公开(公告)号：US07256644B2
公开(公告)日：2007-08-14
申请号：US10628384
申请日：2003-07-29
申请人： Tsukasa Ooishi , Hideto Hidaka
发明人： Tsukasa Ooishi , Hideto Hidaka
IPC分类号： G05F1/10
CPC分类号： G11C5/063 , G11C5/14 , G11C5/144 , G11C5/147 , G11C2207/2227 , Y10T307/391 , Y10T307/461 , Y10T307/696 , Y10T307/724 , Y10T307/747
摘要： Resistance elements are inserted into a main power supply line and a main ground line so that offset differential amplifiers receive voltages developed across the same. The differential amplifiers control transistors connected to a sub power supply line and a sub ground line. Thus, a leakage current flowing from the sub power supply line to the main ground line and that flowing from the main power supply line to the sub ground line are regularly kept constant. Consequently, it is possible to prevent an operation delay in an initial stage of a standby state while keeping an effect of reducing a subthreshold leakage current in a semiconductor circuit device having a hierarchical power supply structure.
摘要翻译：电阻元件插入主电源线和主接地线，使得偏移差分放大器接收在其上产生的电压。差分放大器控制连接到副电源线和次接地线的晶体管。因此，从副电源线流向主接地线并从主电源线流向副接地线的漏电流规则地保持恒定。因此，可以在保持具有分级供电结构的半导体电路装置中降低亚阈值泄漏电流的效果的同时防止在待机状态的初始阶段的操作延迟。

29. 发明授权

US07254057B2 Magnetic thin-film memory device for quick and stable reading data 有权
标题翻译：磁性薄膜记忆装置，用于快速，稳定地读取数据
公开(公告)号：US07254057B2
公开(公告)日：2007-08-07
申请号：US10891109
申请日：2004-07-15
申请人： Hideto Hidaka
发明人： Hideto Hidaka
IPC分类号： G11C11/14
CPC分类号： H01L27/228 , G11C8/08 , G11C11/15 , G11C11/16
摘要： An MTJ memory cell is independently provided with a write word line and a read word line used for data write and data read. By separately arranging read word lines every two regions formed by dividing a memory array in the column direction, it is possible to reduce signal propagation delays of the read word lines and accelerate the data read operation. Activation of each read word line is controlled by a write word line in accordance with a row selection result in a hierarchical manner. A word-line-current control circuit forms and cuts off the current path of a write word line correspondingly to data write and data read.
摘要翻译： MTJ存储单元独立地具有用于数据写入和数据读取的写字线和读字线。通过在列方向上划分存储器阵列形成的每两个区域分开布置读取字线，可以减少读取字线的信号传播延迟并加速数据读取操作。每个读取字线的激活根据分层方式的行选择结果由写入字线控制。字线电流控制电路对应于数据写入和数据读取形成并切断写入字线的当前路径。

30. 发明申请

US20070132488A1 Data output circuit with reduced output noise 审中-公开
标题翻译：数据输出电路具有降低的输出噪声
公开(公告)号：US20070132488A1
公开(公告)日：2007-06-14
申请号：US11704916
申请日：2007-02-12
申请人： Hideto Hidaka , Masakazu Hirose
发明人： Hideto Hidaka , Masakazu Hirose
IPC分类号： H03B1/00
CPC分类号： H03K19/00361
摘要： A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused. A stable output signal is provided at high speed.
摘要翻译：当内部节点的电位达到H电平时，数据输出驱动晶体管导通，从而将输出节点放电到地电位。当驱动晶体管导通时，输出节点以高速放电到地电位。当高电平数据的输出完成时，该驱动晶体管导通预定时间段，由此输出节点在预定时间段内被放电到地电位的电平。结果，输出节点的电位从高电平降低到中间电平，使得后续输出信号的幅度减小。提供了可以有效地防止产生振铃而不增加访问时间的输出电路。提供了一种对策，用于当输出节点电位达到不产生振铃的电位时，抑制在输出节点处高速驱动输出节点的振铃。高速提供稳定的输出信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式